2. basics of packet switching

8/13/2019 2. Basics of Packet Switching

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2014/1/13 1

Chapter 2

Basics of Packet Switching



2014/1/13 3

Router Physical Configuration

1 12

S Y N C

Fan

4N

2N

2N M C

2 3 4 5 6 7 8 9 10 11

3 4 1 2

1 2 6 5 13 14

R C

E \ F S C S W

- A c t i v e

S W

- S t a n d b y

L I 1

L I 2

L I 3

L I 4

L I 5

L I 6

L I 7

L I 8

MC-Main Controller

RC-Route Controller

SYNC-Sync/Clk

E/FSC-Ethernet switch/File System Controller



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Generic Router Operations

Packet Switching is the transport of packets/cellsfrom an input interface to an output interface

Packets arrive at the line interface

Header look up, switching translation and decisionare performed

Packets are switched through, or queued at outputinterface



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X

Generic Router Architecture

Network

Processor

MemoryMemory

SPI-4

Egress

TrafficManagement

Ingress

Traffic

Management16

16

10Gbps

traffic

SwitchFabric

FramerO/E,

E/O

Line Interface



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Ingress Line Interface

OC-

192c

10G

Connector

16 64

16 LVDS @ 622 Mhz

10G

CSIX

64 HSTL @ 200 - 250

Mhz

Aggregate = ~13G

SDRAM CAM

~7 optical @ ~2G

Aggregate = ~13G

Qty 7

10:1

SERDE

S

(approx)

Control

microprocessor To/From

Shelf Control Processor

Network

Processor

(e.g. ezchip)

Framer

(e.g. AMCC

GANGES)

SPI-4

64 HSTL @ 175 Mhz

Aggregate = 10G

64

OC-192c

Transponder(e.g. Lightlogic)

PCI

32-bi

t @

66 MHz

Switch

Fabric


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Why Do We Need High-performance Routers? Prevent routers becoming the bottleneck in the Internet

(DWDM provides huge transmission bandwidth)

Increase POP (point of presence) capacity, and to reduce

cost, size and power.

.

POP with smaller routersPOP with large routers

• Ports: Price >$100k, Power > 400W.

• It is common for 50-60% of ports to be for interconnection.


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A Case study: UUNET Internet Backbone Build Up

1999 View (4Q)

• 8 OC-48 links between POPs (notparallel)

2000 View (4Q)

• 52 OC-48 links between POPs: many parallel links

• 3 OC-192 Super POP links: multiple parallel interfacesbetween POPs (D.C. – Chicago; NYC – D.C.)

To Meet the traffic growth, Higher Performance Routers withHigher Port Speed, are required



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Wire-speed Per-packet Processing

Accept packet arriving on an incoming link

Classify packet into different flow in order to provide security,different QoS, etc.

Lookup packet destination address in the forwarding table, toidentify outgoing port(s)

Manipulate packet header: e.g., decrement TTL, updateheader checksum

Send packet to the outgoing port(s)

Buffer packet in the queue

Transmit packet onto outgoing link

Problems more under-defined protocol standards

Hard to maintain per-packet state that comes and goes

Too many exceptions are handled by software



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IP Address Lookups Find Longest Prefix Match

Routing table contains (Prefix, Next Hop)

pairs Packet destination address compares to

prefix, starting from the left

Prefix that match longest address bits isdesired match

Packet is forwarded to the specified nexthop

For example - address :10110010100000110011100110010000

10* 611* 7110* 51011* 30100* 2

01011* 1100001* 0001100* 11011001* 41011010* 30100110* 701001101* 1010110011* 910010000* 801011001* 7

v



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Why IP Lookup Is Difficult

IP lookup must be fast - available processing timeis 32ns per packet for 10Gbps port (24Millionminimum-size packets (40bytes) per sec)

Lookup table is large – core router has more than10,000 prefix entries today, and 1 million prefix

entries in the future

IP lookup based on best variable length prefixmatch and thus complex routing



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Speed of Commercial DRAM

The bottleneck is memory speed.

Memory speed is not keeping up with Moore’s

Law.

0.001

0.01

0.1

1

10

100

1000

1980 1983 1986 1989 1992 1995 1998 2001

A c c e

s s T i m e

( n s

Moore’s Law

2x / 18 months

1.1x / 18 months



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DRAM

Dense memory

Current generation is 1Gbit

Store value on very small capacitors

New generation every 3-4 years

Features shrink 0.7 each generation, 2x in area

Density is growing 4x in a generation

Cell efficiency is hard to improve, so chips aregetting larger

Not fastest, but cheap

New development of faster memory such as Rambus,DDR, and QDR.



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SRAM vs. DRAM

High Throughputs – wide datapaths running at highclock rate

Low Density (Expensive) – SRAM 4X to 6X morearea per bit than DRAM



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Internal Blocking in a Delta Network: Two Cells Destined forOutput Ports 4 and 5 Collide



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Output Port Contention

• Output port contention, resulting in arbitration and buffering, is

a major challenging problem when building a packet switch.



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Head of Line (HOL) Blocking

• Maximum throughput is limited to 58.6% due to HOL blocking.



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Call Scheduling Disciplines in Multicasting



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Shared-Medium Switching Architecture



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A 44 Crossbar Switch



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Different Buffering Strategies for a Crossbar Switch



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Problem Definition

A generic crossbar switch engine:

Capacity Requirement: Given line rates R and fan-outof N , need an aggregate throughput of AT=NR

QoS Requirement: Offer various levels of service suchas priorities, guaranteed bandwidth and delay toidentified flows

Line 1

Line 2

Line N

pp

pp

pp

CROSSBAR

SWITCH

Line 1

Line 2

Line N

Packet processors



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Input buffered Crossbars (cont’d)

Advantages: Memory bandwidth required = AT/N = R

Disadvantages:

Crossbar blocking: is optimal matching enough?

Frequency and complexity of centralizedarbitration does not scale with size and interfacerates

How to guarantee switch-wide QoS to individual

flows: Arbitration determines observed bandwidth Difficult to implement multicast



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Combined Input Output Queueing (CIOQ)

Crossbars with speedup:

Goal: Get close to optimal matching

Example:iSLIP arbitration

Maximal weight matching yields 100% throughput for uniformthroughput with log N iteration

Maximal size matching yields optimal throughput with aspeedup of 2 - 1/N

X1

N

1

N

Arbiter



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CIOQ(cont’d) Retro-fitting QoS

Hierarchical scheduler in the input buffers

Centralized arbitration: Template based approach(use iSLIP for extra bandwidth)

Distributed arbitration: additional speedup and

backpressure from output to input buffers Remaining issues:

Even through worst case QoS is attainable, QoSstill does not match a pure output buffered switch

as crossbar arbitration dominates



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Constraining Factors

Memory bandwidth

Contention points versus memory size

Frequency and complexity of scheduling

Rate of transfer from input to output (speedup

factor) Frequency and complexity of arbitration



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A Fully Interconnected Switch



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Knockout Switch Bus Interface



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Three Different Topologies of Banyan-Based Switches



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A Clos Switch Configuration

i j



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Routing Constraint in Clos-Network Switch

Example of Internal Blocking in a Three-Stage



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a p e o te a oc g a ee StageClos Switch

Nonblocking Condition for a Three-Stage Clos



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g gSwitch



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Buffering Strategies for ATM Switches



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Virtual Output Queue (VOQ) at the Input Ports

The Maximum Throughput Achievable Using



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g p gInput Queuing with FIFO Buffer

The Mean Waiting Time for Input Queuing with FIFO



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The Mean Waiting Time for Input Queuing with FIFOBuffers for the Limiting Case for N =

The Cell Loss Probability for Output Queuing as a Function of the Buffer



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The Cell Loss Probability for Output Queuing as a Function of the BufferSize b and the Switch Size N , for Offered Loads (a) p = 0.8 (b) p = 0.9

The Cell Loss Probability for Output Queuing as a Function of the BufferSize b and Offered Loads Varying from p = 0 70 to p = 0 95 for the



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Size b and Offered Loads Varying from p = 0.70 to p = 0.95, for thelimiting case N =

The Mean Waiting Time for output Queuing as a Function of the Offered



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The Mean Waiting Time for output Queuing as a Function of the Offered

Load p , for N = and Output FIFO Sizes Varying from b =1 to b =

The Cell Loss Probability for Completely Shared Buffering as a Functionof the Buffer Size per Output b and the Switch Size N for Offered Loads



of the Buffer Size per Output b and the Switch Size N , for Offered Loads(a) p = 0.8 (b) p = 0.9

2. basics of packet switching

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