1st IAA Latin American Symposium on

Small Satellites: Advanced Technologies

and Distributed Systems

Novel Methodology for using Latest Technology

Electronic Components in Space

“The person who says it cannot be done should not interrupt the person doing it” Chinese Proverb

Eng. Roberto M. CIBILS rcibils@invap.com.ar INVAP

PARTS SELECTION USUAL

PRACTICES

Use “as is”

Maximum risk of mission failure

Very cheap and fast supply

Upscreening

Risk of failing qualification

More expensive than “space qualified”

The more demanding environmental requirements, the lower the size of the accepted batch; if any

RISK MANAGEMENT

BASED SELECTION

Risk analysis

Risk mitigation

Risk assessment

RISK ANALYSIS

Vulnerabilities in Design

Reliability Paradox

Vulnerabilities in Design

Reliability paradox

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 2 4 6 8 10 12 14

Pro

bab

ilit

y

Time [years]MTTF

Pf=1-e-t/MTTF ; r=e-tmission/MTTF

Vulnerabilities in Design

Reliability paradox

Metalic Strip Cross-Section

Electromigration

Blacks Equation

Mathematical Model for Lifetime

A: Cross-section area dependent constant

J: Current Density

N: Scaling factor, usually set to 2

Ea: Activation Energy for electromigration

K: Boltzmann constant

T: Temperature

Pay attention to the EXPONENTIAL dependence with

temperature

Tk

E

J

ALifetime

a

Nexp

Oxide Thickness

Time Dependent Dielectric Breakdown (TDDB)

Negative Bias Thermal Instability (NBTI)

Hot Carrier Injection (HCI)

In ALL of them Lifetime depends EXPONENTIALLY with temperature

Solder Contacts

BGA and CCGA Packages

Coffin-Manson

Vulnerabilities & Failures

Phases

Vulnerabilities generation: Ground

Failure occurrence: Space

Vulnerabilities Generation

During design

Metalic strips size

Oxide thickness

Solder contacts

During manufacturing

Die

Bonding

Contacts

Packages

During other phases

Transport

Storage

Handling

Assembly & Tests

Vulnerabilities Generated in other

Phases

Permeability, Delamination, Ionic contamination, Corrosion

Electrostatic Discharge

RISK MITIGATION

Preemtive (delay) strategy

Failure mitigation strategy

FAULT PREEMPTION

Wear Out by Ground Induced

Vulnerabilities

SPECIAL PROCEDURES

For procurement

For reception

For storage

For assembly

For test

Wear Out by the Space Environment

TOTAL IONIZING DOSE (TID)

WEAR OUT MITIGATION:

Spot Shielding

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

1.00E+01

1.00E+02

1.00E+03

1.00E+04

1.00E+05

1.00E+06

1.00E+07

0 5 10 15 20 25 30 35 40 45 50

TID

(rad

)

mm de aluminio

DDC- Multi-misión

Electrones atrapadosProtones atrapadosProtones solares

Protones Oct-89

Fotones

Total

Wear Out by

TEMPERATURE Board Level

High Thermal Conductivity Coating

Heat flowing through the thermal coating compensates the lack of convection in space.

Box Level

Phase Change Materials

Paraffin Heat Switches

System Level

Variable Surface Radiators

Loop Heat Pipes

Wear Out by

THERMAL CYCLES Lifetime extension techniques for BGA and CCGA packages

(use of fillers ó micro-coil springs)

FAULT MITIGATION

Radiation induced failure modes of

random occurrence

Latch Up

SEU/SEFI

LATCH UP MITIGATION

SEL-triggered Power Switchs

Use of fast-acting over-current sensing power switches to give a degree of protection against damage from SEL.

SEL susceptibility depends on silicon junction temperature. Reducing the operating temperature range reduces the latch up risk,

SEU MITIGATION by SW

EDAC and TTMR

Repetition codes

Parity bits

Checksums

Cyclic Redundancy Checks (CRCs)

Cryptographic hash functions

Error-correcting codes

Time Triple Modular Redundancy

SEFI MITIGATION

WATCH DOG Lockstep Checkpointing

Roll back

Example: TI TMS570 series

RISK

ASSESSMENT

Risk Assessment

By

pro

cess

By

anal

ysis

By

de

sign

(p

art)

By

de

sign

(b

oar

d)

By

de

sign

(Sy

ste

m)

By

test

Re

curr

ing

cost

[U

$S]

Re

curr

ing

tim

e

[mo

nth

s]

Occ

urr

en

ce

pro

bab

ility

(be

fore

mit

igat

ion

)O

curr

en

ce

pro

bab

ility

(aft

er

mit

igat

ion

)

Seve

rity

Ris

k

(be

fore

mit

igat

ion

)

Ris

k

(aft

er

mit

igat

ion

)

Delamination

Cracks in the passivation layer

Cracks in the die

Ionic contamination

Moisture condensation

Corrosion

Outgassing

Popcorning

Intermetalic compound in the bonding

Tin wiskers

Overheating

Infant mortality

Degraded ball bonds

Wire sweep

Shorts, floating nodes

Fatigue of solder joints

Electromigration

Mitigation Figures of Merit

IC Code Number

Re

leva

nce

Failure mode

CONCLUSIONS

The use of “space qualified” electronic components produce systems with higher mass-volume, higher power consumption, and lower performance than those produced using mass market driven commercial quality electronic components.

The “use as is” strategy for using electronic components of commercial quality level is risky

The use of “up-screening” for qualifying COTS for space missions is expensive and produce the risk of failing in satisfying the mission requirements.

A better strategy can be applied by analyzing and mitigating the vulnerabilities of electronic parts.

For this, it is necessary to develop a “toolbox” of specific mitigation techniques for the critical failure modes of the components of interest. The development of this toolbox has to be a project itself an not be embedded at the shadow of one particular space mission.

QUESTIONS?

References

[1] D. Cadbury, "Space Race: The Epic Battle Between America and the Soviet Union for Dominion of Space", Ed. HarperCollins (2005)

[2] L. Hamiter, "The History of Space Quality EEE Parts in the United States", ESA Electronic Components Conference, ESTEC, Noordwijk, The Netherlands (12 - 16 November, 1990)

[3] F. Chiavassa, "MIL System Overview - EEE Parts", CCT Composants Conference (Nov 2004).

[4] "Small Satellites: A Revolution in Space Science", Final Report, Keck Institute for Space Studies California Institute of Technology Pasadena, CA (July 2014)

[5] https://terrabella.google.com/

[6] D. Sinclair, J. Dyer, "Radiation Efects and COTS Parts in SmallSats ", 27th Annual AIAA/USU Conference on Small Satellites, (August 10-15, 2013)

[7] A. Shao, E. Koltz, J. Wertz, "Quantifying the Cost Reduction Potential for Earth Observation Satellites", 12th Reinventing Space Conference, London - UK (18-20 November, 2014)

[8] NASA, EEE-INST-002: Instructions for EEE Parts Selection, Screening, Qualification, and Derating.

References

[9] J. Plante, M. Sampson, Cost Impacts of Upgrading Electronic Parts for Use in NASA Space Flight Systems, NASA Goddard Space Flight Center. Available in web: https://nepp.nasa.gov/ DocUploads/3F0EA425-5267-4A18-8E99EAEF6BF3A1B7/Cost%20Impacts%20of%20Upgradi ng%20Electronic%20Parts%20for%20Use%20in%20NASA%20Space%20Flight%20Systems.pdf

[10] ESA, ECSS-Q-ST-60C, Electrical, electronic and electromechanical (EEE) components.

[11] R.L. de Orio, H. Ceric, S. Selberherr, "Physically based models of electromigration: From Black’s equation to modern TCAD models", Microelectronics Reliability, Vol. 50, pp. 775–789 (2010)

[12] S. Salemi, L. Yang, J. Dai, J. Qin, J. Bernstein, "Physics-of-Failure Based Handbook of Microelectronic Systems", RiAC, University of Maryland.

[13] R. Cibils, "Radiation Tolerance Evolution of CMOS Integrated Circuits", 1st IAA Latin American Symposium on Small Satellites: Advanced Technologies and Distributed Systems (Feb 7-10, 2017)

[14] R. Cibils, "Small Satellites Hardened by Design for the use of Non-Space Qualified EEE Parts", 2014 NEPP EEE Parts for Small Missions Workshop, GSFC (Sep 10-11, 2014)

BACK UP

INTRODUCTION

SPACE ACTIVITY

ORIGIN:

Objectives: strategic, military

Budget: Unlimited

Quality of EEE parts: Space

TODAY: Universities

Objetive : human resource

Budget: Very low

Quality of EEE parts: COTS

Spin offs

Objetive : profit

Budget: Very low

Quality of EEE parts: SPACE/COTS

WHY USING COTS?

WHY USING COTS?

WHY USING COTS?

SPACE QUALIFIED COTS

TRANSCEIVER A full PCB is required to fulfill

this function

ANALOG DEVICES

AD9361

CMOS - 65 nm

Single chip 10 x 10 mm

PROCESSOR

AEROFLEX

LEON 3 - DUAL CORE

CMOS - 180 nm

134 DMIPS

NXP

SoC Processors i.MX7

CMOS 28 nm FD-SOI

1570 DMIPS

MEMORY

3DPLUS

3DFN064G08VB1388

CMOS NAND FLASH

Stack 8 x 8 (64) Gbits

MICRON

MT29F512G08AUEBBH8-12

CMOS 3D NAND FLASH

512 Gbits

CCD SENSOR CONTROLLER

CIRRUS LOGIC

LM98640

CMOS

10 chips are needed

TEXAS INSTRUMENTS

WM8235

CMOS

Only 3 chips are enough

FUNCTIONIMPLEMENTATION

PERFORMANCE?

PROCESSORS

INT

ER

SIL

HS

1-8

0C

86

RH

-8

AT

ME

L T

SC

21

02

0

AT

ME

L T

SC

69

5 (E

RC

32

)

IBM

RA

D 6

00

0

AR

M C

OR

TE

X M

1 (

AR

M V

6-M

)

AT

ME

L A

T6

97

F (

LE

ON

3)

INT

EL i8

04

86

AE

RO

FL

EX

DU

AL

CO

RE

LE

ON

3 F

T

INT

EL S

TR

ON

GA

RM

SA

-111

0

BA

E S

YS

TE

MS

RA

D-7

50

IBM

PP

C 6

03

IBM

PP

C 7

50

IBM

PP

C 7

50

FX

IBM

PP

C 7

50

GX

FR

EE

SC

AL

E M

PC

86

10

FR

EE

SC

AL

E M

PC

74

48

0

1000

2000

3000

4000

5000

6000

CA

PAC

IDA

D D

E P

RO

CES

AM

IEN

TO [

MIP

S]

- RAD TOLERANT COTS- RAD HARD- RAD HARD BY DESIGN- CORE

DATA STORAGE DENSITY?

2- La memoria de mayor densidad de Micron (MT29F512G08AUEBBH8-12) es de 512 Gbit.

MEMORIES 1- Las memorias NAND FLASH de mayor densidad de 3D-Plus (3DFN64G16VS8710) son

de 64 Gbit que, por ejemplo, espacializa ocho dies de 8Gbits de Micron .

MASS?

TRANSCEIVERS

-- AD9361

SIZE?

CCD Controllers

LM98640

WM8235

TECHNOLOGY PHASE SHIFT

Technology

10

μm

3 μ

m

1.5

μm

1 μ

m

80

0 n

m

60

0 n

m

35

0 n

m

25

0 n

m

18

0 n

m

13

0 n

m

90

nm

65

nm

45

nm

32

nm

28

nm

22

nm

FIN

FET

14

nm

FD-S

OI

28

/22

nm

10

nm

7 n

m

5 n

m

Year

19

71

19

75

19

82

19

85

19

89

19

94

19

95

19

97

19

99

20

00

20

02

20

04

20

06

20

08

20

10

20

11

20

12

20

14

20

15

20

16

20

17

20

18

20

20

TOD

AY

LEO

N 3

DU

AL

CO

RE

TEC

HN

OLO

GY

FPG

A R

TG4

TEC

HN

OLO

GY

SAC

-D L

AU

NC

HIN

G

CM

OS

TEC

HN

OLO

GY

USE

D IN

SA

C-C

CM

OS

TEC

HN

OLO

GY

USE

D IN

SAC

-D, S

AO

CO

M,

AR

SAT-

1,2

SAC

-C L

AU

NC

HIN

G

AR

SAT

1 L

AU

NC

HIN

G

AR

SAT

2 L

AU

NC

HIN

G

SAO

CO

M

LAU

NC

HIN

G

20 years

21 years

24 years

17 years

between 15 and 25 years

SELECTION CRITERIA

Use COTS only if they provide a considerable improvement of

technology

Focus on CMOS Integrated Circuits