978-1-4673-0455-9/12/$31.00 ©2012 IEEE

Self-controllablPower, High S

Shyam A

Abstract- The trend of decreasing device sichip densities involving several hundtransistors per chip has resulted in tremedesign complexity. Power dissipation oforms, such as dynamic, sub thresholeakage, etc. and there is need to reducelow leakage power, 45-nm 7T SRAM ispaper. The stand-by leakage power of 7Tby incorporating a newly-developed reduction circuit called a “Self-controlla(SVL)” circuit. Simulation result of 7t SRCADENCE tool shows the reduction power. In this design seven Transistor (sram is used as a Load Circuit. The Csimulation in standard 45nm CMOS tecall results obtained for this paper.

Keywords- Leakage Current, Low Power, S

I. INTRODUCTION

In modern integrated chips, SRAM ceportion [1]. Now-a-days power dissipatiocircuits has become an important design advancements in the memory chip reconsumption during the read and write operaTechnology scaling results in a high densitythere is a significant increase in leakagminimum size SRAM cell is highly desirablmemory integration density. As the integratincreases, leakage power is becoming a today’s memory chips. Lower voltages ancause a significant degradation of data stabthis design seven Transistor (7T) gated-grouas a Load Circuit. The bottom transistor is the ground path while the cell is in standbythe leakage paths through the inverter NMdesign has shown that the cell retains its vaeven in the absence of a ground path. In thitransistor’s gate is connected to the WORDtransistor is sized identically to the inverterto match their current carrying capacity. The

Shyam Akashe is Associate Professor of ITM

Vlsi.shyam@gmail.com) Meenakshi Mishra is Research scholar of ITM

mishra.meenakshi13@gmail.com) Sanjay Sharma is Associate Professor of TU

sanjay.sharma@thapar.edu)

E

le Voltage Level CircuSpeed 7T SRAM Cell a

Technology Akashe, Meenakshi Mishra,and Sanjay Sharma

ize and increasing dred millions of endous increase in occurs in various old leakage, gate e each of these. A s designed in this T sram is reduced

leakage current able Voltage Level RAM design using

in total average 7T) gated-ground Cadence Virtuoso chnology confirms

SRAM, SVL, VLSI

lls occupy a major on in the memory consideration. The

equire that power ations must be low.

y of components but ge current [2]. A le for increasing the tion of components prime concern in

nd smaller devices ility in cells [3]. In und SRAM is used intended to cut off

y mode to eliminate MOS sources. This alue during standby is study, the bottom D line. The bottom r NMOS transistors e objective of this

Gwalior, India (email:

M Gwalior, India (email:

U Patiala, India (email:

paper is to reduce leakage currenby investigate the transistor sizoptimum power and leakage cur

II. 7T SRAM C

The schematic of 7 transistoIn this section, a new 7-transistleakage current in stand-by moare deemed superior in thewhile traditional 6T cells are deprocess. The layout of 7T SRAM

Fig 1. Schematic of 7T SRAM Cell.

The 7 cell investigated is theground SRAM cell depicted additional NMOS transistor pltraditional 6T SRAM cell to redstandby mode.[4][5][6] Practiceits value during standby even inIn this study, the bottom transiWORD line. The bottom transiinverter NMOS transistors to capacity.[7]

uit for Low at 45 nm

nt applying SVL technique and zing of the 7T SRAM cell for rrent.

CELL DESIGN

or SRAM cell is shown in fig1. tor SRAM cell which have low ode. The gated-ground 7T cells e high performance process, emed the best in the low power

M cell is shown in fig.2

e seven transistor (7T) gated-in Fig 1.This cell has an

laced in the ground path of a duce leakage while the cell is in e has shown that the cell retains n the absence of a ground rail. istor’s gate is connected to the istor is sized identically to the match their current carrying

Fig. 2. Layout of 7T SRAM cell.

A. Write operation of 7T SRAM cell To write “1” to the storage node

simultaneously), at first, BL and BLB are reand discharged. WL is set to low to turn PWL is maintained at a low voltage to keep Nup to high-level by BL through P1, while Qlow-level by BLB through P2. When Q is chset WL to high and turn P1 and P2 off. In coto the node Q (“1” to QB, simultaneously)discharged and charged, respectively. [8]

Fig.3. Write operation waveform of 7T SRAM cell

There is no additional power consumption evread cycles come alternately, because therbetween the voltages level of bit lines in reawrite cycles. The write operation waveform

Q (“0” to QB, espectively charged P1 and P2 on, next N5 off. Q is charged QB is discharged to harged sufficiently, ontrast, to write “0” ), BL and BLB are

ven if the write and re is no mismatch d cycles and that in is shown in fig.3

B.Read operation of 7T SRAM

Given that Q stores “1”, at P1 and P2 off, next WL is maintN5 on, BL is discharged throustays high because N4 insulatesoperation waveform is shown and QB completely decouple thread operation. In contrast, wturning P1 and P2 off, and discharged through N4 and Nproposed SRAM cell is differenSRAM cells. In 7T SRAM cell,writing path.

Fig. 4. Read operation waveform of 7T

Reading datum does not Besides, the voltage of the storclosely maintained at the groundTherefore, the 7T SRAM cell external noise. [8]

III. Self-Controllab

The portable systems There are two well-known tepower (Pst). One is to use a m(MTCMOS) [9]. It effectively repower supply through the use oHowever, there are serious drtechnique, such as the fact thatbased on this technique cannot rinvolves using a variable thresho[10] that reduces Pst by increatechnique also faces some seriarea penalty and a large power psupply circuits requires low leak

cell

first, WL is set to high to turn tained at a high voltage to keep

ugh N3 and N5. Whereas BLB s BLB from the GND.The read in fig.4 .The storage nodes Q

he datum from the BL during a when Q stores “0”, as long as

turning N5 on, the BLB is N5. The read operation of the

nt from that of the 6T and 4T reading path is separated from

T SRAM cell with sense amplifier

interfere the storage nodes. rage node, which stores “0”, is d level during a read operation. has higher endurance against

ble Voltage Level

which are driven by battery, echniques that reduce leakage multi-threshold-voltage CMOS educes Pst by disconnecting the of high Vt MOSFET switches. rawbacks with the use of this t both memories and flip-flops retain data. The other technique old-voltage CMOS (VTCMOS) asing the substrate-biases. This ous problems, such as a large

penalty due to the substrate-bias kage power.

A self-controllable-voltage-level (SVL) csupply a maximum DC voltage to an actrequest or can decrease the DC voltage scircuit in stand-by mode was developed. Thidrastically reduce stand-by leakage powecircuits with minimal overheads in termsspeed. When CL goes to a high level, VD(0.7V), while VS decreases to VSS (0Vbecomes active[11]. Three types of self-clevel (SVL) circuits are developed.

Type-1 [Fig.5] has an upper SVL circuit, Tlower SVL circuit, and Type-3 [Fig.7] comblower SVL circuits. In the following, explanation of the SVL circuit function,assumed as the load-circuit. The upper SVL p-MOSFET switch (p-SW) and n-MOSFEconnected in series. The “on p-SW” conne(VDD) and the load circuit in the active mo“on n-SW” connect VDD and the load cmode.

Fig. 5.Schematic diagram of USVL based 7T SRAM c

Similarly, the lower SVL circuit, which incn-SW and p-SW connected in series, is ground-level power supply (VSS) and thelower SVL circuit not only supplies VSScircuit through the “on n-SW” but also supstand-by load circuit through the use of theffect of the SVL circuit on the leakage cload circuit (i.e., reduction in current) wSVL circuit and the load circuit were desiCMOS technology.

The effective gate length of both the nMOSFET was 45 nm, the threshold voltagMOSFETs was 0.21 V, and the threshold the p-MOSFETs was -0.27 V.

circuit—which can tive-load circuit on supplied to a load is S V L circuit can

er of CMOS logic of chip area and

D increases to VDD V), so the SRAM ontrollable voltage

ype-2 [Fig.6] has a bines the upper and for simplicity of

a SRAM cell is consists of a single

ET switch (n-SW) cts a power supply ode on request, and circuit in stand-by

cell

corporates a single located between a

e load circuit. The S to the active-load pplies VSS to the he “on p-SW”.The current through the

was examined. The igned using 45 nm

-MOSFET and p-ge (Vthn) of the n-

voltage (Vthp) of

While gate voltage (VG) of the4(a) is kept at “0”, the p-MOSFthe n-MOSFET (n-MOS) is tu(CL) turns on n-SW1 and turns the inverter through n-SWs. T(Vdsn), that is, a drain voltage be expressed as

Vdsn= VDD – mv,

Fig .6. Schematic diagram of LSVL ba

Where v is a voltage drop ofbe changed by varying m or v increasing m or v will increase tMOS”; that is, it will decrealowering (DIBL) effect and, coresults in a decrease in the sub t(Istn); that is, the leakage decreases.

In the case of the Type-2 Ssignal (CLB) turns on p-SW1 anis supplied to the stand-by invev) through m p-SWs. Thus, accVdsn reduces Istn Furthermoincreased by mv, so the substr(Vsub), expressed by

Vsub= – mv,

is increased. Both the reductioincrease in the back-gate bias increase in Vthn.

e stand-by inverter shown Fig. FET (pMOS) is turned on while urned off. When control signal

off p-SW, VDD is supplied to Thus, a drain-to-source voltage

(VD) of the “off n-MOS”, can

(1)

ased 7T SRAM cell.

f the single n-SW and Vdsn can (or both). Decreasing Vdsn by the barrier height of the “off n-ase the drain induced-barrier-onsequently, increase Vthn this threshold current of the n-MOS current through the inverter

SVL circuit, a negative control nd turns off nSW so that VSS rter with VG of “0” (i. e. , m ording to Equation (1), reduced ore, source voltage (VS) is rate bias (i.e., back-gate bias)

(2)

on in the DIBL effect and the (BGB) effect lead to further

Fig. 7. Schematic diagram of SVL based 7T SRAM ce

Fig. 8. Waveform of SVL based 7T SRAM cel

TABLE I OPERATION MODE

Mode Upper SVL Circuit Lower S

Active

pMOS switch is turned on nMOS s

VDD is supplied Vss is su Stand-by Mode

nMOS switch is turned on pMOS s

VD (<VDD) is supplied VS(>VSS

ell.

SVL Circuit

switch is turned on

upplied

switch is turned on

S) is supplied

The DIBL effect on n-Mincorporating the Type-3 SVLsince Vdsn in this case can be ex

Vdsn= VDD – 2mv,

The BGB effect due to Vsubin the Type-3 circuit.The wavefis shown in fig.8.The operation in TABLE I.

IV. CIRCUIT SIMUL

In this paper a SVL based c7T SRAM cell. The parameterSRAM cell using cadence virtuoand TABLE (III) respectively.

TABLPARAMETERS OF

Process Technology

Power Supply Voltage

Pre-Charge Voltage

TABL

SIMULATION RESULT OF SV

Circuit

7T SRAM during Write

7T SRAM during Read

7T SRAM with USVL

7T SRAM with LSVL

7T SRAM with SVL

IV. ACKNOWLThis work was supported I

collaboration Cadence design sylike to thank to Professor R.D Gtechnical advice..

V.CONCLSVL circuit will play a maj

the SVL circuit on the leakage c(i.e., reduction in current) was ethe load circuit were designed uSub threshold memory design hthe past years, but most of themto achieve sub threshold regioninherently process variation tapproach attractive for nano variations is a major design conseveral advantages in different mhigh Vds to load circuits for higmode load Vds through “On Mfor minimum stand-by leakage

MOS in the stand-by inverter L circuit is further decreased, xpressed as

(3)

b [given by Eq. (2)] also occurs form of SVL based 7T SRAM mode of SVL circuit is shown

LATION AND RESULTS connection is used in proposed rs and result of SVL based 7T oso tool is given in TABLE (II)

LE II 7T SRAM CELL

45nm

0.7V

1V

LE III VL BASED 7T SRAM CELL

Leakage Current

1.347 uA

1.25 uA

1.155 µA

1.077 µA

0.04 µA

LEDGEMENT ITM University Gwalior, with ystem. The authors would also Gupta sir for their enlightening

LUSION or role in future. The effect of current through the load circuit examined. The SVL circuit and using 45nm CMOS technology. has received a lot of attention in m use large number of transistor n operation. The new technique tolerant, this makes the new computing in which process

nstraint. In this circuit we have modes that is in operating mode gh speed operation, in stand-by

MOS switches” to Load circuits e power, data retention, high

noise immunity and SVL circuit small stand-by power dissipation, negligible speed degradation, negligible area overhead, high noise immunity, data retentions at stand-by mode.

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