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TRANSCRIPT
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2006 Microchip Technology Inc. DS01021A-page 1
DEVICE MIGRATIONS
This document is intended to describe the functional dif-
ferences and the electrical specification differences that
are present when migrating from one device to the next.
INTRODUCTION
The new PIC18FXXJ Flash family of devices has
several key differences from the previous generation of
PIC18 Flash devices. This migration document willidentify, examine and explain these differences and how
they could affect a system design. These differences
include a change in the naming convention of the parts,
general functionality, module differences and how to use
the correct setting for programming tools.
POWERING THE DEVICE
Internal Voltage Regulator,VDDCORE/VCAP, LF vs. F Devices,VDD Levels
Unlike previous devices in the PIC18 Flash family line,
the PIC18FXXJ Flash family of devices has an internalvoltage regulator. This voltage regulator provides a
lower supply voltage to the core of the device than what
is provided to the I/O pins. In devices with a larger pin
count (60+ pins), the voltage regulator can be enabled or
disabled externally through the ENVREG pin. This pin
can either be tied to VDD to enable the voltage regulator
or pulled to ground to disable the voltage regulator.
Figure 1 shows the effective circuit for the larger pin
count devices. Notice that the ENVREG pin is present
and that it controls whether the regulator is on or off.
In lower pin count devices, such as the PIC18F45J10
(see Figure 2), the F designation in the name (i.e.,
PIC18F45J10) specifies that the internal voltage
regulator enable is always tied to VDD and the regulator
is always on. The LF designation (i.e.,
PIC18LF45J10) specifies that the voltage regulator
enable is always tied to ground and that the regulator
will always be disabled.
FIGURE 1: INTERNAL CONNECTIONS
FOR TYPICAL HIGH PINCOUNT DEVICES
FIGURE 2: INTERNAL CONNECTIONSFOR LOW PIN COUNT F
AND LF DEVICES
Note: These devices have been designed to
perform to the parameters of their respective
data sheets. They have been tested to an
electrical specification designed to
determine their conformance with these
parameters. Due to process differences in
the manufacture of these devices, they may
have different performance characteristics
than their earlier versions. These differencesmay cause the devices to perform differently
in your application than the earlier version of
these devices.
Note: The user should verify that the device oscil-
lators start and perform as expected.
Adjusting the loading capacitor values
and/or the oscillator mode may be required.Device Core I/O Pads
ENVREG
VDDCORE/VCAP
VDD
Vss
PIC18F87J10
Voltage Regulator
In
Out
Enable
Device Core
VDDCORE VDD
VSS
PIC18LF45J10
Device Core
VCAP
VSS
PIC18F45J10
VDD
F Devices: Regulator enable hard-wired to VDD,regulator always enabled.
LF Devices: Regulator enable hard-wired to
ground, regulator always disabled.
I/O Pads
I/O Pads
Voltage Regulator
InOut
Enable
Voltage Regulator
InOut
Enable
Migrating from PIC18F to PIC18FXXJ Flash Devices
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DS01021A-page 2 2006 Microchip Technology Inc.
The VDDCORE/VCAP pin can have two functions. When
the regulator is disabled, where ENVREG is grounded
on high pin count devices and low pin count devices
with the LF designation, VDDCORE is used to supply
power to the digital core of the device. This will reduce
the current consumption of the part by removing the
voltage regulators quiescent current, which is the larg-
est contributor to the current consumption of the partwhile it is in an Idle or Sleep mode. In this mode, power
must be supplied on both the VDDCORE pin as well as
the VDD pin. The common configuration is to tie
VDDCORE to VDD and power the part from 2.0V to 2.7V.
Alternatively, power can be supplied from separate
sources to VDDCORE (2.0V to 2.7V) and VDD (VDDCORE
to 3.6V). This allows the core to run at a lower voltage
while the I/O pins and peripherals run at a higher volt-
age. When running in this mode, it is essential that
VDDCORE never exceed VDD, including during start-up.
When the voltage regulator is enabled, where
ENVREG is tied to VDD on high pin count devices and
low pin count devices with an F designation, a low
Equivalent Series Resistance (ESR) capacitor is
required on the VCAP pin in order to stabilize the output
from the internal voltage regulator. In this mode, the
device must be powered from 2.7V to 3.6V on VDD.
When the regulator is disabled, VDDCORE must beprovided from 2.0V to 2.7V in order to power the core
of the device.
Figure 3 shows the common power configuration for
high pin count PIC18FXXJ Flash devices. Figure 4
shows the common power configuration for low pin
count PIC18FXXJ Flash devices.
FIGURE 3: TYPICAL POWER CONFIGURATIONS FOR HIGH PIN COUNT PIC18FXXJ FLASHDEVICES
FIGURE 4: TYPICAL POWER CONFIGURATIONS FOR LOW PIN COUNT PIC18FXXJ FLASH
DEVICES
ENVREG
VDDCORE/
VDD
Vss
PIC18F87J10
ENVREG VDD
PIC18F87J10
VCAP VssVDDCORE/VCAP(1)
Note 1: Voltage into VDDCORE must not exceed VDD and must be less then 2.7V.
Regulator Enabled: Regulator Disabled:
VCAP
PIC18F45J10
VDDCORE(1)
PIC18LF45J10
Note 1: Voltage into VDDCORE must not exceed VDD and must be less then 2.7V.
VDD
Vss
VDD
Vss
Regulator Enabled (By Default): Regulator Disabled (By Default):
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2006 Microchip Technology Inc. DS01021A-page 3
Brown-out Reset (BOR)
PIC18FXXJ Flash devices have a BOR module
included as part of the internal voltage regulator. When
the output of the regulator drops below the minimum
core voltage, the device will go into a Brown-out Reset
condition. Since the BOR module is provided by the
voltage regulator, a device with the voltage regulatordisabled (high pin count devices where ENVREG is
grounded and all low pin count devices with the LF
designation) will also have the BOR module disabled.
This differs from earlier PIC18 Flash devices, where a
programmable BOR module can be selectively
enabled or disabled, either in a Configuration Word or
control register, and can be configured for a certain
voltage at which the Reset becomes active. These
devices require a programmable BOR because they
require a decrease in operating frequency when the
voltage drops; thus, the programmable BOR allows
users to ensure that this specification is not violated
when the system voltage drops. In contrast,
PIC18FXXJ Flash devices, with the voltage regulatorenabled, require only a single level BOR because they
can run full speed at the minimum operational voltage.
The BOR functionality in PIC18FXXJ Flash devices is
provided by the voltage regulator and is not available
when the regulator is disabled.
CLOCKING
Higher Clocking Frequencies at LowerVoltages, LF vs. F Devices
Although the PIC18FXXJ Flash family of devices has a
narrow operational voltage range, they are able to pro-vide more MIPS per volt than previous PIC18 Flash
devices. These devices are able to run at 40 MHz
(10 MIPS) while operating at 2.25V. This increased
operational flexibility enables users to harness the full
power and speed of the device in a wider voltage range.
Figure 5 shows the relationship between VDD and the
operating frequency for devices with the regulator
enabled (high pin count devices where ENVREG is tied
to VDD and low pin count devices with the F designa-
tion). Figure 6 shows the relationship between VDD,
VDDCORE and the operating frequency for devices with
the voltage regulator disabled. Note that if VDD is tied to
VDDCORE, the maximum operational voltage is 2.75V.
Oscillator Options
The oscillator options for a PIC18FXXJ Flash device are
EC, ECPLL, HS, HSPLL and the 31 kHz internal oscilla-
tor. PIC18FXXJ Flash devices do not have the XT and
LP options often found in other PIC18 Flash devices. RC
mode is available in some of the PIC18FXXJ Flash
devices. Please see the appropriate data sheet for more
information about the specific device.
FIGURE 5: VDD vs. OPERATIONALFREQUENCY (REGULATOR
ENABLED)
FIGURE 6: VDDCORE vs. OPERATIONALFREQUENCY (REGULATOR
DISABLED)
Power-up Timer
In PIC18FXXJ Flash devices, the Power-up Timer is
always enabled. In previous devices, it was an optional
feature that could be enabled or disabled in a
configuration setting.
Start-up/Reset Delay
Because the Power-up Timer is always enabled in the
PIC18FXXJ Flash devices, the start-up time for these
devices is comparatively longer than the PIC18 Flash
parts. There is also an additional delay for PIC18FXXJ
Flash devices after any Reset in order to copy theConfiguration Words from program memory into the
Configuration registers. During this delay, the internal
RC oscillator serves as the device source. After the
Configuration registers are loaded, the device switches
to the clock specified by the FOSC Configuration bits.
Refer to Configuration Words for more details.
VDD
3.6V
2.75V2.7V
2.25V
2.0V
4 MHz 40 MHz
VDDCORE
2.75V
2.7V
2.25V
2.0V
4 MHz 40 MHz
Note: 3.6V VDD VDDCORE.
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DS01021A-page 4 2006 Microchip Technology Inc.
PIN DIFFERENCES
5 Volt Tolerant Pins
Although PIC18FXXJ Flash devices have a maximum
VDD of 3.6V, I/O pins with only digital functions can
tolerate up to 5V. Pins that are multiplexed with analog
features are not 5V tolerant and include, but are notlimited to:
Any pin that is an analog input (AN0, AN1, etc.)
Any clock source pins (OSC1, OSC2, T1OSC)
Any comparator input pins
Note that pins that are 5V tolerant as inputs can only
drive VDD as an output. For applications that require a
5V output on an external device, a 5V port pin can be
emulated by:
adding an external pull-up resistor;
setting the LAT register bit for that pin to 0; and
manipulating the TRIS register bit for that pin to
either allow the pin to pull up to 5V or drive downto ground.
When using a pull-up resistor on a port pin, the
capacitance of the connection between the two devices
needs to be considered to determine the rise/fall rate of
the signal on this port pin and what resistor value is
appropriate for an application. Consider the following
shown in Equation 1:
EQUATION 1:
For example, as shown by the circuit in Figure 7, PVDD
is the voltage the resistor is pulling to. If R = 1 k,
CT = 10 pF and PVDD = 5V, then the time from when
the PIC18FXXJ Flash device releases the line (allows
the resistor to pull the line high) until Device A detects
the change is shown in Equation 2:
EQUATION 2:
FIGURE 7: CONNECTING DEVICESWITH A PULL-UP RESISTOR
When the PIC18FXXJ Flash device drives ground on
the line, then the value of R used to calculate is the
series resistance of the output driver, plus the trace
impedance. The rise time caused by the trace will typi-
cally be negligible compared to the port output fall time
(TIOF). See the AC Characteristics section of the
respective device data sheet for the value of TIOF.
Internal Pull-up Resistors
To make a digital pin on the PIC18FXXJ Flash devices
tolerant to 5V, a level translator is required. The internal
pull-up resistors on the port pins cannot pull the pins all
the way to VDD; they are limited to VDD minus the
threshold drop of the translator or VTN. More specific
information on output pull-up limits are given in the
Electrical Characteristics section of the device data
sheet.
Current Ratings on I/O Pins
Another point of consideration when migrating to a
PIC18FXXJ Flash part is the current source/sink capa-
bility of the port pins. In many PIC18 Flash parts, all of
the ports are capable of sinking or sourcing 25 mA per
pin. In the PIC18FXXJ Flash devices, certain ports,
generally PORTB and PORTC, have retained the
25 mA sink/source current rating per pin. Other ports
have ratings of either 8 mA or 2 mA per pin. Users
should always refer to the device data sheet for a
specific PIC18FXXJ Flash family of devices for current
rating information.
VCAP/VDDCORE and ENVREG
PIC18FXXJ Flash devices introduce new pins:
VCAP/VDDCORE, on all devices and ENVREG, on
devices of 44 pins or above. Each of these pins
replaces one of the port pins as compared to equivalent
PIC18 Flash devices. See Internal Voltage
Regulator, VDDCORE/VCAP, LF vs. F Devices,
VDD Levels for more information about the use of
these pins and their effects on the devices
functionality.
where:
= RCT, TVIH = the high input voltage of the
receiving device and PVDD is the voltage the
resistor is pulled up to.
Rise/Fall Time =lnPVDD
PVDD TVIH( )
ln =PVDD
PVDD TVIH( ) (1K)(10 pF)ln
5V
5V(.8 * 5V( )= 16 ns
5V 5V3V
CT
Note: CT represents trace circuit capacitance
between devices, not an actual component.
RPIC18FXXJ Flash Device A
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2006 Microchip Technology Inc. DS01021A-page 5
PROGRAM MEMORY
Device ID
In low pin count PIC18FXXJ Flash devices, F and
LF designated parts have different device IDs. In
PIC18 Flash devices, the F and LF parts share the
same device ID. Refer to Correct Settings forDevice Programmers and Software Tools for more
information on how this changes programmer and tool
usage.
Configuration Words
In PIC18 Flash devices, the Configuration Words are
located starting at address 300000h. This address
resides beyond the space of regular user program
memory (see Figure 8 for an example).
In PIC18FXXJ Flash devices, the Configuration Words
are located at the very end of the user memory space
(see Figure 9). These values are copied on any Reset
from the program memory location into the
Configuration registers. Once this copy is complete, the
write mechanism to the Configuration registers is
disabled.
If any of the Configuration bits are changed in theprogram memory during user operation, they will not
have an effect until the device goes through a Reset.
After a device Reset, the Configuration Words will be
copied back into the Configuration registers.
FIGURE 8: PIC18 FLASH CONFIGURATION WORD ADDRESS LOCATION
PC
Stack Level 1
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
CALL, RCALL, RETURN
RETFIE, RETLW
21
0000h
0018h
On-Chip
Program Memory
High Priority Interrupt Vector 0008h
UserMemorySpace
1FFFFFh
4000h
3FFFh
Read 0
200000h
PIC18FX4X0
PIC18FX5X0
8000h
7FFFh
On-Chip
Program Memory
Read 0
Configuration Configuration 300000h
Words Words
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Self-Write and EEPROM Emulation
There are several considerations when migrating a
self-writing application to a PIC18FXXJ Flash device.
The first consideration is that PIC18FXXJ Flash
devices have larger erase blocks than most PIC18
Flash devices. This increases the number of writes
required to restore the entire block after an erase.Another consideration is that, unlike PIC18 Flash
devices, each write block can only be written to once in
between erase cycles. This means that if an application
wants to change one bit of program memory to a zero,
it needs to buffer the entire erase block, erase the
memory and write back the entire memory with that bit
changed. Many PIC18 Flash devices allow multiple
writes to a block between erases, which allows an
application to copy out only the block that needs to be
changed, clear that one bit, then write it back to
memory. The mandatory erase, increased buffering
requirement and lower number of write cycles in the
PIC18FXXJ Flash devices make EEPROM emulation
more difficult.
In the PIC18FXXJ Flash devices, the holding registers
for the self-write do not reset themselves to FFh after the
write completes. They retain the values from the last
block programmed. This will apply to applications that
may write complete blocks to memory and wish for the
rest of the data to remain FFh. To insure that the remain-
ing bytes are programmed to FFh, the application will
need to do a TBLWT instruction for the remaining bytes
in the block with the value FFh.
Any application that uses self-write or EEPROM emu-
lation on a PIC18FXXJ Flash device should be aware
of the number of typical write cycles for that device (see
Write Cycles for more details).
Special consideration should be made for applications
that use the self-write functionality in the last erase
block of the user memory space. See Configuration
Words for more details.
Code Protection
Code protection in the PIC18FXXJ Flash devices isimplemented as a single block. The entire memory is
protected by a single Configuration bit. Like the code
protection bit(s) in previous devices, this bit blocks
external writes and reads from the In-Circuit Serial
Programming (ICSP) module. However, this code
protection bit does not limit table read or write functions
within the application code.
Programming Mode Entry
The programming mode entry method has changed for
PIC18FXXJ Flash devices. In the past, PIC18 Flash
devices have relied on a 12V supply on VPP/MCLR to
enter the program mode through High-VoltageProgramming mode, or a high signal on PGM for entry
into Single-Supply Programming mode when the Con-
figuration bit was appropriately set. In PIC18FXXJ
Flash devices, the programming mode entry is done by
first raising and then lowering the Reset line. Once the
part is back in Reset, a sequence is serially entered into
the programming pins to enter the programming mode.
Finally, the MCLR line is set high again to begin
programming.
Figure 10 shows an example of programming mode
entry on a PIC18FXXJ Flash device. Refer to the
appropriate device programming specification for the
specific timing requirements and device information.
FIGURE 10: ENTERING PROGRAM/VERIFY MODE FOR PIC18FXXJ FLASH DEVICES
MCLR
PGD
PGC
VDD
P13
P1
b31 b30 b29 b28 b27 b2 b1 b0b3
...
Program/Verify Entry Code = 4D434850h
P2B
P2AP19
P20
0 1 0 0 1 0 0 0 0
P12
VIH VIH
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CORRECT SETTINGS FOR DEVICEPROGRAMMERS AND SOFTWARE TOOLS
Extra caution should be used when using any program-
ming tools with a PIC18FXXJ Flash device. The
PIC18FXXJ Flash devices are unable to handle the
12V on VPP/MCLR that is typically used to enter a
device into programming mode. Before attaching a
PIC18FXXJ Flash device onto a demonstration board
or inserting it into a programming socket:
1. Verify that the board will provide the appropriate
voltage levels.
2. Verify that the VDDCORE/VCAP pin is correctly
configured, as previously described in Internal
Voltage Regulator, VDDCORE/VCAP, LF vs.
F Devices, VDD Levels.
3. Verify that the programmer and MPLAB IDE
both have the correct device selected.
Attach the programmer to the computer and verify that
the programmer is on and enabled for the correct
device before connecting the programmer to the board
or inserting the part into the programmer. Failure to do
so could result in damage or destruction of the part.
To select the correct device, go to the Configure menu
option in MPLAB IDE, then choose the Select Device
option. From this menu, select the correct device(Figure 11).
FIGURE 11: SELECTING A DEVICE IN MPLABIDE
Note: For low pin count PIC18FXXJ Flash
devices, the F and LF designated parts
will be listed separately in the Select
Device dialog box. This differs from
PIC18 Flash devices, where only the F
designated part is listed in the Select
Device dialog box.
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MODULE DIFFERENCES
A/D Calibration
One major functional change added to the PIC18FXXJ
Flash devices is the ability for users to calibrate the A/D
converter. This calibration will help compensate for any
offset generated within the module.
To start calibration, first set the ADCAL calibration bit in
the ADCON0 register (see Figure 12). With the ADCAL
bit set, start an A/D conversion by setting the
GO/DONE bit. This conversion will not read any of the
analog input pins. This process should be done each
time the operation of the device changes, for example,
oscillator changes, voltage changes, after any Reset
conditions, etc.
SUMMARY
PIC18FXXJ Flash devices give system designers more
options and flexibility in filling their microcontroller
needs. The key differences listed in this document help
distinguish the PIC18FXXJ Flash devices from the
PIC18 Flash devices, allowing designers to select the
appropriate device for their application. Designersshould consider these differences when designing and
developing their products.
FIGURE 12: EXCERPT FROM ADCON0 REGISTER SHOWING THE ADCAL BIT
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCAL CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
bit 7 ADCAL: A/D Calibration bit
1 = Calibration is performed on next A/D conversion
0 = Normal A/D converter operation (no calibration is performed)
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DS01021A-page 10 2006 Microchip Technology Inc.
NOTES:
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2006 Microchip Technology Inc. DS01021A-page 11
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
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RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
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Microchip disclaims all liability arising from this information and
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implicitly or otherwise, under any Microchip intellectual property
rights.
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PRO MATE, PowerSmart, rfPIC, and SmartShunt are
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All other trademarks mentioned herein are property of their
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2006, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for re lief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification forits worldwide headquarters, design and wafer fabrication facilities inChandler and Tempe, Arizona and Mountain View, California inOctober 2003. The Companys quality system processes andprocedures are for its PICmicro8-bit MCUs, KEELOQcode hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchips quality system for the designand manufacture of development systems is ISO 9001:2000 certified.
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