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ADDWF f, d, a

ADDWFC f, d, a

ANDWF f, d, a

CLRF f, a

COMF f, d, a

CPFSEQ f, a

CPFSGT f, aCPFSLT f, a

DECF f, d, a

DECFSZ f, d, a

DCFSNZ f, d, a

INCF f, d, a

INCFSZ f, d, a

INFSNZ f, d, a

IORWF f, d, a

MOVF f, d, a

MOVFF fs, fd

MOVWF f, a

MULWF f, a

NEGF f, a

RLCF f, d, a

RLNCF f, d, a

RRCF f, d, a

RRNCF f, d, a

SETF f, a

SUBFWB f, d, a

SUBWF f, d, a

SUBWFB f, d, a

SWAPF f, d, a

TSTFSZ f, a

XORWF f, d, a

BCF f, b, a

BSF f, b, a

BTFSC f, b, a

BTFSS f, b, a

BTG f, d, a

BC n

BN n

BNC n

BNN n

BNOV n

BNZ n

BOV n

BRA n

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BZ n

CALL n, s

CLRWDT

DAW

GOTO n

NOP NOP

POP

PUSH

RCALL n

RESET

RETFIE s

RETLW k

RETURN s

SLEEP

ADDLW

kANDLW k

IORLW k

LFSR f, k

MOVLB k

MOVLW k

MULLW k

RETLW k

SUBLW k

XORLW k

TBLRD*

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

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Add WREG and f

Add WREG and Carry bit to f

AND WREG with f

Clear f

Complement f

Compare f with WREG, skip =

Compare f with WREG, skip >Compare f with WREG, skip WSyntax: CPFSGT f {,a}

Operands: 0 f 255

a [0,1]

Operation: (f) (W),

skip if (f) > (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 010a ffff ffff

Description: Compares the contents of data memory

location f to the contents of the W by

performing an unsigned subtraction.If the contents of f are greater than the

contents of WREG, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

If a is 0, the Access Bank is selected.

If a is 1, the BSR is used to select the

GPR bank (default).

If a is 0 and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 26.2.3 Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register fProcess

Data

No

operation

If skip:

Q1 Q2 Q3 Q4

No

operation

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No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4No

operation

No

operation

No

operation

No

operation

No

operation

Nooperation

No

operation

No

operation

Example: HERE CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC = Address (HERE)

W = ?

After InstructionIf REG > W;

PC = Address (GREATER)

If REG W;

PC = Address (NGREATER)

CPFSLT Compare f with W, Skip if f < W

Syntax: CPFSLT f {,a}

Operands: 0 f 255

a [0,1]

Operation: (f) (W),

skip if (f) < (W)

(unsigned comparison)Status Affected: None


Description: Compares the contents of data memory

location f to the contents of W by

performing an unsigned subtraction.

If the contents of f are less than the

contents of W, then the fetched

instruction is discarded and a NOP is

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executed instead, making this a




GPR bank (default).

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followedby a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

No

operation

If skip:

Q1 Q2 Q3 Q4No

operation

No

operation

No

operation

No

operation


Q1 Q2 Q3 Q4

No

operationNo

operation

No

operation

No

operation

No

operation

No

operation

Nooperation

No

operation

Example: HERE CPFSLT REG, 1

NLESS :

LESS :

Before Instruction

PC = Address (HERE)

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W = ?

After Instruction

If REG < W;

PC = Address (LESS)

If REG W;

PC = Address (NLESS)

PIC18F2455/2550/4455/4550

DS39632C-page 326 Preliminary 2006 Microchip Technology Inc.DAW Decimal Adjust W Register

Syntax: DAW

Operands: None

Operation: If [W > 9] or [DC = 1] then

(W) 6 W;

else

(W) W

If [W + DC > 9] or [C = 1] then

(W) 6 DC W;

else

(W) DC WStatus Affected: C

Encoding: 0000 0000 0000 0111

Description: DAW adjusts the eight-bit value in W,

resulting from the earlier addition of two

variables (each in packed BCD format)

and produces a correct packed BCD

result.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Readregister W

Process

Data

Write

W

Example 1: DAW

Before Instruction

W = A5h

C = 0

DC = 0

After InstructionW = 05h

C = 1

DC = 0

Example 2:

Before Instruction

W = CEh

C = 0

DC = 0

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After Instruction

W = 34h

C = 1

DC = 0

DECF Decrement f

Syntax: DECF f {,d {,a}}

Operands: 0 f 255

d [0,1]a [0,1]

Operation: (f) 1 dest

Status Affected: C, DC, N, OV, Z

Encoding: 0000 01da ffff ffff

Description: Decrement register f. If d is 0, the

result is stored in W. If d is 1, the

result is stored back in register f

(default).



GPR bank (default).If a is 0 and the extended instruction







Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Readregister f

Process

Data

Write to

destination

Example: DECF CNT, 1, 0

Before Instruction

CNT = 01h

Z = 0

After Instruction

CNT = 00hZ = 1

2006 Microchip Technology Inc. Preliminary DS39632C-page 327

PIC18F2455/2550/4455/4550

DECFSZ Decrement f, Skip if 0

Syntax: DECFSZ f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]

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Operation: (f) 1 dest,

skip if result = 0



Description: The contents of register f are

decremented. If d is 0, the result is

placed in W. If d is 1, the result is

placed back in register f (default).If the result is 0, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.



GPR bank (default).




mode whenever f 95 (5Fh). SeeSection 26.2.3 Byte-Oriented and



Words: 1

Cycles: 1(2)



Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

ProcessData

Write to

destination

If skip:

Q1 Q2 Q3 Q4

No

operation

No

operation

No

operationNo

operation


Q1 Q2 Q3 Q4

No

operation

No

operation

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No

operation

No

operation

No

operation

No

operationNo

operation

No

operation

Example: HERE DECFSZ CNT, 1, 1

GOTO LOOP

CONTINUE

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT 1If CNT = 0;

PC = Address (CONTINUE)

If CNT 0;

PC = Address (HERE + 2)

DCFSNZ Decrement f, Skip if Not 0

Syntax: DCFSNZ f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]


skip if result 0

Status Affected: NoneEncoding: 0100 11da ffff ffff


decremented. If d is 0, the result is


placed back in register f (default).

If the result is not 0, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If a is 0, the Access Bank is selected.If a is 1, the BSR is used to select the

GPR bank (default).







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Words: 1

Cycles: 1(2)



Q Cycle Activity:

Q1 Q2 Q3 Q4


Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

No

operation

No

operationNo

operation

No

operation


Q1 Q2 Q3 Q4

No

operation

No

operation

No

operationNo

operation

No

operation

No

operation

No

operation

No

operation

Example: HERE DCFSNZ TEMP, 1, 0ZERO :

NZERO :

Before Instruction

TEMP = ?

After Instruction

TEMP = TEMP 1,

If TEMP = 0;

PC = Address (ZERO)

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If TEMP 0;

PC = Address (NZERO)

PIC18F2455/2550/4455/4550

DS39632C-page 328 Preliminary 2006 Microchip Technology Inc.

GOTO Unconditional Branch

Syntax: GOTO k

Operands: 0 k 1048575

Operation: k PCStatus Affected: None

Encoding:

1st word (k)

2nd word(k)

1110

1111

1111

k19kkk

k7kkk

kkkk

kkkk0kkkk8

Description: GOTO allows an unconditional branch

anywhere within the entire

2-Mbyte memory range. The 20-bit

value k is loaded into PC. GOTO

is always a two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

k,

No

operation

Read literal

k,

Write to PC

No

operation

No

operation

No

operationNo

operation

Example: GOTO THERE

After Instruction

PC = Address (THERE)

INCF Increment f

Syntax: INCF f {,d {,a}}

Operands: 0 f 255

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d [0,1]

a [0,1]

Operation: (f) 1 dest

Status Affected: C, DC, N, OV, Z



incremented. If d is 0, the result is

placed in W. If d is 1, the result isplaced back in register f (default).



GPR bank (default).







Literal Offset Mode for details.Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write to

destination

Example: INCF CNT, 1, 0

Before InstructionCNT = FFh

Z = 0

C = ?

DC = ?

After Instruction

CNT = 00h

Z = 1

C = 1

DC = 1


PIC18F2455/2550/4455/4550INCFSZ Increment f, Skip if 0

Syntax: INCFSZ f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]


skip if result = 0


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placed back in register f. (default)

If the result is 0, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, makingit a two-cycle instruction.



GPR bank (default).







Literal Offset Mode for details.Words: 1

Cycles: 1(2)



Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write to

destinationIf skip:

Q1 Q2 Q3 Q4

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:Q1 Q2 Q3 Q4

No

operation

No

operation

No

operation

No

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operation

No

operation

No

operation

No

operation

Nooperation

Example: HERE INCFSZ CNT, 1, 0

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT + 1

If CNT = 0;

PC = Address (ZERO)

If CNT 0;PC = Address (NZERO)

INFSNZ Increment f, Skip if Not 0

Syntax: INFSNZ f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]


skip if result 0







If the result is not 0, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.



GPR bank (default).

If a is 0 and the extended instructionset is enabled, this instruction operates






Words: 1

Cycles: 1(2)

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Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

DataWrite to

destination

If skip:

Q1 Q2 Q3 Q4

No

operation

No

operation

No

operation

Nooperation


Q1 Q2 Q3 Q4

No

operation

No

operation

No

operation

No

operation

Nooperation

No

operation

No

operation

No

operation

Example: HERE INFSNZ REG, 1, 0

ZERO

NZERO

Before InstructionPC = Address (HERE)

After Instruction

REG = REG + 1

If REG 0;

PC = Address (NZERO)

If REG = 0;

PC = Address (ZERO)

PIC18F2455/2550/4455/4550

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IORLW Inclusive OR Literal with W

Syntax: IORLW k

Operands: 0 k 255

Operation: (W) .OR. k W

Status Affected: N, Z

Encoding: 0000 1001 kkkk kkkk

Description: The contents of W are ORed with theeight-bit literal k. The result is placed in

W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal k

Process

Data

Write to WExample: IORLW 35h

Before Instruction

W = 9Ah

After Instruction

W = BFh

IORWF Inclusive OR W with f

Syntax: IORWF f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]

Operation: (W) .OR. (f) dest

Status Affected: N, ZEncoding: 0001 00da ffff ffff

Description: Inclusive OR W with register f. If d is

0, the result is placed in W. If d is 1,

the result is placed back in register f

(default).



GPR bank (default).



in Indexed Literal Offset Addressingmode whenever f 95 (5Fh). See




Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

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Decode Read

register f

Process

Data

Write to

destination

Example: IORWF RESULT, 0, 1

Before InstructionRESULT = 13h

W = 91h

After Instruction

RESULT = 13h

W = 93h


PIC18F2455/2550/4455/4550

LFSR Load FSR

Syntax: LFSR f, k

Operands: 0 f 2

0 k 4095Operation: k FSRf


Encoding: 1110

1111

1110

0

00ff

k7kkk

k11kkk

kkkk

Description: The 12-bit literal k is loaded into the

File Select Register pointed to by f.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

k MSB

Process

Data

Write

literal k MSB

to FSRfHDecode Read literal

k LSB

Process

Data

Write literal k

to FSRfL

Example: LFSR 2, 3ABh

After Instruction

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FSR2H = 03h

FSR2L = ABh

MOVF Move f

Syntax: MOVF f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]

Operation: f destStatus Affected: N, Z


Description: The contents of register f are moved to

a destination dependent upon the

status of d. If d is 0, the result is



Location f can be anywhere in the

256-byte bank.


If a is 1, the BSR is used to select theGPR bank (default).








Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4Decode Read

register f

Process

Data

Write W

Example: MOVF REG, 0, 0

Before Instruction

REG = 22h

W = FFh

After Instruction

REG = 22hW = 22h

PIC18F2455/2550/4455/4550


MOVFF Move f to f

Syntax: MOVFF fs,fd

Operands: 0 fs 4095

0 fd 4095

Operation: (fs) fd

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Encoding:

1st word (source)

2nd word (destin.)

1100

1111

ffff

ffffffff

ffff

ffffs

ffffd

Description: The contents of source register fs are

moved to destination register fd.

Location of source fs can be anywhere

in the 4096-byte data space (000h to

FFFh) and location of destination fd

can also be anywhere from 000h to

FFFh.Either source or destination can be W

(a useful special situation).

MOVFF is particularly useful for

transferring a data memory location to a

peripheral register (such as the transmit

buffer or an I/O port).

The MOVFF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Words: 2

Cycles: 2

Q Cycle Activity:Q1 Q2 Q3 Q4

Decode Read

register f

(src)

Process

Data

No

operation

Decode No

operation

No dummyread

No

operation

Write

register f

(dest)

Example: MOVFF REG1, REG2

Before Instruction

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REG1 = 33h

REG2 = 11h

After Instruction

REG1 = 33h

REG2 = 33h

MOVLB Move Literal to Low Nibble in BSR

Syntax: MOVLW k

Operands: 0 k 255Operation: k BSR



Description: The eight-bit literal k is loaded into the

Bank Select Register (BSR). The value

of BSR always remains 0

regardless of the value of k7:k4.

Words: 1

Cycles: 1

Q Cycle Activity:


literal k

Process

Data

Write literal

k to BSR

Example: MOVLB 5

Before Instruction

BSR Register = 02h

After Instruction

BSR Register = 05h

2006 Microchip Technology Inc. Preliminary DS39632C-page 333PIC18F2455/2550/4455/4550

MOVLW Move Literal to W

Syntax: MOVLW k

Operands: 0 k 255

Operation: k W



Description: The eight-bit literal k is loaded into W.

Words: 1

Cycles: 1


Decode Read

literal k

Process

Data

Write to W

Example: MOVLW 5Ah

After Instruction

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W = 5Ah

MOVWF Move W to f

Syntax: MOVWF f {,a}

Operands: 0 f 255

a [0,1]

Operation: (W) f


Encoding: 0110 111a ffff ffffDescription: Move data from W to register f.

Location f can be anywhere in the

256-byte bank.



GPR bank (default).





Section 26.2.3 Byte-Oriented andBit-Oriented Instructions in Indexed


Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write

register f

Example: MOVWF REG, 0

Before Instruction

W = 4Fh

REG = FFh

After Instruction

W = 4Fh

REG = 4Fh

PIC18F2455/2550/4455/4550


MULLW Multiply Literal with W

Syntax: MULLW kOperands: 0 k 255

Operation: (W) x k PRODH:PRODL



Description: An unsigned multiplication is carried

out between the contents of W and the

8-bit literal k. The 16-bit result is

placed in PRODH:PRODL register pair.

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PRODH contains the high byte.

W is unchanged.

None of the Status flags are affected.

Note that neither Overflow nor Carry is

possible in this operation. A zero result

is possible but not detected.

Words: 1

Cycles: 1Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal k

Process

Data

Write

registers

PRODH:

PRODL

Example: MULLW 0C4hBefore Instruction

W = E2h

PRODH = ?

PRODL = ?

After Instruction

W = E2h

PRODH = ADh

PRODL = 08h

MULWF Multiply W with f

Syntax: MULWF f {,a}

Operands: 0 f 255

a [0,1]Operation: (W) x (f) PRODH:PRODL



Description: An unsigned multiplication is carried

out between the contents of W and the

register file location f. The 16-bit

result is stored in the PRODH:PRODL

register pair. PRODH contains the

high byte. Both W and f are

unchanged.

None of the Status flags are affected.Note that neither Overflow nor Carry is

possible in this operation. A zero

result is possible but not detected.

If a is 0, the Access Bank is

selected. If a is 1, the BSR is used

to select the GPR bank (default).


set is enabled, this instruction

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operates in Indexed Literal Offset

Addressing mode whenever

f 95 (5Fh). See Section 26.2.3

Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode for details.Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write

registers

PRODH:PRODL

Example: MULWF REG, 1

Before Instruction

W = C4h

REG = B5h

PRODH = ?

PRODL = ?

After Instruction

W = C4h

REG = B5h

PRODH = 8Ah

PRODL = 94h 2006 Microchip Technology Inc. Preliminary DS39632C-page 335

PIC18F2455/2550/4455/4550

NEGF Negate f

Syntax: NEGF f {,a}

Operands: 0 f 255

a [0,1]

Operation: (f) 1 f

Status Affected: N, OV, C, DC, Z


Description: Location f is negated using twos

complement. The result is placed in thedata memory location f.



GPR bank (default).





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Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4


Process

Data

Write

register f

Example: NEGF REG, 1

Before Instruction

REG = 0011 1010 [3Ah]

After Instruction

REG = 1100 0110 [C6h]

NOP No OperationSyntax: NOP

Operands: None

Operation: No operation


Encoding: 0000

1111

0

xxxx

0

xxxx

0

xxxxDescription: No operation.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

No

operation

No

operationExample:

None.

PIC18F2455/2550/4455/4550


POP Pop Top of Return Stack

Syntax: POP

Operands: None

Operation: (TOS) bit bucket

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Encoding: 0000 0000 0000 0110

Description: The TOS value is pulled off the return

stack and is discarded. The TOS value

then becomes the previous value that

was pushed onto the return stack.

This instruction is provided to enable

the user to properly manage the returnstack to incorporate a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Pop TOS

value

No

operationExample: POP

GOTO NEW

Before Instruction

TOS = 0031A2h

Stack (1 level down) = 014332h

After Instruction

TOS = 014332h

PC = NEW

PUSH Push Top of Return Stack

Syntax: PUSH

Operands: None

Operation: (PC 2) TOS


Encoding: 0000 0000 0000 0101

Description: The PC + 2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implementing a

software stack by modifying TOS and

then pushing it onto the return stack.

Words: 1

Cycles: 1


Decode Push PC + 2

onto return

stack

No

operation

No

operation

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Example: PUSH

Before Instruction

TOS = 345Ah

PC = 0124h

After Instruction

PC = 0126h

TOS = 0126h

Stack (1 level down) = 345Ah 2006 Microchip Technology Inc. Preliminary DS39632C-page 337

PIC18F2455/2550/4455/4550

RCALL Relative Call

Syntax: RCALL n

Operands: -1024 n 1023

Operation: (PC) 2 TOS,

(PC) 2 2n PC


Encoding: 1101 1nnn nnnn nnnn

Description: Subroutine call with a jump up to 1K

from the current location. First, returnaddress (PC + 2) is pushed onto the

stack. Then, add the 2s complement

number 2n to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a


Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literaln

Push PC to

stack

Process

Data

Write to PC

No

operation

No

operation

Nooperation

No

operation

Example: HERE RCALL Jump

Before Instruction

PC = Address (HERE)

After Instruction

PC = Address (Jump)

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TOS = Address (HERE + 2)

RESET Reset

Syntax: RESET

Operands: None

Operation: Reset all registers and flags that are

affected by a MCLR Reset.

Status Affected: All

Encoding: 0000 0000 1111 1111Description: This instruction provides a way to

execute a MCLR Reset in software.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Start

Reset

No

operation

Nooperation

Example: RESET

After Instruction

Registers = Reset Value

Flags* = Reset Value

PIC18F2455/2550/4455/4550


RETFIE Return from Interrupt

Syntax: RETFIE {s}

Operands: s [0,1]

Operation: (TOS) PC,

1 GIE/GIEH or PEIE/GIEL,

if s = 1

(WS) W,

(STATUSS) STATUS,

(BSRS) BSR,

PCLATU, PCLATH are unchanged

Status Affected: GIE/GIEH, PEIE/GIEL.

Encoding: 0000 0000 0001 000s

Description: Return from interrupt. Stack is popped

and Top-of-Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low priorityglobal interrupt enable bit. If s = 1, the

contents of the shadow registers WS,

STATUSS and BSRS are loaded into

their corresponding registers, W,

STATUS and BSR. If s = 0, no update

of these registers occurs (default).

Words: 1

Cycles: 2

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Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

No

operation

Pop PC from

stackSet GIEH or

GIEL

No

operation

No

operation

No

operation

No

operation

Example: RETFIE 1After Interrupt

PC = TOS

W = WS

BSR = BSRS

STATUS = STATUSS

GIE/GIEH, PEIE/GIEL = 1

RETLW Return Literal to W

Syntax: RETLW k

Operands: 0 k 255

Operation: k W,

(TOS) PC,

PCLATU, PCLATH are unchangedStatus Affected: None


Description: W is loaded with the eight-bit literal k.

The program counter is loaded from the

top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Words: 1

Cycles: 2

Q Cycle Activity:


literal k

Process

Data

Pop PC from

stack, Write

to W

No

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operation

No

operation

No

operation

No

operation

Example:CALL TABLE ; W contains table

; offset value

; W now has

; table value

:

TABLE

ADDWF PCL ; W = offset

RETLW k0 ; Begin table

RETLW k1 ;

:

:RETLW kn ; End of table

Before Instruction

W = 07h

After Instruction

W = value of kn


PIC18F2455/2550/4455/4550

RETURN Return from Subroutine

Syntax: RETURN {s}

Operands: s [0,1]

Operation: (TOS) PC,

if s = 1(WS) W,

(STATUSS) STATUS,

(BSRS) BSR,

PCLATU, PCLATH are unchanged


Encoding: 0000 0000 0001 001s

Description: Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

s= 1, the contents of the shadow

registers WS, STATUSS and BSRS areloaded into their corresponding

registers, W, STATUS and BSR. If

s = 0, no update of these registers

occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

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register f

Process

Data

Write to

destination

Example: RLCF REG, 0, 0

Before Instruction

REG = 1110 0110C = 0

After Instruction

REG = 1110 0110

W = 1100 1100

C = 1

C register f

PIC18F2455/2550/4455/4550


RLNCF Rotate Left f (No Carry)

Syntax: RLNCF f {,d {,a}}

Operands: 0 f 255d [0,1]

a [0,1]

Operation: (f) dest,

(f) dest



Description: The contents of register f are rotated

one bit to the left. If d is 0, the result

is placed in W. If d is 1, the result is

stored back in register f (default).



GPR bank (default).








Words: 1

Cycles: 1


Decode Read

register f

Process

Data

Write to

destination

Example: RLNCF REG, 1, 0

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Before Instruction

REG = 1010 1011

After Instruction

REG = 0101 0111

register f

RRCF Rotate Right f through Carry

Syntax: RRCF f {,d {,a}}

Operands: 0 f 255d [0,1]

a [0,1]


(f) C,

(C) dest

Status Affected: C, N, Z



one bit to the right through the Carry

flag. If d is 0, the result is placed in W.

If d is 1, the result is placed back inregister f (default).



GPR bank (default).








Words: 1Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write to

destination

Example: RRCF REG, 0, 0

Before InstructionREG = 1110 0110

C = 0

After Instruction

REG = 1110 0110

W = 0111 0011

C = 0

C register f


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PIC18F2455/2550/4455/4550

RRNCF Rotate Right f (No Carry)

Syntax: RRNCF f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]


(f) destStatus Affected: N, Z



one bit to the right. If d is 0, the result



If a is 0, the Access Bank will be

selected, overriding the BSR value. If a

is 1, then the bank will be selected as

per the BSR value (default).

If a is 0 and the extended instructionset is enabled, this instruction operates






Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write to

destination

Example 1: RRNCF REG, 1, 0

Before Instruction

REG = 1101 0111

After Instruction

REG = 1110 1011

Example 2: RRNCF REG, 0, 0

Before InstructionW = ?

REG = 1101 0111

After Instruction

W = 1110 1011

REG = 1101 0111

register f

SETF Set f

Syntax: SETF f {,a}

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Operands: 0 f 255

a [0,1]

Operation: FFh f



Description: The contents of the specified register

are set to FFh.

If a is 0, the Access Bank is selected.If a is 1, the BSR is used to select the

GPR bank (default).








Words: 1


Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write

register f

Example: SETF REG,1

Before Instruction

REG = 5Ah

After InstructionREG = FFh

PIC18F2455/2550/4455/4550


SLEEP Enter Sleep mode

Syntax: SLEEP

Operands: None

Operation: 00h WDT,

0 WDT postscaler,

1 TO,

0 PD

Status Affected: TO, PDEncoding: 0000 0000 0000 0011

Description: The Power-Down status bit (PD) is

cleared. The Time-out status bit (TO)

is set. Watchdog Timer and its

postscaler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

Words: 1

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Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Process

Data

Go toSleep

Example: SLEEP

Before Instruction

TO = ?

PD = ?

After Instruction

TO = 1

PD = 0

If WDT causes wake-up, this bit is cleared.

SUBFWB Subtract f from W with Borrow

Syntax: SUBFWB f {,d {,a}}Operands: 0 f 255

d [0,1]

a [0,1]

Operation: (W) (f) (C) dest



Description: Subtract register f and Carry flag

(borrow) from W (2s complement

method). If d is 0, the result is stored

in W. If d is 1, the result is stored in

register f (default).










Instructions in Indexed Literal OffsetMode for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

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Data

Write to

destination

Example 1: SUBFWB REG, 1, 0

Before Instruction

REG = 3

W = 2

C = 1After Instruction

REG = FF

W = 2

C = 0

Z = 0

N = 1 ; result is negative


Before Instruction

REG = 2

W = 5

C = 1After Instruction

REG = 2

W = 3

C = 1

Z = 0

N = 0 ; result is positive


Before Instruction

REG = 1

W = 2

C = 0

After InstructionREG = 0

W = 2

C = 1

Z = 1 ; result is zero

N = 0


PIC18F2455/2550/4455/4550

SUBLW Subtract W from Literal

Syntax: SUBLW k

Operands: 0 k 255

Operation: k (W) WStatus Affected: N, OV, C, DC, Z


Description W is subtracted from the eight-bit

literal k. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

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Decode Read

literal k

Process

Data

Write to W

Example 1: SUBLW 02h

Before Instruction

W = 01hC = ?

After Instruction

W = 01h

C = 1 ; result is positive

Z = 0

N = 0


Before Instruction

W = 02h

C = ?

After InstructionW = 00h

C = 1 ; result is zero

Z = 1

N = 0


Before Instruction

W = 03h

C = ?

After Instruction

W = FFh ; (2s complement)

C = 0 ; result is negative

Z = 0N = 1

SUBWF Subtract W from f

Syntax: SUBWF f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]

Operation: (f) (W) dest



Description: Subtract W from register f (2s

complement method). If d is 0, theresult is stored in W. If d is 1, the

result is stored back in register f

(default).




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Instructions in Indexed Literal Offset

Mode for details.Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write to

destination

Example 1: SUBWF REG, 1, 0Before Instruction

REG = 3

W = 2

C = ?

After Instruction

REG = 1

W = 2

C = 1 ; result is positive

Z = 0

N = 0

Example 2: SUBWF REG, 0, 0

Before InstructionREG = 2

W = 2

C = ?

After Instruction

REG = 2

W = 0

C = 1 ; result is zero

Z = 1

N = 0

Example 3: SUBWF REG, 1, 0

Before InstructionREG = 1

W = 2

C = ?

After Instruction

REG = FFh ;(2s complement)

W = 2

C = 0 ; result is negative

Z = 0

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W = 1Ah (0001 1010)

C = 0

After Instruction

REG = 1Bh (0001 1011)

W = 00h

C = 1

Z = 1 ; result is zero

N = 0Example 3: SUBWFB REG, 1, 0

Before Instruction

REG = 03h (0000 0011)

W = 0Eh (0000 1101)

C = 1

After Instruction

REG = F5h (1111 0100)

; *2s comp+

W = 0Eh (0000 1101)

C = 0

Z = 0N = 1 ; result is negative

SWAPF Swap f

Syntax: SWAPF f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]


(f) dest



Description: The upper and lower nibbles of register

f are exchanged. If d is 0, the result


placed in register f (default).



GPR bank (default).






Bit-Oriented Instructions in IndexedLiteral Offset Mode for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

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Data

Write to

destination

Example: SWAPF REG, 1, 0

Before Instruction

REG = 53h

After Instruction

REG = 35h 2006 Microchip Technology Inc. Preliminary DS39632C-page 345

PIC18F2455/2550/4455/4550

TBLRD Table Read

Syntax: TBLRD ( *; *+; *-; +*)

Operands: None

Operation: if TBLRD *

(Prog Mem (TBLPTR)) TABLAT;

TBLPTR No Change;

if TBLRD *+


(TBLPTR) 1 TBLPTR;if TBLRD *-


(TBLPTR) 1 TBLPTR;

if TBLRD +*

(TBLPTR) 1 TBLPTR;

(Prog Mem (TBLPTR)) TABLAT


Encoding: 0000 0000 0000 10nn

nn=0 *

=1 *+

=2 *-

=3 +*Description: This instruction is used to read the contents

of Program Memory (P.M.). To address the

program memory, a pointer called Table

Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range.

TBLPTR[0] = 0: Least Significant Byte

of Program Memory

Word

TBLPTR[0] = 1: Most Significant Byteof Program Memory

Word

The TBLRD instruction can modify the value

of TBLPTR as follows:

no change

post-increment

post-decrement

pre-increment

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Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

No

operationNo

operation

No

operation

No operation

(Read Program

Memory)

No

operation

No operation

(WriteTABLAT)

TBLRD Table Read (Continued)

Example 1: TBLRD *+ ;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

MEMORY (00A356h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 00A357h

Example 2: TBLRD +* ;

Before InstructionTABLAT = AAh

TBLPTR = 01A357h



After Instruction

TABLAT = 34h

TBLPTR = 01A358h

PIC18F2455/2550/4455/4550


TBLWT Table Write

Syntax: TBLWT ( *; *+; *-; +*)Operands: None

Operation: if TBLWT*

(TABLAT) Holding Register;

TBLPTR No Change;

if TBLWT*+


(TBLPTR) 1 TBLPTR;

if TBLWT*-

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(TBLPTR) 1 TBLPTR;

if TBLWT+*

(TBLPTR) 1 TBLPTR;

(TABLAT) Holding Register


Encoding: 0000 0000 0000 11nn

nn=0 *=1 *+

=2 *-

=3 +*

Description: This instruction uses the 3 LSBs of TBLPTR

to determine which of the

8 holding registers the TABLAT is written to.

The holding registers are used to

program the contents of Program

Memory (P.M.). (Refer to Section 6.0

Flash Program Memory for additional

details on programming Flash memory.)The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range. The LSb of

the TBLPTR selects which byte of the

program memory location to access.

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify thevalue of TBLPTR as follows:

no change

post-increment

post-decrement

pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operationNo

operation

No

operation

No

operation

No

operation

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(Read

TABLAT)

No

operation

No

operation

(Write to

HoldingRegister)

TBLWT Table Write (Continued)

Example 1: TBLWT *+;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

HOLDING REGISTER

(00A356h) = FFh

After Instructions (table write completion)

TABLAT = 55h

TBLPTR = 00A357hHOLDING REGISTER

(00A356h) = 55h

Example 2: TBLWT +*;

Before Instruction

TABLAT = 34h

TBLPTR = 01389Ah

HOLDING REGISTER

(01389Ah) = FFh

HOLDING REGISTER

(01389Bh) = FFh

After Instruction (table write completion)

TABLAT = 34hTBLPTR = 01389Bh

HOLDING REGISTER

(01389Ah) = FFh

HOLDING REGISTER

(01389Bh) = 34h


PIC18F2455/2550/4455/4550

TSTFSZ Test f, Skip if 0

Syntax: TSTFSZ f {,a}

Operands: 0 f 255

a

[0,1]Operation: skip if f = 0



Description: If f = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOP is executed,

making this a two-cycle instruction.


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GPR bank (default).






Bit-Oriented Instructions in IndexedLiteral Offset Mode for details.

Words: 1

Cycles: 1(2)



Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

register f

Process

DataNo

operation

If skip:

Q1 Q2 Q3 Q4

No

operation

No

operation

No

operation

No

operationIf skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

No

operation

No

operation

No

operation

No

operation

Nooperation

No

operation

No

operation

No

operation

Example: HERE TSTFSZ CNT, 1

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NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

If CNT = 00h,

PC = Address (ZERO)

If CNT 00h,PC = Address (NZERO)

XORLW Exclusive OR Literal with W

Syntax: XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W



Description: The contents of W are XORed with

the 8-bit literal k. The result is placed

in W.

Words: 1Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal k

Process

Data

Write to W

Example: XORLW 0AFh

Before Instruction

W = B5h

After InstructionW = 1Ah

PIC18F2455/2550/4455/4550


XORWF Exclusive OR W with f

Syntax: XORWF f {,d {,a}}

Operands: 0 f 255

d [0,1]

a [0,1]

Operation: (W) .XOR. (f) dest


Encoding: 0001 10da ffff ffffDescription: Exclusive OR the contents of W with

register f. If d is 0, the result is stored

in W. If d is 1, the result is stored back

in the register f (default).



GPR bank (default).


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Words: 1


Q1 Q2 Q3 Q4

Decode Read

register f

Process

Data

Write to

destination

Example: XORWF REG, 1, 0

Before Instruction

REG = AFhW = B5h

After Instruction

REG = 1Ah

W = B5h

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Aadir WREG y F

Aadir WREG y seguir poco a f

Y WREG con F

Claro f

Complementar f

Comparar f con WREG, skip =

Comparar f con WREG, omita>Comparar f con WREG, omita WSintaxis: CPFSGT F {,} un

Operandos: 0 f 255

a [0,1]

Operacin: (f) - (W),

skip if (f)> (W)

(Comparacin sin signo)

Estado afectado: Ninguno

Codificacin: 0110 010a ffff ffff

Descripcin: Compara el contenido de la memoria de datos

ubicacin "f" al contenido de la W por

la realizacin de una resta sin signo.Si el contenido de 'f' es mayor que el

contenido de WREG, entonces el exagerado

instruccin se descarta y un NOP es

ejecutado en su lugar, haciendo de este un

instruccin de dos ciclos.

Si 'a' es '0 ', se selecciona el Banco de Acceso.

Si 'a' es '1 ', el BSR se utiliza para seleccionar el

Banco GPR (por defecto).

Si 'a' es '0 'y la instruccin ampliada

set est activada, funciona esta instruccin

en Indexed Literal Offset Dirigindose

modo cada vez que f 95 (5Fh). Ver

Seccin 26.2.3 "orientados a bytes y

Operaciones con bits orientada en indiciada

Modo de desplazamiento Literal "para ms detalles.

Palabras: 1

Ciclos: 1 (2)

Nota: 3 ciclos si saltar y seguido

por una instruccin de 2 palabras.

Q ciclo de actividades:

Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'Proceso

Datos

No

operacin

Si saltar:

Q1 Q2 Q3 Q4

No

operacin

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No

operacin

No

operacin

No

operacin

Si saltar y seguido por la instruccin 2 palabras:

Q1 Q2 Q3 Q4No

operacin

No

operacin

No

operacin

No

operacin

No

operacin

Nooperacin

No

operacin

No

operacin

Ejemplo: AQU CPFSGT REG, 0

NGREATER:

MAYOR:

Antes de Instruccin

PC = Direccin (AQU)

#NAME?

Despus de InstruccinSi REG> W;

PC = Direccin (MAYOR)

Si REG W;

PC = Direccin (NGREATER)

CPFSLT Comparar f con W, Omitir si f

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ejecutado en su lugar, haciendo de este un

instruccin de dos ciclos.




Palabras: 1

Ciclos: 1 (2)

Nota: 3 ciclos si saltar y seguidopor una instruccin de 2 palabras.


Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

Proceso

Datos

No

operacin

Si saltar:

Q1 Q2 Q3 Q4No

operacin

No

operacin

No

operacin

No

operacin


Q1 Q2 Q3 Q4

No

operacinNo

operacin

No

operacin

No

operacin

No

operacin

No

operacin

Nooperacin

No

operacin

Ejemplo: AQU CPFSLT REG, 1

Alvo:

MENOS:

Antes de Instruccin

PC = Direccin (AQU)

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#NAME?

Despus de Instruccin

Si REG 9] o [DC = 1] y luego

(W ) 6 W ;

ms

(W ) W

Si [W + DC> 9] o [C = 1] y luego

(W ) 6 DC W ;

ms

(W ) DC W Estado afectado: C

Codificacin: 0000 0000 0000 0111

Descripcin: DAW ajusta el valor de ocho bits en W,

resultante de la adicin anterior de dos

las variables (cada una en formato BCD para llevar)

y produce un BCD empaquetado correcto

resultado.

Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4

Decode Leerregistrarse W

Proceso

Datos

Escribir

W

Ejemplo 1: DAW

Antes de Instruccin

W = A5H

C = 0

DC = 0

Despus de InstruccinW = 05h

C = 1

DC = 0

Ejemplo 2:

Antes de Instruccin

W = CEH

C = 0

DC = 0

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W = 34h

C = 1

DC = 0

DECF Disminuir f

Sintaxis: DECF f {, {d, a}}

Operandos: 0 f 255

d [0,1]a [0,1]

Operacin: (f) - 1 dest

Estado afectado: C, CC, N, OV, Z

Codificacin: 0000 01DA ffff ffff

Descripcin: Disminuye el Registro 'f'. Si 'd' es '0 ', el

resultado se almacena en W. Si 'd' es '1 ', la

resultado se almacena en el registro 'f'

(Por defecto).



Banco GPR (por defecto).Si 'a' es '0 'y la instruccin ampliada







Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4

Decode Leerregistrarse 'f'

Proceso

Datos

Escriba a

destino

Ejemplo: DECF CNT, 1, 0

Antes de Instruccin

CNT = 01h

Z = 0


CNT = 00hZ = 1

2006 Microchip Technology Inc. DS39632C pginas Preliminar 327

PIC18F2455/2550/4455/4550

DECFSZ Disminuir f, Saltar si es 0

Sintaxis: DECFSZ f {, {d, a}}

Operandos: 0 f 255

d [0,1]

a [0,1]

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Operacin: (f) - 1 dest,

saltar si el resultado = 0


Codificacin: 0010 11da ffff ffff

Descripcin: El contenido del registro 'f' son

decrementado. Si 'd' es '0 ', el resultado es

colocado en W. Si 'd' es '1 ', el resultado es

se coloc de nuevo en el registro 'f' (por defecto).Si el resultado es '0 ', la siguiente instruccin,

que ya se capta, se desecha

y un NOP se ejecuta en lugar, haciendo

es una instruccin de dos ciclos.







modo cada vez que f 95 (5Fh). VerSeccin 26.2.3 "orientados a bytes y



Palabras: 1

Ciclos: 1 (2)




Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

ProcesoDatos

Escriba a

destino

Si saltar:

Q1 Q2 Q3 Q4

No

operacin

No

operacin

No

operacinNo

operacin


Q1 Q2 Q3 Q4

No

operacin

No

operacin

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No

operacin

No

operacin

No

operacin

No

operacinNo

operacin

No

operacin

Ejemplo: AQU DECFSZ CNT, 1, 1

GOTO BUCLE

CONTINUAR

Antes de Instruccin

PC = Direccin (AQU)


CNT CNT = - 1Si CNT = 0;

PC = Direccin (CONTINUE)

Si CNT 0;

PC = Direccin (HERE + 2)

DCFSNZ Disminuir f, Omitir si no 0

Sintaxis: DCFSNZ f {, {d, a}}

Operandos: 0 f 255

d [0,1]

a [0,1]

Operacin: (f) - 1 dest,

saltar si el resultado 0

Estado afectado: NingunoCodificacin: 0100 11da ffff ffff


decrementado. Si 'd' es '0 ', el resultado es


se coloc de nuevo en el registro 'f' (por defecto).

Si el resultado no es '0 ', la siguiente

instruccin, que ya se fue a buscar, es

descarta y se ejecuta un NOP

en cambio, lo que es un ciclo de dos

instrucciones.

Si 'a' es '0 ', se selecciona el Banco de Acceso.Si 'a' es '1 ', el BSR se utiliza para seleccionar el








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Palabras: 1

Ciclos: 1 (2)




Q1 Q2 Q3 Q4

Decode Leerregistrarse 'f'

Proceso

Datos

Escriba a

destino

Si saltar:

Q1 Q2 Q3 Q4

No

operacin

No

operacinNo

operacin

No

operacin


Q1 Q2 Q3 Q4

No

operacin

No

operacin

No

operacinNo

operacin

No

operacin

No

operacin

No

operacin

No

operacin

Ejemplo: AQU DCFSNZ TEMP, 1, 0ZERO:

NZERO:

Antes de Instruccin

TEMP =?


TEMP TEMP = - 1,

Si TEMP = 0;

PC = Direccin (CERO)

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Si TEMP 0;

PC = Direccin (NZERO)

PIC18F2455/2550/4455/4550

DS39632C pginas 328 Preliminar 2006 Microchip Technology Inc.

GOTO Incondicional Rama

Sintaxis: GOTO k

Operandos: 0 k 1048575

Operacin: k PC Estado afectado: Ninguno

Codificacin:

Primera palabra (k )

Segunda palabra (k )

1110

1111

1111

k19kkk

k7kkk

kkkk

kkkk0kkkk8

Descripcin: GOTO permite un salto incondicional

en cualquier lugar dentro de la totalidad

Rango de memoria de 2 Mbytes. El de 20 bits

valor "k" se carga en PC . GOTO

es siempre una instruccin de dos ciclos.

Palabras: 2

Ciclos: 2


Q1 Q2 Q3 Q4

Decode Leer literal

'K' ,No

operacin

Leer literal

'K' ,

Escriba a PC

No

operacin

No

operacin

No

operacinNo

operacin

Ejemplo: GOTO NO


PC = Direccin (NO)

INCF Incremento de f

Sintaxis: INCF f {, {d, a}}

Operandos: 0 f 255

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d [0,1]

a [0,1]

Operacin: (f) 1 dest

Estado afectado: C, CC, N, OV, Z



incrementado. Si 'd' es '0 ', el resultado es

colocado en W. Si 'd' es '1 ', el resultado esse coloc de nuevo en el registro 'f' (por defecto).










Modo de desplazamiento Literal "para ms detalles.Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

Proceso

Datos

Escriba a

destino

Ejemplo: INCF CNT, 1, 0

Antes de InstruccinCNT = FFh

Z = 0

C =?

#NAME?


CNT = 00h

Z = 1

C = 1

CC = 1


PIC18F2455/2550/4455/4550INCFSZ Incremento de f, Saltar si es 0

Sintaxis: INCFSZ f {, {d, a}}

Operandos: 0 f 255

d [0,1]

a [0,1]

Operacin: (f) 1 dest,

saltar si el resultado = 0


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incrementado. Si 'd' es '0 ', el resultado es


se coloc de nuevo en el registro 'f'. (Por defecto)

Si el resultado es '0 ', la siguiente instruccin,

que ya se capta, se desecha

y un NOP se ejecuta en lugar, haciendoes una instruccin de dos ciclos.










Modo de desplazamiento Literal "para ms detalles.Palabras: 1

Ciclos: 1 (2)




Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

Proceso

Datos

Escriba a

destinoSi saltar:

Q1 Q2 Q3 Q4

No

operacin

No

operacin

No

operacin

No

operacin

Si saltar y seguido por la instruccin 2 palabras:Q1 Q2 Q3 Q4

No

operacin

No

operacin

No

operacin

No

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operacin

No

operacin

No

operacin

No

operacin

Nooperacin

Ejemplo: AQU INCFSZ CNT, 1, 0

NZERO:

ZERO:

Antes de Instruccin

PC = Direccin (AQU)


CNT CNT = + 1

Si CNT = 0;


Si CNT 0;PC = Direccin (NZERO)

INFSNZ Incremento de f, Omitir si no 0

Sintaxis: INFSNZ f {, {d, a}}

Operandos: 0 f 255

d [0,1]

a [0,1]

Operacin: (f) 1 dest,

saltar si el resultado 0




incrementado. Si 'd' es '0 ', el resultado escolocado en W. Si 'd' es '1 ', el resultado es


Si el resultado no es '0 ', la siguiente

instruccin, que ya se fue a buscar, es

descarta y se ejecuta un NOP

en cambio, lo que es un ciclo de dos

instrucciones.




Si 'a' es '0 'y la instruccin ampliadaset est activada, funciona esta instruccin






Palabras: 1

Ciclos: 1 (2)

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Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

Proceso

DatosEscriba a

destino

Si saltar:

Q1 Q2 Q3 Q4

No

operacin

No

operacin

No

operacin

Nooperacin


Q1 Q2 Q3 Q4

No

operacin

No

operacin

No

operacin

No

operacin

Nooperacin

No

operacin

No

operacin

No

operacin

Ejemplo: AQU INFSNZ REG, 1, 0

ZERO

NZERO

Antes de InstruccinPC = Direccin (AQU)


REG = REG + 1

Si REG 0;

PC = Direccin (NZERO)

Si REG = 0;


PIC18F2455/2550/4455/4550

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IORLW Inclusive OR Literal con W

Sintaxis: IORLW k

Operandos: 0 k 255

Operacin:. (W) OR. k W

Estado afectado: N, Z

Codificacin: 0000 1001 kkkk kkkk

Descripcin: El contenido de W se ORed con elocho bits literal 'k'. El resultado se coloca en

W.

Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4

Decode Leer

literal "k"

Proceso

Datos

Escriba a WEjemplo: IORLW 35h

Antes de Instruccin

W = 9Ah


W = BFh

IORWF Inclusive OR W con f

Sintaxis: IORWF f {, {d, a}}

Operandos: 0 f 255

d [0,1]

a [0,1]

Operacin:. (W) OR. (F) dest

Estado afectado: N, ZCodificacin: 0001 00da ffff ffff

Descripcin: Inclusive OR W con registro 'f'. Si 'd' es

'0 ', El resultado se coloca en W. Si' d 'es '1',

el resultado se vuelve a colocar en el registro 'f'

(Por defecto).






en Indexed Literal Offset Dirigindosemodo cada vez que f 95 (5Fh). Ver




Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4

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Decode Leer

registrarse 'f'

Proceso

Datos

Escriba a

destino

Ejemplo: IORWF RESULTADO, 0, 1

Antes de InstruccinRESULTADO = 13h

W = 91h


RESULTADO = 13h

W = 93h


PIC18F2455/2550/4455/4550

FSR Cargar LFSR

Sintaxis: LFSR f, k

Operandos: 0 f 2

0 k 4095Operacin: k FSRf


Codificacin: 1110

1111

1110

0

00ff

k7kkk

k11kkk

kkkk

Descripcin: El literal 'k' de 12 bits se carga en el

Seleccionar archivo Registro apuntado por 'f'.Palabras: 2

Ciclos: 2


Q1 Q2 Q3 Q4

Decode Leer literal

'K' MSB

Proceso

Datos

Escribir

literal "k" MSB

a FSRfHDecode Leer literal

'K' LSB

Proceso

Datos

Escribe literal 'k'

a FSRfL

Ejemplo: LFSR 2, 3ABh


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FSR2H = 03h

FSR2L = ABh

MOVF Mueva f

Sintaxis: MOVF f {, {d, a}}

Operandos: 0 f 255

d [0,1]

a [0,1]

Operacin: f destEstado afectado: N, Z


Descripcin: El contenido del registro 'f' se mueven a

un destino depende de la

estado de 'd'. Si 'd' es '0 ', el resultado es



Ubicacin 'f' puede estar en cualquier lugar en el

Banco de 256 bytes.


Si 'a' es '1 ', el BSR se utiliza para seleccionar elBanco GPR (por defecto).








Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4Decode Leer

registrarse 'f'

Proceso

Datos

Escribe W

Ejemplo: MOVF REG, 0, 0

Antes de Instruccin

REG = 22h

W = FFh


REG = 22hW = 22h

PIC18F2455/2550/4455/4550


MOVFF Mueva f af

Sintaxis: fs MOVFF, fd

Operandos: 0 fs 4095

0 fd 4095

Operacin: (fs) fd

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Codificacin:

Primera palabra (fuente)

Segunda palabra (destin.)

1100

1111

ffff

ffffffff

ffff

ffffs

ffffd

Descripcin: El contenido de la fuente registran 'FS' son

trasladado a registro destino 'fd'.

Lugar de origen 'fs' puede estar en cualquier lugar

en el espacio de datos de 4096 bytes (000h a

FFFh) y la ubicacin de destino 'fd'

Tambin puede ser en cualquier lugar de 000h a

FFFh.El origen o el destino pueden ser W

(Una situacin especial til).

MOVFF es particularmente til para los

la transferencia de una ubicacin de memoria de datos a un

registro perifrico (tales como la transmisin

tampn o un puerto de E / S).

La instruccin MOVFF no puede utilizar el

PCL, TOSU, TOSH o TOSL como

registro de destino.

Palabras: 2

Ciclos: 2

Q ciclo de actividades:Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

(Src)

Proceso

Datos

No

operacin

Decode No

operacin

No maniquleer

No

operacin

Escribir

registrarse 'f'

(Dest)

Ejemplo: REG1 MOVFF, REG2

Antes de Instruccin

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REG1 = 33h

REG2 = 11h


REG1 = 33h

REG2 = 33h

MOVLB Mueva Literal a Menor Nibble en BSR

Sintaxis: MOVLW k

Operandos: 0 k 255Operacin: k BSR



Descripcin: El literal 'k' de ocho bits se carga en el

Bank Select Register (BSR). El valor

de BSR permanece siempre '0 '

independientemente del valor de K7: K4.

Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4Decode Leer

literal "k"

Proceso

Datos

Escribe literal

'K' a BSR

Ejemplo: MOVLB 5

Antes de Instruccin

BSR Registro = 02h


BSR Registro = 05h

2006 Microchip Technology Inc. DS39632C pginas Preliminar 333PIC18F2455/2550/4455/4550

Movlw Mueva Literal a W

Sintaxis: MOVLW k

Operandos: 0 k 255

Operacin: k W



Descripcin: El literal "k" de ocho bits se carga en W.

Palabras: 1

Ciclos: 1

Q ciclo de actividades:Q1 Q2 Q3 Q4

Decode Leer

literal "k"

Proceso

Datos

Escriba a W

Ejemplo: MOVLW 5Ah


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W = 5Ah

MOVWF Mover W af

Sintaxis: MOVWF f {,} un

Operandos: 0 f 255

a [0,1]

Operacin: (W) f


Codificacin: 0110 111a ffff ffffDescripcin: Mover datos de W para registrarse 'f'.

Ubicacin 'f' puede estar en cualquier lugar en el

Banco de 256 bytes.








Seccin 26.2.3 "orientados a bytes yOperaciones con bits orientada en indiciada


Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

Proceso

Datos

Escribir

registrarse 'f'Ejemplo: MOVWF REG, 0

Antes de Instruccin

W = 4Fh

REG = FFh


W = 4Fh

REG = 4Fh

PIC18F2455/2550/4455/4550


MULLW Multiplicar Literal con W

Sintaxis: MULLW kOperandos: 0 k 255

Operacin: (W) x k PRODH: Prdl



Descripcin: Una multiplicacin sin signo se lleva

entre el contenido de W y el

8-bit literal 'k'. El resultado de 16 bits es

colocado en PRODH: Prdl par de registros.

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PRODH contiene el byte alto.

W es sin cambios.

Ninguno de los indicadores de estado se ven afectados.

Tenga en cuenta que ni el desbordamiento ni Carry es

posible en esta operacin. Un resultado de cero

es posible, pero no detectado.

Palabras: 1

Ciclos: 1Q ciclo de actividades:

Q1 Q2 Q3 Q4

Decode Leer

literal "k"

Proceso

Datos

Escribir

registros

PRODH:

Prdl

Ejemplo: MULLW 0C4hAntes de Instruccin

W = E2H

PRODH =?

Prdl =?


W = E2H

PRODH = ADH

Prdl = 08h

MULWF Multiplicar W con f

Sintaxis: MULWF F {,} un

Operandos: 0 f 255

a [0,1]Operacin: (W) x (f) PRODH: Prdl



Descripcin: Una multiplicacin sin signo se lleva

entre el contenido de W y el

registrarse file location 'f'. El de 16 bits

resultado se almacena en el PRODH: Prdl

regstrese par. PRODH contiene la

byte alto. Tanto W y 'f' son

sin cambios.

Ninguno de los indicadores de estado se ven afectados.Tenga en cuenta que ni el desbordamiento ni Carry es

posible en esta operacin. Un cero

resultado es posible, pero no detecta.

Si 'a' es '0 ', el Banco El acceso es

seleccionada. Si 'a' es '1 ', se utiliza la BSR

para seleccionar el banco GPR (por defecto).


set est activada, esta instruccin

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opera en Indexed Literal Offset

Modo de direccionamiento siempre

f 95 (5Fh). Consulte la Seccin 26.2.3

Byte orientada y orientada-Bit

Las instrucciones de indexado Literal Offset

Mode para obtener ms informacin.

Palabras: 1

Ciclos: 1Q ciclo de actividades:

Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

Proceso

Datos

Escribir

registros

PRODH:

Prdl

Ejemplo: MULWF REG, 1Antes de Instruccin

W = C4h

REG = B5h

PRODH =?

Prdl =?


W = C4h

REG = B5h

PRODH = 8Ah

Prdl = 94h


PIC18F2455/2550/4455/4550NEGF Negar f

Sintaxis: NEGF F {,} un

Operandos: 0 f 255

a [0,1]

Operacin: (f) 1 f

Estado afectado: N, OV, C, DC, Z


Descripcin: Location 'f' es negado el uso de dos de

complementar. El resultado se coloca en el

posicin de la memoria de datos 'f'.

Si 'a' es '0 ', se selecciona el Banco de Acceso.Si 'a' es '1 ', el BSR se utiliza para seleccionar el








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Palabras: 1

Ciclos: 1


Q1 Q2 Q3 Q4

Decode Leer

registrarse 'f'

ProcesoDatos

Escribir

registrarse 'f'

Ejemplo: NEGF REG, 1

Antes de Instruccin

REG = 0011 1010 [3Ah]


REG = 1100 0110 [C6H]

NOP Sin operacin

Sintaxis: NOP

Operandos: NingunoOperacin: Ninguna operacin


Codificacin: 0000

1111

0

xxxx

0

xxxx

0

xxxx

Descripcin: No hay operacin.

Palabras: 1Ciclos: 1


Q1 Q2 Q3 Q4

Decode No

operacin

No

operacin

No

operacin

Ejemplo:

Ninguno.PIC18F2455/2550/4455/4550


POP Pop Top of Return Stack

Sintaxis: POP

Operandos: Ninguno

Operacin: (TOS) Cuchara bits


Codificacin: 0000 0000 0000 0110

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Descripcin: El valor de TOS se quit el retorno

apilar y se desecha. El valor TOS

a continuacin, se convierte en el valor anterior que

se inserta en la pila de retorno.

Esta instruccin se proporciona para permitir

al usuario a manejar adecuadamente el retorno

apilar para incorporar una pila de software.

Palabras: 1Ciclos: 1


Q1 Q2 Q3 Q4

Decode No

operacin

Pop TOS

valor

No

operacin

18f4550 español

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