17127_digital electronics presentation

7/30/2019 17127_digital Electronics Presentation

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SEQUENTIAL CIRCUITS

In digital circuit theory, sequential logic is a type of logic circuit

whose output depends not only on the present value of its input

signals but on the past history of its inputs.


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Introduction 2

Introduction

A sequential circuit consists of afeedbackpath, and employs some memory elements.

Combinational

logic

Memory

elements

Combinational

outputs Memory outputs

External inputs

Sequential circuit = Combinational logic + Memory Elements


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Introduction 3

Introduction

There are two types of sequential circuits:synchronous: outputs change only at specific

time

asynchronous: outputs change at any time

Bistable logic devices: latches andflip-flops.

Latches and flip-flops differ in the method used

for changing their state.


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Memory Elements 4

Memory Elements

Memory element: a device which can remembervalue indefinitely, or change value on commandfrom its inputs.

Characteristic table:Command(at time t)

Q(t) Q(t+1)

Set X 1

Reset X 0

0 0Memorise /No Change 1 1

commandMemory

element stored valueQ

Q(t): current state

Q(t+1) or Q+: next state


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Memory Elements 5

Memory Elements

Memory element with clock. Flip-flops are memoryelements that change state on clock signals.

Clock is usually a square wave.

commandMemory

element stored valueQ

clock

Positive edges Negative edges

Positive pulses


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Memory Elements 6

Memory Elements

Two types of triggering/activation:pulse-triggered

edge-triggered

Pulse-triggered

latchesON = 1, OFF = 0

Edge-triggered flip-flops

positive edge-triggered (ON = from 0 to 1; OFF = othertime)

negative edge-triggered (ON = from 1 to 0; OFF =other time)


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S-R Latch 7

S-R Latch

Complementaryoutputs: Q and Q'. When Q is HIGH, the latch is in SETstate.

When Q is LOW, the latch is in RESETstate.

For active-HIGH inputS-R latch(also known as NORgate latch),

R=HIGH (and S=LOW)a RESET state

S=HIGH (and R=LOW)a SET state

both inputs LOWa no change

both inputs HIGHa

Q and Q'both LOW (invalid)!

S

R

Q

Q


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S-R Latch 8

S-R Latch

For active-LOW inputS'-R' latch(also known asNAND gate latch),R'=LOW (and S'=HIGH)a RESET state

S'=LOW (and R'=HIGH)a SET state

both inputs HIGHa no change

both inputs LOWaQ and Q'both HIGH (invalid)!

Drawback of S-R latch: invalid conditionexists and must be avoided.


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S-R Latch 9

S-R Latch

Characteristics table for active-high input S-R latch:

Characteristics table for active-low input S'-R' latch:

S R Q Q'

0 0 NC NC No change. Latchremained in present state.

1 0 1 0 Latch SET.

0 1 0 1 Latch RESET.

1 1 0 0 Invalid condition.

S' R' Q Q'

1 1 NC NC No change. Latchremained in present state.

0 1 1 0 Latch SET.

1 0 0 1 Latch RESET.

0 0 1 1 Invalid condition.

S

R

Q

Q'

S

R

Q

Q'


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S-R Latch 10

S-R Latch

Active-HIGH input S-R latch

Active-LOW input S-R latch

R

S

Q

Q'

S R Q Q'

1 0 1 0 initial

0 0 1 0 (afer S=1, R=0)

0 1 0 1

0 0 0 1 (after S=0, R=1)

1 1 0 0 invalid!

S' R' Q Q'

1 0 0 1 initial1 1 0 1 (afer S'=1, R'=0)

0 1 1 0

1 1 1 0 (after S'=0, R'=1)

0 0 1 1 invalid!

S'

R'

Q

Q'

S'

R'

Q

Q'

0

1

1

0

0

0

1

0

1

0

0

1

0

0

0

1

1

1

0

0


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Gated S-R Latch 11

Gated S-R Latch

S-R latch + enable input(EN) and 2 NANDgatesgated S-R latch.

S

R

Q

Q'

EN

S

ENR

Q

Q'


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Gated S-R Latch 12

Gated S-R Latch

Outputs change (if necessary) only when EN isHIGH.

Under what condition does the invalid state occur?

Characteristic table:

Q(t) S R Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 indeterminate

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 indeterminate

EN=1

S R Q(t+1)

0 0 Q(t) No change

0 1 0 Reset

1 0 1 Set

1 1 indeterminate

Q(t+1) = S + R'.Q

S.R = 0


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JK latch

JK latch

J K Qnext Comment

0 0 Q No change

0 1 0 Reset

1 0 1 Set

1 1 Q Toggle

The JK latch is an SR latch that is made to toggle

its output when passed the restricted

combination of 11


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Gated D Latch 14

Gated D Latch

Make R input equal to S'

gated D latch. D latch eliminates the undesirable condition

of invalid state in the S-R latch.

D

ENQ

Q'

DQ

Q'

EN


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Gated D Latch 15

Gated D Latch

When EN is HIGH,D=HIGH latch is SETD=LOW latch is RESET

Hence when EN is HIGH, Qfollows the D (data)input.

Characteristic table:

When EN=1, Q(t+1) = D

EN D Q(t+1)

1 0 0 Reset

1 1 1 Set0 X Q(t) No change


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Gated D Latch 16

Latch Circuits: Not Suitable

Latch circuits are not suitable in synchronous logiccircuits.

When the enable signal is active, the excitationinputs are gated directly to the output Q. Thus, anychange in the excitation input immediately causes a

change in the latch output.

The problem is solved by using a special timingcontrol signal called a clockto restrict the times atwhich the states of the memory elements may

change. This leads us to the edge-triggered memory

elements calledflip-flops.


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Edge-Triggered Flip-flops 17

Edge-Triggered Flip-flops

Flip-flops: synchronous bistable devices Output changes state at a specified point on a

triggering input called the clock.

Change state either at thepositive edge (rising

edge) or at the negative edge (falling edge) of theclock signal.

Positive edges Negative edges

Clock signal


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Edge-Triggered Flip-flops 18

Edge-Triggered Flip-flops

S-R, D and J-K edge-triggered flip-flops. Notethe > symbol at the clock input.

S

C

R

Q

Q'

S

CR

Q

Q'

D

CQ

Q'

D

C

Q

Q'

J

C

K

Q

Q'

J

CK

Q

Q'

Positive edge-triggered flip-flops

Negative edge-triggered flip-flops


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SR Flip-flop 19

S-R Flip-flop S-R flip-flop: on the triggering edge of the clock

pulse,S=HIGH (and R=LOW)a SET stateR=HIGH (and S=LOW)a RESET stateboth inputs LOWa no changeboth inputs HIGHa invalid

Characteristic table of positive edge-triggered S-Rflip-flop:

X = irrelevant (dont care)

= clock transition LOW to

HIGH

S R CLK Q(t+1) Comments

0 0 X Q(t) No change

0 1 0 Reset

1 0 1 Set

1 1 ? Invalid


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SR Flip-flop 20

S-R Flip-flop

It comprises 3 parts:a basic NAND latch

apulse-steering circuit

apulse transition detector(or edge detector) circuit

The pulse transition detector detects a rising (orfalling) edge and produces a very short-durationspike.


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SR Flip-flop 21

S-R Flip-flop

The pulse transition detector.S

Q

Q'

CLKPulse

transition

detector R

Positive-going transition

(rising edge)

CLKCLK'

CLK*

CLK'

CLK

CLK*

Negative-going transition

(falling edge)

CLK'

CLK

CLK*

CLKCLK'

CLK*


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D Flip-flop 22

D Flip-flop D flip-flop: single input D (data)

D=HIGHa SET state

D=LOWa RESET state

Q follows D at the clock edge.

Convert S-R flip-flop into a D flip-flop: add an inverter.

A positive edge-triggered D flip-flop

formed with an S-R flip-flop.

S

C

R

Q

Q'

CLK

D D CLK Q(t+1) Comments

1 1 Set

0 0 Reset

= clock transition LOW to

HIGH


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D Flip-flop 23

D Flip-flop

Application: Parallel data transfer.To transfer logic-circuit outputsX, Y,Zto flip-flops Q1, Q2 and Q3 for storage.

* After occurrence of negative-going

transition

Q1 =

X*

D

CLK

Q

Q'

Q2 =

Y*

D

CLK

Q

Q'

Q3 =

Z*

D

CLK

Q

Q'

Combinational

logic circuit

Transfer

X

Y

Z


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J-K Flip-Ffop 24

J-K Flip-flop J-K flip-flop: Q and Q' are fed back to the pulse-

steering NAND gates.

No invalid state.

Include a toggle state.

J=HIGH (and K=LOW)a SET stateK=HIGH (andJ=LOW)a RESET state

both inputs LOWa no change

both inputs HIGHa toggle


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J-K Flip-flop 25

J-K Flip-flop J-K flip-flop.

Characteristic table.

JQ

Q'

CLKPulse

transitiondetector

K

J K CLK Q(t+1) Comments

0 0 Q(t) No change

0 1 0 Reset1 0 1 Set

1 1 Q(t)' Toggle

Q J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0Q(t+1) =J.Q'+ K'.Q


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T Flip-flop 26

T Flip-flop T flip-flop: single-input version of the J-K flip flop,

formed by tying both inputs together.

Characteristic table.T CLK Q(t+1) Comments

0 Q(t) No change1 Q(t)' Toggle

Q T Q(t+1)

0 0 00 1 1

1 0 1

1 1 0

Q(t+1) = T.Q'+ T'.Q

TQ

Q'

CLKPulse

transition

detector

J

C

K

Q

Q'

CLK

T


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T Flip-flop 27

T Flip-flop

Application: Frequency division.

J

C

K

Q

CLK

High

CLK

Q

Divide clock frequency by 2.

J

C

K

QA

CLK

High

J

C

K

QB

High

CLK

QA

QB

Divide clock frequency by 4.


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Asynchronous Inputs 28

Asynchronous Inputs S-R, D and J-K inputs are synchronous inputs, as

data on these inputs are transferred to the flip-flops output only on the triggered edge of the clockpulse.

Asynchronous inputs affect the state of the flip-flopindependent of the clock; example:preset(PRE)and clear(CLR) [or direct set(SD) and direct reset(RD)]

When PRE=HIGH, Q is immediately set to HIGH.

When CLR=HIGH, Q is immediately cleared to LOW.

Flip-flop in normal operation mode when both PREand CLR are LOW.


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Asynchronous Inputs 29

Asynchronous Inputs

A J-K flip-flop with active-LOW preset and clearinputs.

JQ

Q'

CLK

Pulsetransition

detectorK

PRE

CLR

J

C

K

Q

Q'

PRE

CLR

PRE

CLR

CLK

QPreset Toggle ClearJ = K= HIGH


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SR Master-Slave Flip-Flop

Read input at first half of clock cycle

Output only changed at second half of clock cycle

The value that is produced at the output is theresponse of the value that is stored in the master stageimmediately before negative edge occurred.

S

C

R

S

C

R

Master Slave

Q

Q

Y

Y

S

C

R

From Figure 5-9, page 216


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Master slave structure provides following

functionalities to the logic:

The output may only change once

The change in the output is triggered at negative

edge of clock

The change may occur during negative clock only


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Shift Registers

Registers 1.33


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Shift Register Applications Shift Registers are an important Flip-Flop configuration with a

wide range of applications, including:

Computer and Data Communications

Serial and Parallel Communications

Multi-bit number storage Sequencing

Basic arithmetic such as scaling (a serial shift to theleft or right will change the value of a binary number

a power of 2) Logical operations

Registers 1.34


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Parallel versus Serial

Serial communications: provides a binary number as asequence of binary digits, one after another, through one

data line.

Parallel communications: provides a binary number as

binary digits through multiple data lines at the same time.

Registers 1.35


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Shift Registers

Shift Registers are devices that store and move data bits in serial (to

the left or the right),

..or in parallel,

..or a combination of serial and parallel.

Registers 1.36


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Configuration

In Shift Registers, the binary digit transfers (shifts) from the output

of one flip-flop to the input of the next individual Flip-Flop at

every clock edge.

Once the binary digits are shifted in, the individual Flip-Flops will

each retain a bit, and the whole configuration will retain a binary

number.

Registers 1.37


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Construction

Shift registers are constructed from flip-flops due to their characteristics:

Edge-triggered devices Output state retention

Each Flip-Flop in a shift register can retain one binary digit.

For instance, if a 5-bit binary number needs to be stored and shifted, 5 flip-flops

are required.

Each binary digit transfer operation requires a clock edge.

Asynchronous inputs are useful in resetting the whole configuration.

Registers 1.38


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Shift Register Construction

Shift registers are comprised of D Flip-Flopsthat share a common clock input.

D Q

Q

D Q

Q

D Q

Q

Registers 1.39


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Combinations of Data Transfer Methods

SISO: Serial In, Serial Out

SIPO: Serial In, Parallel Out

PISO: Parallel In, Serial Out

PIPO: Parallel In, Parallel Out

How many clock edges are required for each operation?

10110 10110

10110

10110

10110

1011010110

10110

Registers 1.40


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SISO Flip-Flop Shift Register a Serial In Serial Out shift register has a single

input and a single output

D Q

Q

D Q

Q

D Q

Q

Input Output

Registers 1.41


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SIPO Flip-Flop Shift Register

a Serial In Parallel Out shift register has a singleinput and access to all outputs

D Q

Q

D Q

Q

D Q

Q

Input

Output Output Output

Registers 1.42


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PISO Flip-Flop Shift Register

a Parallel In Serial Out shift register requiresadditional gates, and the parallel input must

revert to logic low.Input

D Q

Q

Input

Output

Input

D Q

Q

D Q

Q

Registers 1.43


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PISO Flip-Flop Shift Register


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PIPO Flip-Flop Shift Register

a Parallel In Parallel Out register has thesimplest configuration. It represents a memory

device.

D Q

Q

Input

Output

D Q

Q

Output

D Q

Q

Output

Input Input

Registers 1.45


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Application: Parallel transferring the contents of a Register

to another register.

Describe where this circuit

combination may be used.

Registers 1.46


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Bidirectional Shift register

A binary number can be divided by 2 by shifting it one stage to theright similarly number can be multiplied by 2 by shifting it to the

left

A bidirectional, or reversible, shift register is one in which the data

can be shift either left or right


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JK Shift Registers

J-K Shift registers are seldom used, as two inputs (J,K) arerequired to load the first flip-flop (note all others receive only

set or reset inputs).

Input OutputJ Q

K Q

J Q

K Q

J Q

K QInput

Registers 1.48


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Ring Counter

A ring counter takes the serial output of the last Flip-Flop of a shiftregister and provides it to the serial input of the first Flip-Flop.

Ring Counters are also known as re-circulating shift registers.

Registers 1.49

i


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Ring Counter

Registers 1.50

with initial register values of 100, the repeating pattern is: 100,

010, 001, 100... .


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Self-Starting or Load on Power-up

Note that one of the registers must be pre-

loaded with a 1 (or 0) in order to operate

properly.

Registers 1.51


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Johnson Counter A Johnson Counter re-circulates the last flip-flop Q (inverted)

output back to the input of the first Flip-Flop.

It doesnt require an initialization value, and will provide a

predictable output state sequence.

Registers 1.52


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Re-Circulating Counters

Johnson Counter

0000

1000

1100

1110

1111

01110011

0001

A 4-bit Johnson counter has a modulus of8, meaning thereare 8 unique output states.

8 unique states

Registers 1.53


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State Diagram A State Diagram is used to describe the sequence of

output states of a circuit.

The state diagram for the previous Johnson counter looks

like this:

1000

1100

1110

1111

0111

0011

0001

0000

Registers 1.54

St t R iti


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Registers 1.55

State Recognition

One application of registers is to recognize a specific binarynumber. Sequences of bits are loaded in series into a

register. External detection gates will identify if the value

matches a predetermined value:

55

Comparison of two values


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Registers 1.56

Comparison of two values

Values stored in shift registers can be compared by using the following circuit :

What is the output be if both binary inputs are the same?56


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Delay Line

A SISO shift register may be used to introduce delay del t in

digital signals

del t = N x (1/fc)

N= number of stages

Fc = clock frequency

D Q

Q

D Q

Q

D Q

Q

Input Output


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Introduction: Counters 58

Introduction: Counters Counters are circuits that cycle through a specified

number of states.

Two types of counters:

synchronous (parallel) counters

asynchronous (ripple) counters Ripple counters allow some flip-flop outputs to be

used as a source of clock for other flip-flops.

Synchronous counters apply the same clock to all

flip-flops.


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Asynchronous (Ripple) Counters


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Asynchronous (Ripple) Counters 60

Asynchronous (Ripple) Counters

Asynchronous counters: the flip-flops do notchange states at exactly the same time as they donot have a common clock pulse.

Also known as ripple counters, as the input clock

pulse ripples through the counter cumulativedelay is a drawback.

n flip-flops a MOD (modulus) 2n

counter.(Note: A MOD-xcounter cycles throughxstates.)

Output of the last flip-flop (MSB) divides theinput clock frequency by the MOD number of thecounter, hence a counter is also afrequencydivider.


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Asynchronous (Ripple) Counters Example: 2-bit ripple binary counter.

Output of one flip-flop is connected to the clockinput of the next more-significant flip-flop.

K

J

K

J

HIGH

Q0 Q1

Q0

FF1FF0

CLK CC

Timing diagram00 01 10 11 00 ...

4321CLK

Q0

Q0

Q1

1 1

1 1

0

0 0

0 0

0


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Asynchronous (Ripple) Counters Example: 3-bit ripple binary counter.

K

J

K

JQ0 Q1

Q0

FF1FF0

CC

K

J

Q1C

FF2

Q2

CLK

HIGH

4321CLK

Q0

Q1

1 1

1 1

0

0 0

0 0

0

8765

1 10 0

1 10 0

Q2 0 00 0 1 1 11 0

Recycles back to 0


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Asynchronous (Ripple) Counters Propagation delays in an asynchronous (ripple-

clocked) binary counter.

If the accumulated delay is greater than the clockpulse, some counter states may be misrepresented!

4321CLK

Q0

Q1

Q2

tPLH

(CLK to Q0)

tPHL (CLK to Q0)

tPLH(Q0 toQ1)

tPHL (CLK to Q0)

tPHL (Q0 toQ1)

tPLH(Q1 toQ2)


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Asynchronous (Ripple) Counters Example: 4-bit ripple binary counter (negative-

edge triggered).

K

J

K

JQ1Q0

FF1FF0

CC

K

J

C

FF2

Q2

CLK

HIGH

K

J

C

FF3

Q3

CLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3


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Asynchronous Counters with MOD number

< 2^n 65

Asyn. Counters with MOD no. < 2n

States may be skipped resulting in a truncated

sequence.

Technique: force counter to recycle before goingthrough all of the states in the binary sequence.

Example: Given the following circuit, determine thecounting sequence (and hence the modulus no.)

K

JQ

Q

CLK

CLRK

JQ

Q

CLK

CLRK

JQ

Q

CLK

CLR

C B A

B

C

AllJ, K

inputs are

1 (HIGH).


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< 2^n 66


Example (contd):

K

JQ

Q

CLK

CLRK

JQ

Q

CLK

CLRK

JQ

Q

CLK

CLR

C B A

B

C

AllJ, K

inputs are

1 (HIGH).

A

B

1 2

C

NAND

Output

10

3 4 5 6 7 8 9 10 11 12Clock MOD-6 counter

produced by clearing

(a MOD-8 binary

counter) when count

of six (110) occurs.


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< 2^n 67


Example (contd): Counting sequence ofcircuit (in CBA order).

A

B

C

NANDOutput

10

1 2 3 4 5 6 7 8 9 10 11 12

Clock

111 000001

110

101

100

010

011

Temporary

stateCounter is a MOD-6

counter.

0

0

0

1

0

0

0

1

0

1

1

0

0

0

1

1

0

1

0

0

0

1

0

0


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< 2^n 68


Exercise: How to construct an asynchronous MOD-5 counter? MOD-7 counter? MOD-12 counter?

Question: The following is a MOD-? counter?

K

JQ

QCLR

C B A

C

DEF

AllJ = K = 1.

K

JQ

QCLR

K

JQ

QCLR

K

JQ

QCLR

K

JQ

QCLR

K

JQ

QCLR

DEF


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< 2^n 69


Decade counters (or BCD counters) are counters

with 10 states (modulus-10) in their sequence.They are commonly used in daily life (e.g.: utilitymeters, odometers, etc.).

Design an asynchronous decade counter.

D

CLK

HIGH

K

J

C

CLR

Q

K

J

C

CLR

QC

K

J

C

CLR

QB

K

J

C

CLR

QA

(A.C)'

n


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< 2^n 70


Asynchronous decade/BCD counter (contd).

D

C

1 2

B

NANDoutput

3 4 5 6 7 8 9 10Clock

11

A

D

CLK

HIGH

K

J

C

CLR

Q

K

J

C

CLR

QC

K

J

C

CLR

QB

K

J

C

CLR

QA (A.C)'

0

0

0

0

1

0

0

0

0

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

0

1

1

0

1

1

1

0

0

0

0

1

1

0

0

1

0

0

0

0


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Asynchronous Down Counters 71

Asynchronous Down Counters So far we are dealing with up counters. Down

counters, on the other hand, count downwardfrom a maximum value to zero, and repeat.

Example: A 3-bit binary (MOD-23) down counter.

K

J

K

JQ1Q0

CC

K

J

C

Q2

CLK

1

Q

Q'

Q

Q'

Q

Q'

Q

Q'

3-bit binary

up counter

3-bit binary

down counter

1

K

J

K

JQ1Q0

CC

K

J

C

Q2

CLK

Q

Q'

Q

Q'

Q

Q'

Q

Q'


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Asynchronous Down Counters

Asynchronous Down Counters Example: A 3-bit binary (MOD-8) down counter.

4321CLK

Q0

Q1

1 1

1 0

0

0 1

0 0

0

8765

1 10 0

1 01 0

Q2 1 10 1 1 0 00 0

001

000111

010

011

100

110

101

1

K

J

K

JQ1Q0

CC

K

J

C

Q2

CLK

Q

Q'

Q

Q'

Q

Q'

Q

Q'


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Cascading Asynchronous Counters 73

Cascading Asynchronous Counters Larger asynchronous (ripple) counter can be

constructed by cascading smaller ripple counters. Connect last-stage output of one counter to the

clock input of next counter so as to achieve higher-modulus operation.

Example: A modulus-32 ripple counter constructedfrom a modulus-4 counter and a modulus-8counter.

K

J

K

J

Q1Q0

CCCLKQ

Q'

Q

Q'

Q

Q'K

J

K

J

Q3Q2

CC

K

JC

Q4

Q

Q'

Q

Q'

Q

Q'

Q

Q'

Modulus-4 counter Modulus-8 counter


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Cascading Asynchronous Counters Example: A 6-bit binary counter (counts from

0 to 63) constructed from two 3-bit counters.

3-bit

binary counter

3-bit

binary counterCount

pulse

A0 A1 A2 A3 A4 A5

A5 A4 A3 A2 A1 A0

0 0 0 0 0 00 0 0 0 0 1

0 0 0 : : :0 0 0 1 1 10 0 1 0 0 00 0 1 0 0 1: : : : : :


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Cascading Asynchronous Counters If counter is a not a binary counter, requires

additional output.

Example: A modulus-100 counter using twodecade counters.

CLK

Decade

counterQ3 Q2 Q1 Q0

C

CTENTC

1 Decade

counterQ3 Q2 Q1 Q0

C

CTENTC

freq

freq/10freq/10

0

TC= 1 when counter recycles to 0000


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Synchronous (Parallel) Counters 76

Synchronous (Parallel) Counters Synchronous (parallel) counters: the flip-flops are

clocked at the same time by a common clock pulse. We can design these counters using the sequential

logic design process.

Example: 2-bit synchronous binary counter (using T

flip-flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs

A1 A0 A1+

A0+

TA1 TA0

0 0 0 1 0 10 1 1 0 1 1

1 0 1 1 0 11 1 0 0 1 1

0100

1011


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Synchronous (Parallel) Counters Example: 2-bit synchronous binary counter (using T

flip-flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs

A1 A0 A1+

A0+

TA1 TA0

0 0 0 1 0 1

0 1 1 0 1 11 0 1 1 0 11 1 0 0 1 1

TA1 =A0

TA0 = 1

1

K

J

K

JA1A0

CC

CLK

Q

Q'

Q

Q'

Q

Q'

( )


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Synchronous (Parallel) Counters Example: 3-bit synchronous binary counter (using T

flip-flops, or JK flip-flops with identical J, K inputs).Present Next Flip-flop

state state inputs

A2 A1 A0 A2+ A1

+ A0+ TA2 TA1 TA0

0 0 0 0 0 1 0 0 10 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 11 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1

TA2 = A1.A0

A2

A1

A0

1

1

TA1 = A0 TA0 = 1

A2

A1

A0

1

1 1

1

A2

A1

A0

1 1 1

11 1 1

1

h ( ll l)


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Synchronous (Parallel) Counters Example: 3-bit synchronous binary counter (contd).

TA2 = A1.A0 TA1 = A0TA0 = 1

1

A2

CP

A1 A0

K

Q

J K

Q

J K

Q

J

h ( ll l)


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Synchronous (Parallel) Counters Note that in a binary counter, the nth bit (shown

underlined) is always complemented whenever

0111110000

or 1111100000

Hence, Xn is complemented wheneverXn-1Xn-2 ... X1X0= 1111.

As a result, if T flip-flops are used, thenTXn = Xn-1 . Xn-2 . ... . X1 .X0

S h ( ll l) C


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Synchronous (Parallel) Counters Example: 4-bit synchronous binary counter.

TA3 =A2 .A1.A0

TA2 =A1.A0

TA1 =A0

TA0 = 1

1

K

J

K

JA1A0

CC

CLK

Q

Q'

Q

Q'

Q

Q'K

JA2

C

Q

Q'K

JA3

C

Q

Q'

A1.A0 A2.A1.A0

S h (P ll l) C


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Synchronous (Parallel) Counters Example: Synchronous decade/BCD counter.

Clock pulse Q3 Q2 Q1 Q0

Initially 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 1

4 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 1

10 (recycle) 0 0 0 0

T0 = 1

T1 = Q3'.Q0

T2 = Q1.Q0T3 = Q2.Q1.Q0 + Q3.Q0

S h (P ll l) C


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Synchronous (Parallel) Counters Example: Synchronous decade/BCD counter

(contd).

T0 = 1

T1 = Q3'.Q0

T2 = Q1.Q0

T3 = Q2.Q1.Q0 + Q3.Q0

1 Q1

Q0

CLK

T

C

Q

Q'

Q

Q'

Q2 Q3T

C

Q

Q'

Q

Q'

T

C

Q

Q'

Q

Q'

T

C

Q

Q'

Q

Q'

U /D S h C


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Up/Down Synchronous Counters 84

Up/Down Synchronous Counters Up/down synchronous counter: a

bidirectionalcounter that is capable ofcounting either up or down.

An input (control) line Up/Down (or simplyUp) specifies the direction of counting.

Up/Down = 1 Count upward

Up/Down = 0 Count downward

U /D S h C t


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Up/Down Synchronous Counters Example: A 3-bit up/down synchronous

binary counter.Clock pulse Up Q2 Q1 Q0 Down

0 0 0 01 0 0 12 0 1 0

3 0 1 14 1 0 05 1 0 16 1 1 07 1 1 1

TQ0 = 1TQ1 = (Q0.Up) + (Q0'.Up')

TQ2 = ( Q0.Q1.Up )+ (Q0'. Q1'. Up')

Up counterTQ0 = 1

TQ1 = Q0

TQ2 = Q0.Q1

Down counterTQ0 = 1

TQ1 = Q0

TQ2 = Q0.Q1

U /D S h C t


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Up/Down Synchronous Counters Example: A 3-bit up/down synchronous

binary counter (contd).TQ0 = 1

TQ1 = (Q0.Up) + (Q0'.Up')

TQ2 = ( Q0.Q1.Up )+ (Q0'. Q1'. Up')

1

Q1Q0

CLK

T

C

Q

Q'

Q

Q'

T

C

Q

Q'

Q

Q'

T

C

Q

Q'

Q

Q'

Up

Q2

D i i S h C t


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Designing Synchronous Counters 87

Designing Synchronous Counters

Example: A 3-bit Graycode counter (using JK

flip-flops).

100

000

001

101

111

110

011

010

Present Next Flip-flopstate state inputs

Q2 Q1 Q0 Q2+

Q1+

Q0+

JQ2 KQ2 JQ1 KQ1 JQ0 KQ0

0 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 1 0 X 1 X X 00 1 0 1 1 0 1 X X 0 0 X

0 1 1 0 1 0 0 X X 0 X 11 0 0 0 0 0 X 1 0 X 0 X1 0 1 1 0 0 X 0 0 X X 11 1 0 1 1 1 X 0 X 0 1 X1 1 1 1 0 1 X 0 X 1 X 0


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D i i S h C t


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Designing Synchronous Counters 89

Designing Synchronous Counters

3-bit Gray code counter: logic diagram.

JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2Q1)'

KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2Q1

Q1Q0

CLK

Q2J

C

Q

Q'K

J

C

Q

Q'K

J

C

Q

Q'KQ2'

Q0

'

Q1'

D di A C t


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Decoding A Counter 90

Decoding A Counter Decoding a counter involves determining

which state in the sequence the counter is in. Differentiate between active-HIGH and active-

LOWdecoding.

Active-HIGH decoding: output HIGH if the

counter is in the state concerned. Active-LOW decoding: output LOW if the

counter is in the state concerned.

D di A C t


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Decoding A Counter Example: MOD-8 ripple counter (active-HIGH

decoding).

A'B'

C'

1 2 3 4 5 6 7 8 9Clock

HIGH only on count

ofABC= 000

A'B'C

HIGH only on count

ofABC= 001

A'BC'

HIGH only on count

ofABC= 010

100

ABC

HIGH only on count

ofABC= 111

...

Decoding A Counter


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Decoding A Counter Example: To detect that a MOD-8 counter is in

state 0 (000) or state 1 (001).

A'

B'

1 2 3 4 5 6 7 8 9Clock

HIGH only on count

ofABC= 000 or

ABC= 001

100

Example: To detect that a MOD-8 counter is in the odd

states (states 1, 3, 5 or 7), simply use C.

C

1 2 3 4 5 6 7 8 9

Clock

HIGH only on count

ofodd states

100

A'B'C'A'B'C

Counters with Parallel Load


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Counters with Parallel Load 93

Counters with Parallel Load Counters could be augmented with parallel load

capability for the following purposes:To start at a different state

To count a different sequence

As more sophisticated register withincrement/decrement functionality.

Counters with Parallel Load


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Counters with Parallel Load 94

Counters with Parallel Load Different ways of getting a MOD-6 counter:

Count = 1

Load = 0

CPI4 I3 I2 I1

Count = 1

Clear = 1

CP

A4A3A2A1

Inputs = 0

Load

(a) Binary states 0,1,2,3,4,5.

I4 I3 I2 I1

A4A3A2A1

Inputs have no effect

Clear

(b) Binary states 0,1,2,3,4,5.

I4 I3 I2 I1

Count = 1

Clear = 1

CP

A4A3A2A1

0 0 1 1

Load

(d) Binary states 3,4,5,6,7,8.

I4 I3 I2 I1

Count = 1

Clear = 1

CP

A4A3A2A1

1 0 1 0

Load

Carry-out

(c) Binary states 10,11,12,13,14,15.

Counter application: Digital Clock


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Counter application: Digital Clock


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17127_digital electronics presentation

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