1.5-v to 7-v, ultra low dropout … · rt rpcl rb 35.00 40.00 45.00 50.00 55.00 60.00 ... (bottom)...

TPS7H1101-SPTPS7H1201-HT

www.ti.com SLVSAS4D –JUNE 2013–REVISED SEPTEMBER 2013

1.5-V to 7-V, ULTRA LOW DROPOUT REGULATORCheck for Samples: TPS7H1101-SP, TPS7H1201-HT

1FEATURES• Current Share/Parallel Operation to Provide • Low Noise

Higher Output Current – TPS7H1201-HT• Wide VIN Range: 1.5 V - 7 V (17 x VOUT) µV RMS• TPS7H1101-SP: – TPS7H1101-SP

(27 x VOUT) µV RMS– Total Dose (TID) Tolerance > 100kRAD(Si)• PSRR: Over 45 dB at 1 kHz– Single Event Latchup (SEL) Immune to

LET = 85MeV-cm2/mg • Load/Line Transient Response– SEB and SERG Immune to • Fold-Back Current Limit (TPS7H1101-SP)

LET = 85MeV-cm2/mg • 16-Pin Ceramic Flatpack Package (HKS/HKR)– SET/SEFI Onset Threshold

is = 40MeV-cm2/mg APPLICATIONS– SET/SEFI Cross-Section Plot, See Radiation • TPS7H1101-SP: Rad Tolerant Applications

Report • RF 5-V Components VCOs, Receivers, ADCs,• Stable With Ceramic Output Capacitor Amplifiers• ±2.0 % Accuracy over Line, Load and • Clock Distribution

Temperature (TPS7H1101-SP) • Clean Analog Supply Requirements• ±4.2 % Accuracy over Line, Load and • Supports Harsh Environment Applications

Temperature (TPS7H1201-HT) • TPS7H1201-HT Available in Extreme• Programmable SoftStart (–55°C to 210°C) Temperature Range• PowerGood Output TPS7H1101-SP Available in Military

(–55°C to 125°C) Temperature Range (1)• Low Dropout Voltage• TPS7H1201-HT: Texas Instruments' high– TPS7H1201-HT

temperature products utilize highly optimized100 mV (MAX) at 0.5 A (210°C)silicon (die) solutions with design and process– TPS7H1101-SPenhancements to maximize performance over75 mV at 1 A (25°C)extended temperatures.210 mV at 3 A (25°C)

• Engineering Evaluation (/EM) Samples are335 mV (MAX) at 3A (125°C)Available (2)

(1) Custom temperature ranges available(2) These units are intended for engineering evaluation only.

They are processed to a non-compliant flow (e.g. No Burn-In,etc.) and are tested to a temperature rating of 25°C only.These units are not suitable for qualification, production,radiation testing or flight use. Parts are not warranted forperformance over the full MIL specified temperature range of -55°C to 125°C or operating life.

DESCRIPTIONThe TPS7H1x01 is a low dropout (LDO) linear regulator that uses a PMOS pass element configuration. Itoperates under wide range of input voltage, from 1.5 V to 7V while offering excellent PSRR. The TPS7H1x01features a precise and programmable fold back current limit implementation with a very wide adjustment range.To support complex power requirements of FPGAs, DSPs, or Microcontrollers the TPS7H1x01 provides enableon/off functionality, programmable SoftStart, current sharing capability, and a PowerGood open drain output. TheTPS7H1x01 is available in a thermally enhanced16-pin ceramic flatpack package (CFP) .

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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VIN

EN

SoftStart

Power

Good

VOUT

FeedBackGND

CIN

CSS

COUT

1.2 V

1.5 VTPS7H1x01

PCL

COMP

CS

Rcs

Rt

Rpcl

Rb

35.00

40.00

45.00

50.00

55.00

60.00

65.00

0 1 2 3 4 5 6

% o

f to

tal L

oa

d

Output Current

LDO1

LDO2

0

50

100

150

200

250

300

350

0 0.5 1 1.5 2 2.5 3

Dro

po

ut

Vo

lta

ge

(m

V)

I (A)OUT

-55 °C

25 °C

125 °C

0

10

20

30

40

50

60

70

80

0.0 0.1 0.2 0.3 0.4 0.5

Dro

pout

Vol

tage

(m

V)

IOUT (A) C001

210 °C

-55 °C

25 °C

125 °C

45.00

46.00

47.00

48.00

49.00

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54.00

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0.2 0.4 0.6 0.8 1

% o

f To

tal

Loa

d

Output Current

LDO1

LDO2

TPS7H1101-SPTPS7H1201-HTSLVSAS4D –JUNE 2013–REVISED SEPTEMBER 2013 www.ti.com

DESCRIPTION (CONTINUED)xxx

VDO vs. IOUT (TPS7H1201-HT) LDO Current Share (TPS7H1201-HT)

VDO vs. IOUT (TPS7H1101-SP) LDO Current Share (TPS7H1101-SP)

TYPICAL APPLICATION CIRCUIT

2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS (1)

over operating temperature range (unless otherwise noted)UNIT

Input voltage range VIN, PG -0.3 to 7.5 VFB, COMP, PCL, CS, EN -0.3 to VIN + 0.3 V

Output voltage range VOUT , SS -0.3 to VIN VPeak output current Internally limited APG pin sink current 5 mAElectrostatic discharge rating (HBM) 2 kVElectrostatic discharge rating (CDM) 1 kVMaximum Operating junction TPS7H1201 -55 to 220

°Ctemperature, TJ TPS7H1101 -55 to 150Storage temperature, TJ TPS7H1201 -65 to 220

°CTPS7H1101 -65 to 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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THERMAL INFORMATION (1) (2)

TPS7H1x01HKS HKR HKR

THERMAL METRIC (3) (HeatSlug_up_no (HeatSlug_down (HeatSlug_down_no UNITSUnderfill) (4) Underfill) (5) (6) Underfill)

16 PINS 16 PINS 16 PINSθJA Junction-to-ambient thermal resistance (7) 75.4 30.7 86.6θJCtop Junction-to-case (top) thermal resistance (8) 0.4 N/A N/AθJB Junction-to-board thermal resistance (9) 4.8 69 59.3ψJT Junction-to-top characterization 1.1 2.4 5 °C/Wparameter (10)

ψJB Junction-to-board characterization 53.5 12.3 63.2parameter (11)

θJCbot Junction-to-case (bottom) thermal N/A 0.6 0.6resistance (12)

(1) Maximum power dissipation may be limited by overcurrent protection.(2) Test board conditions:

(a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch(b) 2 oz. copper traces located on the top of the PCB(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer(d) 48 0.010 inch thermal vias located under the device package

(3) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.(4) Power rating at a specific ambient temperature TA should be determined with a junction temperature below 220°C. This is the point

where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at orbelow 220°C for best performance and long-term reliability.

(5) Power rating at a specific ambient temperature TA should be determined with a junction temperature below 135°C. This is the pointwhere distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at orbelow 230°C for best performance and long-term reliability.

(6) Values listed in the underfill column were derived using properties from a composite, generic silver filled epoxy underfill. They are notproduct specific.

(7) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, asspecified in JESD51-7, in an environment described in JESD51-2a.

(8) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(9) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCBtemperature, as described in JESD51-8.

(10) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extractedfrom the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(11) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extractedfrom the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(12) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specificJEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.Spacer





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TPS7H1201 ELECTRICAL CHARACTERISTICS1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.3 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG pin pulled up to VIN with 50 kΩ, overoperating temperature range (TJ = -55°C to 210°C), unless otherwise noted. Typical values are at TJ = 25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVIN Input voltage range 1.5 7 V

TJ = 125°C 0.593 0.605 0.617 VFeedback pinVFB 1.5 V ≤ VIN ≤ 7 Vvoltage TJ = 210°C 0.580 0.605 0.630 VVIN -VOUT Output voltage range 0.8 V0.2

TJ = 125°C -2 2 %Output voltage IOUT ≤ 0.5 A, 1.5 V ≤ VIN ≤ 7 V, VOUT = 6.8 V (1)accuracy TJ = 210°C -4.2 4.2 %

ΔVOUT%/ Line regulation 1.5 V ≤ VIN ≤ 7 V -0.07 0.01 0.07 %/VΔVIN

ΔVOUT%/ Load regulation 0.8 V ≤ VOUT ≤ 6.8 V, 0 ≤ ILoad ≤ 0.5 A 0.0125 %/AΔIOUT

1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = -55°C (2) 0.5 31.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = 25°C (2) 0.2 0.61.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = 125°C (2) 0.2 11.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = 210°C (2) 0.84 3DC input lineΔVO mVregulation 1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = -55°C (2) 0.5 31.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = 25°C (2) 0.2 0.61.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = 125°C (2) 0.2 11.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = 210°C (2) 0.84 3VOUT = 0.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = -55°C (2) 0.05VOUT = 0.8 V, 0 ≤ILoad ≤ 0.5 A, TJ = 25°C (2) 0.05VOUT = 0.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 125°C (2) 0.07VOUT = 0.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 210°C (2) 0.51DC output loadΔVO mVregulation VOUT = 6.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = -55°C (2) 0.10VOUT = 6.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 25°C (2) 0.04VOUT = 6.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 125°C (2) 0.05VOUT = 6.8 V, 0 ≤ ILoad ≤ 0.5 A, TJ = 210°C (2) 0.47

VDO Dropout voltage IOUT = 0.5 A, VOUT = 6.8 V, VIN = VOUT + 0.1 V 55.5 100 mVProgrammable VIN = 1.5 V, VOUT = 1.2 V, PCL resistance = 47 kΩ 500 700 mA

ICL output current limitVIN = 1.5 V, VOUT = 1.2 V , PCL resistance varies 200 700 mArange

Operating voltageVCS 0.3 VIN Vrange at CSCSR Current sense ratio ILOAD / ICS, VIN = 2.3 V, VOUT = 1.9 V 47394IGND GND pin current VIN = 1.5V, VOUT = 1.2 V, IOUT = 0.5 A 13 20 mA

Quiescent currentIQ VIN = VOUT + 0.5 V, IOUT = 0 A 12 17 mA(no load)ISHDN Shutdown current VEN < 0.5 V, 0.8 V ≤ VIN ≤ 7 V 15 4500 µA

FB/SNS pinISNS, IFB VIN = 7 V, VOUT = 6.8 V 1 10 nAcurrentEN pin inputIEN VIN = 7 V, VEN = 7 V 6.75 610 nAcurrentEN pin input low 0.35 xVILEN V(disable) VIN

EN pin input high 0.75 xVIHEN V(enable) VIN

Enable pinEprop Dly VIN = 2.2 V, EN rise to IOUT rise 650 1000 µspropagation delay

(1) Based upon using 0.1% resistors.(2) Line and load regulations done under pulse condition for T < 10 ms.





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TPS7H1201 ELECTRICAL CHARACTERISTICS (continued)1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.3 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG pin pulled up to VIN with 50 kΩ, overoperating temperature range (TJ = -55°C to 210°C), unless otherwise noted. Typical values are at TJ = 25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITEnable pin turn-on VIN = 2.2 V, VOUT = 1.8 V, ILOAD = 0.5 A, COUT = 220 μF,TEN 1.4 1.6 msdelay CSS = 2 nF

VTHPG PG threshold on No load,VOUT = 1.2 V and VOUT = 6.8 V 84 90 %VTHPGHYS PG hysteresis 1.5 V ≤ VIN ≤ 7 V 2 %VOLPG PG pin output low IPG = -1 mA 73 400 mV

PG pin leakageILKGPG VOUT > VTHPG, VPG = 7 V 0.02 20 µAcurrentISS SS pin current VSS = 1.5 V to 7 V 2.5 6.3 µA

1 kHz 45Power-supplyPSRR VIN = 2.5 V, VOUT = 1.8 V, COUT = 220 μF dBrejection ratio 100 kHz 20Output noise 17 xVN BW = 10 Hz to 100 kHz, IOUT = 250 mA µVRMSvoltage VOUT

Operating junctionTJ -55 210 °Ctemperature





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TPS7H1101 ELECTRICAL CHARACTERISTICS1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.35 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 µF, PG pin pulled up to VIN with 50 kΩ, overoperating temperature range (TJ = -55°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVIN Input voltage range 1.5 7 VVFB Feedback pin voltage 1.5 V ≤ VIN ≤ 7 V 0.594 0.605 0.616 VVOUT Output voltage range 0.8 VIN - 0.35 V

0 A ≤ IOUT ≤ 3 A, 1.5 V ≤ VIN ≤ 7 V,Output voltage accuracy (1) -2 2 %VOUT = 0.8 V, 1.2 V, 1.8 V, 6.65 V (2)

ΔVOUT%/ Line regulation 1.5 V ≤ VIN ≤ 7 V -0.07 0.01 0.07 %/VΔVIN

ΔVOUT%/ Load regulation 0.8 V ≤ VOUT ≤ 6.65 V, 0 ≤ ILoad ≤ 3 A 0.08 %/AΔIOUT

1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, 0.5 3IOUT = 10 mA, TJ = -55°C (3)

1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, 0.2 0.6IOUT = 10 mA, TJ = 25°C (3)


1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, 0.5 3.0IOUT = 10 mA, TJ = -55°C (3)

1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V,ΔVI DC input line regulation 0.2 0.6 mVIOUT = 10 mA, TJ = 25°C (3)


1.5 V ≤ VIN ≤ 7 V, VOUT = 1.8 V, 0.5 3.0IOUT = 10 mA, TJ = -55°C (3)



(1) The output voltage accuracy of condition at IOUT = 2 A and IOUT = 3 A is specified by characterization , but not production tested.(2) Based upon using 0.1% resistors.(3) Line and load regulations done under pulse condition for T < 10 ms.





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PARAMETER TEST CONDITIONS MIN TYP MAX UNITVOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = -55°C (5) 0.4 1.0VOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C (5) 0.6 1.1VOUT = 0.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C (5) 0.8 1.3VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = -55°C (5) 0.8 1.8VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C (5) 1.3 1.8VOUT = 0.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C (5) 1.6 2.4VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = -55°C (5) 1.1 1.9VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C (5) 1.9 2.6VOUT = 0.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C (5) 2.5 3.4VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = -55°C (5) 0.3 1.2VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C (5) 0.5 1.3VOUT = 1.2 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C (5) 0.6 1.3VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = -55°C (5) 0.8 1.6VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C (5) 1.1 2.1VOUT = 1.2 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C (5) 1.5 2.1VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = -55°C (5) 1.0 1.7VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C (5) 1.1 2.4VOUT = 1.2 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C (5) 2.2 3.5

ΔVO DC output load regulation (4) mVVOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = -55°C (5) 0.1 0.9VOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C (5) 0.3 0.9VOUT = 1.8 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C (5) 0.4 1.2VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = -55°C (5) 1.4 2.4VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C (5) 0.7 1.4VOUT = 1.8 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C (5) 0.6 1.9VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = -55°C (5) 2.5 3.9VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C (5) 1.2 2.1VOUT = 1.8 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C (5) 1.2 2.5VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = -55°C (5) 1.5 2.9VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = 25°C (5) 0.4 2.6VOUT = 6.65 V, 0 ≤ ILoad ≤ 1 A, TJ = 125°C (5) 2.8 3.5VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = -55°C (5) 3.5 5.9VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = 25°C (5) 1.1 4.7VOUT = 6.65 V, 0 ≤ ILoad ≤ 2 A, TJ = 125°C (5) 5.8 8.0VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = -55°C (5) 5.6 9.3VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = 25°C (5) 3.7 8.0VOUT = 6.65 V, 0 ≤ ILoad ≤ 3 A, TJ = 125°C (5) 13.0 25

VDO Dropout voltage (4) IOUT = 3 A, VOUT = 1.3 V 210 335 mVVIN = 1.5 V, VOUT = 1.2 V , PCL resistance = 500 750 mA47 kΩProgrammable output currentICL limit range VIN = 1.5 V, VOUT = 1.2 V , PCL resistance 200 3500 (6) mAvaries

Operating voltage range atVCS 0.3 VIN VCSCSR Current sense ratio ILOAD / ICS, VIN = 2.3 V, VOUT = 1.9 V 47394

(4) The parameter is guaranteed to the limit specified by characterization, but not production tested.(5) Line and load regulations done under pulse condition for T < 10 ms.(6) The maximum limit of the ICLparameter is guaranteed to the limit specified by characterization, but not production tested.





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PARAMETER TEST CONDITIONS MIN TYP MAX UNITIGND GND pin current VIN = 1.5 V, VOUT = 1.2 V, IOUT = 2 A 10 16 mAIQ Quiescent current (no load) VIN = VOUT + 0.5 V, IOUT = 0 A 7 10 mAISHDN Shutdown current 1.5 V ≤ VIN ≤ 7 V 26 230 µAISNS, IFB FB/SNS pin current VIN = 7 V, VOUT = 6.65 V 1 5 nAIEN EN pin input current VIN = 7 V, VEN = 7 V, VOUT = 6.65 V 20 150 nAVILEN EN pin input low (disable) 3.5 V < VIN < 7 V 0.35 x VIN VVIHEN EN pin input high (enable) 3.5 V < VIN < 7 V 0.75 x VIN VEprop Dly Enable pin propagation delay VIN = 2.2 V, EN rise to IOUTrise 650 1000 µs

VIN = 2.2 V, VOUT = 1.8 V, ILOAD = 1 A,TEN Enable pin turn-on delay 1.4 1.6 msCOUT = 220 µF, CSS = 2 nFVTHPG PG threshold No load, 0.8 V ≤ VOUT ≤ 6.65 V 86 90 %VTHPGHYS PG hysteresis 1.5 V ≤ VIN ≤ 7 V 2 %VOLPG PG pin output low IPG = -1 mA 120 400 mVILKGPG PG pin leakage current VOUT > VTHPG, VPG = 7 V 0.5 2.5 µAISS SS pin current VSS = 1.5 V to 7 V 2.5 3.5 µA

1 kHz 48VIN = 2.5 V, VOUT = 1.8 V,PSRR Power-supply rejection ratio dBCOUT = 220 µF 100 kHz 25BW = 10 Hz to 100 kHz,VN Output noise voltage 27 x VOUT µVRMSIOUT = 1 A

Thermal shutdownTSD 185 °CtemperatureOperating junctionTJ -55 125 °Ctemperature





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Thermal Pad

(Bottom Side)

SS

EN

VIN

PCL

GND PG/OC

CS

VOUT

VOUT

VOUT

VOUT

COMP

FB1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

VIN

VIN

VIN

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

Thermal Pad

(Top Side)

FB

COMP

VOUT VIN

VOUT

VOUT

VOUT

VIN

VIN

VIN

CS

PG/OC GND

PCL

EN

SS


PIN ASSIGNMENTS

HKS PACKAGE(TOP VIEW)

HKR PACKAGE(TOP VIEW)





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Table 1. PIN FUNCTIONSPIN DESCRIPTION

NAME No.VIN 3, 4, 5, 6 Unregulated supply voltage. It’s recommended to connect an input capacitor as a good analog circuit practice.VOUT 11, 12, 13, 14 Regulated output.FB 16 The output voltage feedback input through voltage dividers. See FEEDBACK CIRCUIT section.GND 8 Ground/Thermal Pad (1)

Enable pin. Driving this pin to logic high enables the device; driving the pin to logic low disable the device. VINEN 2 voltage must be greater than 3.5 V.Current sense pin. Resistor connected from CS to VIN. CS pin indicates voltage proportional to output current.

CS 10 CS pin low: Foldback current limit disabled (Apply for TPS7H1101-SP only)CS pin high: Foldback current limit enabled (Apply for TPS7H1101-SP only)SoftStart pin. Connecting an external capacitor slows down the output voltage ramp rate after enable event.SS 1 See SoftStart section.PowerGood pin. PG is open drain output to indicate the output voltage reaches to 90% of target. PG pin isPG/OC 9 also used as indicator when over current condition is activated.Programmable current limit. A resistor to GND sets the current limit activation point.

PCL 7 The range of resistor that can be used on the PCL pin to GND is 47kΩ to 160 kΩ (TPS7H1201-HT).The range of resistor that can be used on the PCL pin to GND is 8.2 kΩ to 160 kΩ (TPS7H1101-SP).

COMP 15 Output of error amplifier

(1) Thermal Pad must be connected to GND





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CS

CS

OCP PCL

Vin Vout

2mA

Vref

Thermal

Protection

EN

Vref=1.2V

Iss

SS++-

Vfb

Vref/2

Comp

+-

+-

PG

1.1Vfb

0.9Vfb

PMOS

Rt

Rb

Vcs Voltage proportional

to Output current

Rcs

Rpcl

0.6VCss


Figure 1. Functional Block Diagram





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Vout+

+

-

Vref

SS LDO1

CoutRLoad

CSPCL

+

+

-

Vref

SSLDO2

CS PCL

Rt

Rb

FB

FB

Rcl

Css

Comp

Comp

Cout

Ccomp

Ccomp

Rcl

PG

PG

Rpg

Rpg

Rcl

Optional



Figure 2. Functional Block Diagram (Parallel Operation)





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0

500

1,000

1,500

2,000

2,500

3,000

3,500

±75 ±50 ±25 0 25 50 75 100 125 150 175 200 225

Shu

tdow

n C

urre

nt (

uA)

Junction Temperature (�C)

Vin = 7.0V

Vin = 1.5V

C008

VIN = 7.5 V

VIN = 1.5 V

80

85

90

95

100

±75 ±50 ±25 0 25 50 75 100 125 150 175 200 225

PG

Thr

esho

ld (

%)

Junction Temperature (�C) C009

VOUT = 6.8 V

8

10

12

14

16

±55 ±30 ±5 20 45 70 95 120 145 170 195 220

Gro

und

Cur

rent

(m

A)


Load = 0.5 A

No Load

C006

20

40

60

80

±75 ±50 ±25 0 25 50 75 100 125 150 175 200 225

Dro

pout

Vol

tage

(m

V)


Load = 0.5 A

0.600

0.604

0.608

0.612

0.616

0.620

0.624

±55 ±20 15 50 85 120 155 190 225

Fee

dbac

k V

olta

ge (

V)


VIN = 1.5 V

8

10

12

14

16

±75 ±50 ±25 0 25 50 75 100 125 150 175 200 225

Qui

esce

nt C

urre

nt (

mA

)


Vin = 7.0V

Vin = 1.5V

C005

VIN = 7.5 V

VIN = 1.5 V


TYPICAL CHARACTERISTICS (TPS7H1201-HT)Feedback Voltage Quiescent Current

vs. vs.Temperature Temperature

Figure 3. Figure 4.

Ground Current Dropout Voltagevs. vs.

Temperature Temperature

Figure 5. Figure 6.

Shutdown Current PG Thresholdvs. vs.


Figure 7. Figure 8.





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0.0

0.1

0.2

0.3

0.4

±75 ±50 ±25 0 25 50 75 100 125 150 175 200 225

Load

Reg

ulat

ion

(uA

)


Vout = 0.8V

Vout = 6.8

C010

VOUT = 0.8 V

VOUT = 6.8 V

±100

±90

±80

±70

±60

±50

±40

±30

±20

±10

0

10 100 1k 10k 100k 1M

PS

RR

(dB

)

Frequency (Hz) C012

IOUT = 250 mA

±100

±90

±80

±70

±60

±50

±40

±30

±20

±10

0

10 100 1k 10k 100k 1M

PS

RR

(dB

)

Frequency (Hz) C011

IOUT = No Load



TYPICAL CHARACTERISTICS (TPS7H1201-HT) (continued)Power Supply Ripple Rejection Power Supply Ripple Rejection

vs. vs.Frequency Frequency

IOUT = 250 mA IOUT = No Load

Figure 9. Figure 10.

Load Regulationvs.

Temperature Load Transient Response: Step Load 0 A to 250 mA


Expanded View Overshoot Expanded View Undershoot






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0.01

0.1

1

10

10 100 1,000 10,000 100,000

No

ise

(µV

/H

z)√

Frequency (Hz)


TYPICAL CHARACTERISTICS (TPS7H1201-HT) (continued)RMS Noise (10 Hz - 100 kHz) = 20.26 μVrms,

VIN = 2.1 V, VOUT = 1.8 V at Iload = 0.5 A

Figure 15.





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0

20

40

60

80

100

±55 ±35 ±15 5 25 45 65 85 105 125

Shu

tdow

n C

urre

nt (

uA)


VIN = 1.5 V

VIN = 7 V

80

85

90

95

100

±55 ±35 ±15 5 25 45 65 85 105 125

PG

Thr

esho

ld (

%)


VOUT = 6.8 V

120

160

200

240

280

320

-55 -35 -15 5 25 45 65 85 105 125

Dro

po

ut

Vo

ltag

e (

mV

)

Junction Temperature (°C)

Load = 3 A

5

6

7

8

9

10

11

12

13

±55 ±35 ±15 5 25 45 65 85 105 125

Gro

und

Cur

rent

(m

A)


No Load

Load = 2 A

0.602

0.603

0.604

0.605

0.606

0.607

0.608

-55 -35 -15 5 25 45 65 85 105 125

VIN = 1.5 V

VIN = 7 V

Junction Temperature (°C)

Feedback

Voltage

(V)

5

6

7

8

9

10

±55 ±35 ±15 5 25 45 65 85 105 125

Qui

esce

nt C

urre

nt (

mA

)


VIN = 1.5 V

VIN = 7 V



TYPICAL CHARACTERISTICS (TPS7H1101-SP)Feedback Voltage Quiescent Current

vs. vs.Temperature Temperature


Ground Current Dropout Voltagevs. vs.



Shutdown Current PG Thresholdvs. vs.







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0.01

0.1

1

10

10 100 1,000 10,000 100,000

No

ise

(µV

/H

z)√

Frequency (Hz)


TYPICAL CHARACTERISTICS (TPS7H1101-SP) (continued)RMS Noise (10 Hz - 100 kHz) = 20.33 μVrms,

VIN = 2.1 V, VOUT = 1.8 V at Iload = 3 A

Figure 22. Figure 23. Load Transient Response: Step Load 0.1 A to 1.6mA

Figure 24. Expanded View Overshoot Figure 25. Expanded View Undershoot

Figure 26. Turn-Off





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TPS7H1X01 DETAILED DESCRIPTION

TPS7H1101 OverviewThe TPS7H1101 is a low dropout (LDO) linear regulator that uses PMOS pass element configuration. Thisdevice is 3 A (SP version).

It uses TI’s proprietary process to achieve low noise, high PSRR combined with high thermal performance in a16-pin ceramic flatpack package (HKR).

A number of features are incorporated in the design to provide high reliability and system flexibility. Currentfoldback, overload, current limit and thermal protection are incorporated in the design to make it viable for harshenvironments.

A resistor connected from the CS (current sense) pin to VIN indicates voltage proportional to the output current.When CS is held high, foldback current limit is enabled. Shorting CS low will disable the foldback current limit.

A resistor connected from programmable current limit (PCL) pin to ground sets the current limit activation point.When current limit activation point is reached, it results in LDO going into current foldback mode. Output currentis reduced to approximately 50% of the current limit set point.

TPS7H1101 incorporates thermal protection which disables the output when the junction temperature risesapproximately 185°C, allowing the device to cool. Depending on the power dissipation, thermal resistance andambient temperature, the thermal protection wil turn on. Cycling limits the dissipation of the regulator, protectingit from damage as a result of overheating.

The device also has a current sense monitoring feature. A resistor connected from the CS (current sense) pin toVIN indicates voltage proportional to the output load current. Current Sense Ratio (CSR) is the ratio of outputload current to ICS is 47935. A suitable resistor must be chosen to ensure the CS pin is within its operatingrange of 0.3 V to VIN.

In order to provide system flexibility for demanding current needs, the LDO can be configured in paralleloperation as indicated in Figure 2. In parallel configuration, R30 (resistor from PCL to GND) and R23 (resistorfrom CS pin to VIN) must be left open (unpopulated). The RCL value needs to be selected so that the operatingcondition of CS pin is maintained, as specified in the electrical characteristics table. The current from PCLthrough RCL of LDO1 is determined by the output load current of LDO2 divided by the CSR. Hence, the voltageat CS pin of the LDO1 is 0.605 V – ((output load current of LDO2 + 0.2458)/ CSR * RCL). This parallelconfiguration will provide higher reliability (MTBF) for system needs due to reduced stress on the components, asthe load current will be shared between the two LDOs. Alternately, it can also provide twice the output current tomeet system needs. When using two LDOs in parallel operation for higher output load current, use POLTPS50x01 as an input source.

An enable feature is incorporated in the design allowing one to enable or disable the LDO. Power Good, an opendrain connection, indicates the status of the output voltage. These provide the customers system flexibility inmonitoring and controlling the LDO operation. When using Enable function, VIN voltage must be greater than 3.5V.

TPS7H1101 can also be disabled via SS pin. Pulling soft start (SS) pin low to less than 0.3 V will disable theLDO. This can be achieved by connecting an N-channel MOSFET such as 2N7002 from SS pin to Gnd andcontrolling the gate of the MOSFET to disable the LDO.

TPS7H1201 OverviewThe TPS7H1201 is a low dropout (LDO) linear regulator that uses PMOS pass element configuration. Thisdevice is 7 V, 0.5 A.

It uses TI’s proprietary process to achieve low noise, high PSRR combined with high thermal performance in a16-pin ceramic flatpack package (HKS).

A number of features are incorporated in the design to provide high reliability and system flexibility. Overloadprotection is incorporated in the design to make it viable for harsh environments.

A resistor connected from programmable current limit (PCL) pin to ground sets the current limit activation point.When current limit activation point is reached, output voltage drops while output load current is maintained atcurrent limit point.





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V =OUT

( )R + R VTOP BOTTOM REF

·

¾R

BOTTOM


The device also has a current sense monitoring feature. A resistor connected from the CS (current sense) pin toVIN indicates voltage proportional to the output load current. Current Sense Ratio (CSR) is the ratio of outputload current to ICS is 47064. A suitable resistor must be chosen to ensure the CS pin is within its operatingrange of 0.3 V to VIN.

In order to provide system flexibility for demanding current needs, the LDO can be configured in paralleloperation as indicated in Figure 2. In parallel configuration, R30 (resistor from PCL to GND) and R23 (resistorfrom CS pin to VIN) must be left open (unpopulated). The RCL value needs to be selected so that the operatingcondition of CS pin is maintained, as specified in the electrical characteristics table. The current from PCLthrough RCL of LDO1 is determined by the output load current of LDO2 divided by the CSR. Hence, the voltageat CS pin of the LDO1 is 0.605 V – ((output load current of LDO2 + 0.2458)/ CSR * RCL). This parallelconfiguration will provide higher reliability (MTBF) for system needs due to reduced stress on the components, asthe load current will be shared between the two LDOs. Alternately, it can also provide twice the output current tomeet system needs. We shared between the two LDOs. Alternately, it can also provide twice the output currentto meet system needs. When using two LDOs in parallel operation for higher output load current, use POLTPS50x01 as an input source.

An enable feature is incorporated in the design allowing one to enable or disable the LDO. Power Good, an opendrain connection, indicates the status of the output voltage. These provide the customers system flexibility inmonitoring and controlling the LDO operation. When using Enable function, VIN voltage must be greater than 3.5V.

TPS7H1201 can also be disabled via SS pin. Pulling soft start (SS) pin low to less than 0.3 V will disable theLDO. This can be achieved by connecting an N-channel MOSFET such as 2N7002 from SS pin to Gnd andcontrolling the gate of the MOSFET to disable the LDO.

Adjustable Output VoltageThe Output voltage of the TPS7H1101-SP can be set to user programmable level between 0.8 V and 6.65 V.The Output voltage of the TPS7H1201-HT can be set to user programmable level between 0.8 V and 6.8 V.Thiscan be achieved by using a resistor divider connected between VOUT, FB and GND pins. RTOP connectedbetween VOUT and VFEEDBACK and RBOTTOM being connected between VFEEDBACK and GND.

VOUT can be determined by using Equation 1.

(1)

Where VREF = 0.605 V.





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Table 2. Resistor Values for Typical VoltagesVOUT RTOP RBOTTOM

0.8 V 10 kΩ 30.1 kΩ1 V 10 kΩ 15 kΩ

1.2 V 10 kΩ 10 kΩ1.5 V 15 kΩ 10 kΩ1.8 V 20 kΩ 10 kΩ2.5 V 32 kΩ 10.1 kΩ3.3 V 45.9 kΩ 10.2 kΩ4 V 59 kΩ 10.4 kΩ5 V 77.7 kΩ 10.6 kΩ

5.5 V 78.7 kΩ 9.65 kΩ6 V 78.7 kΩ 8.75 kΩ

6.5 V 78.7 kΩ 7.96 kΩ6.6 V 79.6 kΩ 7.96 kΩ6.7 V 78.7 kΩ 7.77 kΩ

Programmable Current Limit (PCL)Programmable current limit resistor, Rpcl, sets the current limit activation point and can be calculated per

Rpcl = 47394 (Vref)/ (PCLcl - 0.0216),

Where Vref = 0.605 V and PCLcl = programmable current limit (A).

For TPS7H1201-HT, the maximum programmable current limit is 700 mA. The range of resistor that can be usedon the PCL pin to GND is 47 kΩ to 160 kΩ.

For TPS7H1101-SP, the maximum programmable current limit is 3.5 A. The range of resistor that can be usedon the PCL pin to GND is 8.2 kΩ to 160 kΩ.

CapacitorsTPS7H1X01 requires the use of a combination of tantalum and ceramic capacitors to achieve good volume tocapacitance ratio. Table 3 highlights some of the capacitors used in the device. It is recommended that properderating guidelines as recommended by capacitor manufacturer be followed based upon output voltage andoperating temperature.

Note polymer based tantalum capacitors must be derated to at least 60% of rated voltage, whereas manganeseoxide (MnO2) based tantalum capacitors should be derated to 33% of rated voltage depending upon theoperating temperature.

The recommended combination of 220-µF tantalum along with 0.1-µF ceramic capacitor be connected betweenVIN to GND and VOUT to GND.

It is important to ensure that good design layout practice be followed to ensure that the traces connecting VIN toGND pins of LDO and VOUT to GND pins of LDO should be kept short to reduce inductance. Trace length shouldbe no longer than 5 cm.

Table 3. TPS7H1x01 CapacitorsCapacitor DetailsCapacitor Part Number Type Vendor(Capacitor, Voltage, ESR)

T525D476M016ATE035 (1) 47 µF, 10 V, 35 mΩ Tantalum - Polymer KemetT525D107M010ATE025 (1) 100 µF, 10 V, 25 mΩ Tantalum - Polymer KemetT541X337M010AH6720 (1) 330 µF, 10 V, 6 mΩ Tantalum - Polymer KemetT525D227M010ATE025 (1) 220 µF, 10 V, 25 mΩ Tantalum - Polymer KemetT495X107K016ATE100 (1) 100 µF, 16 V, 100 mΩ Tantalum - MnO2 Kemet

(1) Operating temperature is -55°C to 125°C.





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Table 3. TPS7H1x01 Capacitors (continued)Capacitor DetailsCapacitor Part Number Type Vendor(Capacitor, Voltage, ESR)

THJE107K016AJH 100 µF, 16 V, 58 mΩ Tantalum AVXTHJE227K010AJH 220 µF, 10 V, 40 mΩ Tantalum AVX

SMX33C336KAN360 33 µF, 25 V Stacked ceramic AVX





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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

5962-1320201VXC PREVIEW CFP HKR 16 1 TBD NIAU N / A for Pkg Type -55 to 125 5962-1320201VXCTPS7H1101-SP

TPS7H1201SHKS ACTIVE CFP HKS 16 1 TBD NIAU N / A for Pkg Type -55 to 210 TPS7H1201SHKS

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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