1370 ieee journal of solid-state circuits, vol. 42, no. …userin low-vt dies and access/write...

1370 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 6, JUNE 2007

Design of a Process Variation Tolerant Self-RepairingSRAM for Yield Enhancement in Nanoscaled CMOS

Saibal Mukhopadhyay, Member, IEEE, Keejong Kim, Hamid Mahmoodi, Member, IEEE, andKaushik Roy, Fellow, IEEE

Abstract—In nanoscaled technologies, increased inter-die andintra-die variations in process parameters can result in largenumber of parametric failures in an SRAM array, thereby, de-grading yield. In this paper, we propose a self-repairing SRAM toreduce parametric failures in memory. In the proposed technique,on-chip monitoring of leakage current and/or delay of a ringoscillator is used to determine the inter-die process corner of anSRAM die. Depending on the inter-die Vt shift, the self-repairsystem selects the proper body bias to reduce parametric failures.Simulations using predictive 70-nm device show that the pro-posed self-repairing SRAM improves design yield by 5%–40%. Atest-chip is designed and fabricated in IBM 0.13- m CMOS tech-nology to successfully demonstrate the operation of the self-repairsystem.

Index Terms—Design, failure, SRAM, variation, yield.

I. INTRODUCTION

DIE-TO-DIE and within-die variations in process parame-ters can result in functional failures (read, write, access,

and hold failures) in SRAM cell (Fig. 1) [1], [2]. The functionalfailures due to parametric variations (hereafter, referred to asparametric failures) degrades memory yield (i.e., the numberof non-faulty chips) [2]. Due to small geometry of the celltransistors, the principal reason for parametric failures is therandom dopant fluctuation induced threshold voltage mis-match between neighboring transistors of a cell (i.e., randomwithin-die or intra-die variations) [1], [2]. On the other hand,die-to-die variation in process parameters (say, Vt) can amplifythe effect of intra-die variations, thereby, increasing the failureprobability of a cell. In particular, low-Vt dies has a higherprobability of read and hold failures while high-Vt dies suffermostly from access and write failures [3]. Hence, a self-re-pairing technique in SRAM that reduces read/hold failuresin low-Vt dies and access/write failures in high-Vt dies canconsiderably improve yield [3]. This can be achieved by usingadaptive repairing technique such as application of adaptivebody bias (ABB) [3]–[6]. Application of reverse body bias

Manuscript received December 12, 2005; revised December 18, 2006. Thiswork was supported in part by Gigascale System Research Center, Semicon-ductor Research Corporation under Contract 1078.001, Intel, and the IBM PhDFellowship Program. Fabrication of the test-chip was supported by the MOSISEducational Program.

S. Mukhopadhyay is with IBM T. J. Watson Research Center, YorktownHeights, NY-10598 (e-mail: [email protected]).

K. Kim and K. Roy are with the Department of Electrical and ComputerEngineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail:[email protected]; [email protected]).

H. Mahmoodi is with the School of Engineering, San Francisco State Univer-sity, San Francisco, CA 94132 USA (e-mail: [email protected]).

Digital Object Identifier 10.1109/JSSC.2007.897161

Fig. 1. SRAM cell storing “0” at node R.

(RBB) in low-Vt dies increases their Vt, thereby reducing pos-sible read/hold failures in SRAM cells. Similarly, applicationof forward body bias (FBB) in high-Vt dies decreases theirVt, which reduces the number of SRAM cells failing due toaccess and write failures [3]. To apply self-repairing techniquesto SRAM, it is necessary to detect the inter-die Vt corner ofa die even under presence of large intra-die variation. In thispaper, we propose a self-repairing SRAM that successfullydetects the inter-die Vt corners by monitoring the leakage ofa memory array or delay of a ring oscillator. Using delay andleakage monitoring, the proposed SRAM apply proper bodybias to reduces the number of parametric failures in a die andimproves memory yield. The proposed design is first designedand simulated using predictive 70-nm technology [7]. Simu-lation results show 5%–40% (depending on the inter-die andintra-die Vt variations) yield improvement for a 256-kB SRAMarray. The proposed self-repairing SRAM is implemented inIBM 0.13- m CMOS technology. Design and measurementof the test-chip successfully demonstrate the operation of theself-repair system.

II. BACKGROUND: PARAMETRIC FAILURES AND

ADAPTIVE REPAIR OF SRAM

Random within-die variation in process parameters (princi-pally, Vt variation due to random dopant fluctuations) results indifferent types of parametric failures in an SRAM cell. The para-metric failures in SRAM are principally due to access (reduction

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MUKHOPADHYAY et al.: PROCESS VARIATION TOLERANT SELF-REPAIRING SRAM FOR YIELD ENHANCEMENT IN NANOSCALED CMOS 1371

Fig. 2. Effect of inter-die Vt shift and body bias on the failure probabilities. (a) Cell failure probability with inter-die Vt shift. (b) Memory failure probability withinter-die Vt shift. (c) Effect of body bias on cell failure.

in the bit-differential produced while accessing the cell), read(data flipping while reading), write (unsuccessful write), andhold (data flipping at a lower supply voltage in standby mode)[2]. An SRAM cell can fail due to any of the above four mecha-nisms. A column of an SRAM array is defined to be faulty if anyof the cells in that column is faulty. An entire SRAM array issaid to be faulty (memory failure) if number of faulty column ismore than the number of redundant column (assuming columnredundancy).

Proper sizing of the cell transistor can reduce the failure (dueto within-die variation) probability of a cell at nominal inter-diecorner [2]. However, the global inter-die variation in processparameter (such as Vt) can amplify the effect of local randomvariation. To understand this, we first applied a certain amountof Vt shift to all the transistors in an SRAM cell (represents aninter-die Vt shift). Next, we apply random intra-die Vt varia-tion to each transistors in the cell and estimate different failureprobabilities using the method proposed in [2]. At low inter-dieVt corner read (lower static noise margin) and hold (highersubthreshold leakage of pull-down transistor) failures are moreprobable at [2]. At high inter-die Vt corners, due to reduction inthe current of the access transistors write and access failures areexpected to high [Fig. 2(a), simulation in predictive 70-nm tech-nology]. Hence, failure probability of a cell and an SRAM arraystrongly depends of the inter-die process variations. At nominalinter-die corner, low cell failure probability (region B), makesmemory failure very unlikely as number of faulty columns ismore likely to be less than that of redundant columns [Fig. 2(b)].If negative (large read/hold failures in region A) and positive(large access/write failures in region C) inter-die Vt shifts in-crease beyond a certain level, memory failure probability be-comes very high [Fig. 2(b)]. Hence, shifting of the dies fromregion A and C to region B (i.e., region B is widened) usingadaptive repair technique improves yield [Fig. 2(b)].

Application of body bias can be used for adaptive repair of thedies [3]. For simplicity, we have assumed application of bodybias only to NMOS devices of an SRAM cell. Forward bodybias reduces Vt of the access transistors thereby reducing ac-cess and write failures for high-Vt dies in region C. On the otherhand, reverse body bias increases Vt of the devices thereby re-ducing read (higher static noise margin) and hold failures (lowersubthreshold leakage) for low-Vt dies in region A [Fig. 2(c)].

Hence, proper body bias can reduce the dominant types of fail-ures in dies in region A and C and shift them to region B. Basedon the above observation, we propose a self-repairing techniquefor SRAM by detecting the inter-die Vt corner of a die and applyproper body bias to reduce number of failures. In this approach,detection and correction of global die-to-die variation are usedto reduce the effect of local variation, thereby improving theyield.

III. LEAKAGE AND DELAY MONITORING FOR DETECTION

OF INTER-DIE VT SHIFT

To determine the correct body bias to apply to the SRAM chipfor yield improvement, the inter-die process corner of a memorychip needs to be determined. The detection of the inter-die Vtcorner (in the presence of large intra-die Vt variation due toRDF) of a die can be achieved by monitoring the leakage of alarge SRAM array (instead of monitoring the leakage of a singletransistor or cell) or delay of a long inverter chain (instead of asingle one). Leakage distribution due to random within-die Vtvariation of a cell from low inter-die Vt corner can overlap withthat of a cell from high inter-die Vt corner [Fig. 3(a)]. How-ever, since leakage of a large SRAM array is the sum of theleakage of all the cells, the leakage distribution of the arrays(due to within-die Vt variation) from different inter-die cornersare well separated [Fig. 3(b)]. This essentially follows from theCentral Limit Theorem [8]. Similarly, for an inverter chain ofsmall length (say, three), the inter-die shift in the delay can bemasked by the intra-die variation [Fig. 4(a)]. However, for a longinverter chain (say, 300) the delay distributions (due to intra-dievariations) are well separated [Fig. 4(b)]. We used the followingcriteria to determine the minimum array size (say, ) re-quired for effective separation (a similar criteria is used to de-termine minimum length of inverter chain:



Fig. 3. Effect of random intra-die Vt variation at different inter-die Vt corners of SRAM. (a) Leakage distribution (due to intra-die variation) of an SRAM cell.(b) Leakage distribution (due to intra-die variation) of the 1-kB SRAM array. (c) Minimum memory size versus intra-die distribution.

Fig. 4. Vt-binning with monitoring the delay of an inverter chain. (a) Three-stage inverter chain. (b) 300-stage inverter chain. (c) Minimum number of stages foreffective separation.

(1)

Fig. 3(c) and Fig. 4(c) show that memory array largerthan 1 kB and inverter chain more than 300 stages long canprovide good separation under reasonable variation. Hence,array leakage and/or delay of long inverter chain area reliableindicator of inter-die Vt corner even under large intra-dievariation [3].

IV. SELF-REPAIRING SRAM

Let us now discuss the implementation of the proposedself-repairing SRAM using leakage/delay monitors and adap-tive body bias. In the proposed scheme, an on-chip processsensor detects the inter-die process corner of the chip and ac-cordingly applies adaptive repair technique (in this case, properbody bias) to fix the parametric failures in that process corner.

A. Self-Repairing SRAM Using Leakage Monitoring

The schematic of a self-repairing SRAM array with leakagesensor is shown in Fig. 5(a). A current sensor circuit moni-tors the leakage of the entire SRAM array and generates an

output voltage (Vout) that is proportional to the leakage value[Fig. 5(b), simulation result for a simple current mirror circuit atpredictive 70-nm technology]. The output of the leakage mon-itor is compared with the reference voltages corresponding tothe different inter-die process corners. Based on the results ofthis comparison, the body bias selection circuit applies the rightbody bias to the SRAM array (Fig. 6). A PMOS switch bypassesthe leakage monitor during normal mode of operation (“con-trolled” by calibrate signal). The output voltage generated bythe leakage monitor is sampled by a set of flip-flops (F/Fs) atthe negative going edge of the “calibrate” signal (which alsoturns “on” the bypass PMOS). If an SRAM die is in the lowinter-die Vt corner, the output of the leakage monitor (Vout) willbe greater than both the reference voltages ( and )and both comparators generate zero, resulting in application ofa reverse body bias (RBB). Similarly, for a die in the high Vtcorner, Vout will be less than both and and FBBwill applied. For dies in the nominal Vt corner, zero body bias(ZBB) will be applied as .

Statistical simulation of the proposed self-repairing is per-formed in HSPICE using predictive 70-nm technology. First,using Monte-Carlo simulation a large number (10 000) ofinter-die Vt shifts are generated for the SRAM array [Fig. 7(a)].The inter-die Vt distribution results in the inter-die distributionsof the memory leakage [Fig. 7(b)], which results in different



Fig. 5. Self-repairing SRAM using ABB. (a) Block diagram of self-repairing scheme. (b) Inter-die Vt shift and current monitor output.

Fig. 6. Body-bias generation circuit for self-repairing SRAM. (a) Body-bias selection logic. (b) Level converters.

Vout voltage for dies in different inter-die corners [Fig. 7(c)].Finally, based on the comparator (a simple comparator circuitfrom [10] is used in this simulation) results in each die, thecorrect body bias is generated [Fig. 7(d)].

In the proposed scheme, the selection of the reference volt-ages is based on the pre-calibration of the memory leakageat different inter-die process corner. Since, intra-die variationshifts the mean of the leakage distribution from its nominalvalue, pre-calibration needs to consider the amount of intra-dievariation [Fig. 8(a)]. Moreover, spread in Vout due to randomintra-die variation needs to be minimized. In our simulationwe observed that the Vout distribution for dies at the differentVt boundaries are well separated [Fig. 8(b) for a 1-kB cachewith Vt boundaries at 80 mV]. The separation increaseswith an increase in the Vt boundaries and/or the memory size.However, variation in Vout, coupled with non-zero offset ofthe comparators, results in a finite probability of misdetectionof the inter-die corner of a die. For example, a die which isactually in region A (or C) can be detected as a nominal Vt dieif due to within-die Vt variation Vout becomes less than(or more than ). Consequently, instead of applying aRBB (or FBB) the self-repair system will apply a ZBB andthe die will not be repaired. Our simulation shows that theprobability of this error is around 7% for a 1-kB SRAM array

Fig. 7. Operation of the self-repair strategy. (a) Inter-die Vt distribution.(b) Inter-die leakage distribution. (c) Distribution of Vout. (d) Generation ofABB. (LVT: low Vt; NVT: nominal Vt; HVT: high Vt.)

even for a large intra-die Vt variation. Increasing the memorysize or the Vt window for region B reduces this probability[3]. On the other hand, dies in region B also can be misdetected



Fig. 8. Effect of intra-die variation on Vout and the selection of reference voltage. (a) Selection of reference voltage with intra-die variation. (b) Variation of Voutdue to intra-die variation at different inter-die process corner.

Fig. 9. Delay monitor based self-repair circuit. (a) Circuit configuration. (b) Statistical operation.

as in region A (or C) resulting in application of RBB (or FBB).This can shift the die to region A (or C) resulting in yield loss.To understand this let us consider the case where a die is innegative-Vt part of ZBB window. As the die shifts towards theregion A, its probability of getting misdetected as a low Vtdie increases. However, for a nominal Vt die close to region Aapplication of RBB is less likely to shift it to region C (since,region B window is reasonably large). It is easier for the diescloser to the zero Vt point (i.e., middle of the region B) to beshifted to LVT region due to incorrect application of FBB.However, the dies near the middle of region B less likely to bemisdetected. Hence, the possibility of yield loss due to transferof dies from region B to A or C is very low, which is alsoverified from simulations (assuming large intra-die variationand 50 mV comparator offset). It is evident that increasingarray size and Vt boundaries will reduce this error further.

B. Self-Repairing SRAM Using Delay Monitoring

Fig. 9 shows the delay monitor (a 600-stage-long inverterchain) based self-repair circuit. Since the delay of a 600-stage

ring oscillator is significantly higher than the clock period, wecan use the clock and a counter-based detection technique. Thecounter is first initialized to zero state and at the rising edgeof the “calibrate” signal (which needs to be synchronized withthe rising edge of the clock) counting begins. The counter isdisabled at the rising edge of the signal from the output of thefinal inverter. The total delay of the path is determined by thestate of the counter. Finally, the final state of the counter iscompared with pre-calibrated state values representing low-Vtand high-Vt corners (similar to and ) and properbody bias is applied. Monte Carlo simulation is performed usingpredictive 70-nm technology to verify the proposed technique.The inter-die Vt distribution gets converted to the distributionof the final state of the counter [Fig. 9(b)]. The digital com-parator successfully compares the final counter state with ref-erence states and proper body bias is generated. Since the delayis measured in the quanta of the clock cycle, the number ofstages should be large enough to minimize the quantization error(the error can be further minimized using dual-edge triggeredcounters [11]).



Fig. 10. Parametric failures in self-repairing SRAM. (a) Reduction in number of failures in 256-kB memory array using self-repairing SRAM. (b) Yield enhance-ment using self-repairing SRAM.

Fig. 11. Implementation of the proposed self-repairing SRAM. (a) Die photo of the self-repairing SRAM test-chip (technology: 0.13-�m, dual-Vt triple-welltechnology, die size: 16mm , I/O pin: 84, number of transistors:�7 million). (b) Full-chip layout. (c) 16-kB SRAM block layout. (d) Tester circuit layout.

The delay monitor based design eliminates the analog com-ponents (such as current mirror and comparators). The spread inthe output state distribution and the shift in its mean value due tointra-die variation is very low in the delay monitor scheme. Thisnot only minimizes the misprediction errors, but also eliminatesthe need to consider the amount of random variation duringpre-calibration of reference states. Moreover, the delay monitordoes not require the additional bypass PMOS. However, the pri-mary drawback of the delay monitor is that linear dependence ofdelay on Vt reduces the difference between the output states forinverter chains shifted to different inter-die process corners (thedifference in leakage is much higher due to exponential depen-dence of leakage to Vt). The complexity and area overhead ofthe delay monitor circuit (ring oscillator, counter, and the com-parator logic) are also higher compared to the leakage monitorsystem. We would like to mention that the proposed ABB basedyield enhancement technique can also be implemented usingoff-chip selection and application (using programmable fuses)of body bias voltages.

C. Simulation Result for Yield Enhancement

The proposed self-repairing SRAM is applied for 64-kB and256-kB array designed using BPTM 70-nm technology andsimulated in SPICE. The size of the transistors in the SRAMcell is first optimized to minimize the cell failure probabilityat Vt mV (at zero body bias). It is observed thatthe proposed scheme reduces number of failures in low-Vtand high-Vt inter-die corners, which widens the low memoryfailure region resulting in better yield (Fig. 10). The applicationof the self-repair technique results in 5%–40% improvement inyield over the SRAM array with no body bias (Fig. 10). Theeffectiveness of the technique improves with an increase in theintra-die and inter-die variations.

V. DESIGN OF THE TEST-CHIP AND MEASUREMENT RESULTS

The proposed self-repair SRAM is designed and fabricated inIBM 0.13- m CMOS technology. Fig. 11 shows the die photoand layout of the fabricated chip. The dual-Vt option available



Fig. 12. Measurement results for a single isolated cell designed in 0.13-�mCMOS technology.

in the technology is used to emulate inter-die process variations.Two 64-kB SRAMs are implemented, one using low-Vt (repre-sents extreme negative Vt shift) and one with high-Vt (repre-sents extreme positive Vt shift) devices. In the test-chip, we im-plemented the leakage monitor based self-repairing system withon-chip body bias generators.

A. Organization of the Test-Chip

The complete design has two 64-kB array. Each of the arraysis divided in four blocks of 16 kB [Fig. 11(b)]. Each 16-kB blockcontains four blocks of 4-kB array (256 rows 128 columns)with column circuits (i.e., column decoder, read/write multi-plexers, pre-charge circuit, and sense amplifiers) and row drivers(essentially a 256 bit shifter). Each 16-kB block also contains atester circuit (explained in detail later) to test different types offailures [Fig. 11(b) and (c)]. The bypass PMOSes are designedso that they do not come in series with the pre-charge circuit (toreduce pre-charge delay overhead). It should be noted that theread delay is determined by the discharging current through theseries connected access and pull-down NMOS devices. Hence,the bypass PMOS does not introduce additional delay penalty.The area overhead associated with the implementation of by-pass PMOS transistors is approximately 5%.

B. Failure Measurements Results

Fig. 12 shows the measured results for read margin (the dif-ference between read voltage and trip point), write margin (themaximum bit-line voltage with which a “0” can written to thenode storing “1”), read current, and hold voltage (the minimumcell voltage to which data can be held) from a single SRAM cell.It can be observed that FBB degrades read margin (higher readfailure), and increases hold voltage (higher hold failure). On theother hand, RBB reduces read current (higher access failure) andwrite margin (higher write failure). It is interesting to note thatwith RBB, hold voltage increases marginally. However, sinceRBB reduces the leakage spread significantly, it will reduce thespread in the hold voltage, thereby reducing hold failures.

Fig. 13 shows the measured values of a number of differenttypes of failures from low-Vt and the high-Vt array. The on-chip

Fig. 13. Failure measurement results for 64-kB low-Vt and high-Vt array fabri-cated in 0.13-�m CMOS technology. (a) Read failures. (b) Hold failures. (c) Bit-differential (access test). (d) Write failures. High-Vt array shows lower read andhold failures. Low-Vt array shows higher bit-differential (lower access failure,and lower write failures.

Fig. 14. Failure measurement results for 64-kB array with adaptive body biasfabricated in 0.13-�m CMOS technology. (a) RBB reduces read failures inlow-Vt array. (b) RBB reduces hold failures in low-Vt array. (c) FBB increasesbit-differential (lower access failures) in high-Vt array. (d) FBB reduces writefailures in high-Vt array.

failure measurement system described later is used for the mea-surement. First, we modified the measurement conditions to in-crease the number of failures to a statistical significant number.Next, using that condition we studied the effect of Vt shifts andbody bias.

A reduction in the cell supply voltage increases the readfailure for both high-Vt and low-Vt array. However, read failurefor the high-Vt array is lower than the low-Vt array [Fig. 13(a)].



Fig. 15. Proposed leakage sensor and its operation. (a) Conventional design using diode connected load. (b) Proposed leakage sensor. (c) BIAS generation circuitfor the proposed leakage sensor. (d) Sensor output with temperature and Vt change. (e) Effect of intra-die variation on sensor output (simulation result in IBM0.13-�m technology).

Fig. 13(b) shows that at different hold voltages, the hold-fail-ures are more for low-Vt array compared to the high-Vt array.To measure access failure, we measured the bit-differentialat the time of sense-amplifier firing. It can be observed that acell from the high-Vt array has lower bit-differential comparedto the corresponding cell from the low-Vt array [Fig. 13(c)].This indicates that access failure will be more in the high-Vtarray. We performed a weak write test to measure write fail-ures. Fig. 13(d) shows the write failure for the high-Vt andlow-Vt array with different voltages for the low bit-line (i.e.,weak write test ground). High-Vt array showed higher numberof write failures. Hence, the measurement results show thatdifferent types of parametric failures are amplified at differentinter-die Vt corner.

Fig. 14 shows the measurement result which shows the effectof proposed self-repair technique on different cell failures.Based on the proposed scheme, RBB is applied to the low-Vtarray, which reduces the read and hold failures for that array.On the other hand, FBB is applied to the high-Vt array, whichresults in higher bit-differential (lower access failure) and lowerwrite failure for that array [Fig. 14(c) and (d)]. The failuremeasurement results validate the effectiveness of the proposedscheme in repairing SRAM array and improving design yield.

Fig. 16. Measured current sensor output attached to the 64-kB LVT array.

C. Design of the Self-Repair System

The self-repair system consists of the leakage sensor, refer-ence voltages, and body bias selection logic. Let us now discussthe implementation of these components.



Fig. 17. Reference generator circuit. (a) Circuit schematic. (b) Effect of temperature and inter-die Vt shift (simulation result in 0.13-�m CMOS). (c) Measuredreference voltage change in supply voltage.

1) Current Sensor Circuit: The current sensing circuit is es-sentially a current mirror with an active NMOS load (Fig. 15,designed using large devices to reduce RDF effect). The cur-rent sensor is designed to have Vout 1.4 V for low-Vt array(RBB signal is generated) and Vout 0 V for high-Vt array(FBB signal is generated). The diode in the current mirror cir-cuit is designed to be large and distributed in different parts ofthe array (four diodes are used for each of the 4-kB array withless than 0.01% area overhead) to reduce the effect of within-dierandom and spatial variability.

The leakage sensor output (Vout) in the proposed schemeneeds to have low sensitivity to 1) inter-die Vt shift in thesensor transistors, and 2) change in temperature (T). With adiode-connected NMOS load [Fig. 15(a)] positive inter-die Vtshift of the diode at the high-Vt corner increases Vout. Thisreduces the difference in Vout between low and high-Vt cor-ners [“Conv. Design” in Fig. 15(a)]. Also, due to exponentialdependence of array leakage on T, Vout for a high-Vt die athigh T can be comparable to that of a low-Vt die at low-T(Fig. 15). To solve this problem we used active NMOS loadwith variable bias [Fig. 15(b)]. The bias generator circuit is de-signed such that the bias increases with T and inter-die Vt shiftof sensor transistors (with , and in Fig. 15(c),

Vt ). This reduces the resis-tance of the NMOS load at higher T (lower sensitivity of Voutto T) and higher inter-die Vt (compensates the Vt increase ofNMOS load). The transistors M1–M9 are designed to ensure alarger current through at the low-Vt cornercompared to the high-Vt corner. This increases at afaster rate with T for low-Vt cases to compensate the highertemperature sensitivity of the array leakage at the low-Vt corner.Simulations in 0.13- m technology show that the proposedsensor reduces the output sensitivity to temperature, inter-dieand intra-die Vt variation of sensor transistors (Fig. 15). Theleakage sensor is designed to have Vout 1.4 V for low-Vtarray and Vout 0 V for high-Vt array 1.5 V .Measured value of Vout from the sensor monitoring the low-Vtarray leakage is close to 1.4 V (within 5% of the simulatedvalue) (Fig. 16, array leakage is modified using source-bias). Torepresent equal inter-die Vt shift, the array and the sensor are

Fig. 18. Measured sensor output and reference voltage for the low-Vt array fordifferent dies.

designed with same types of devices (i.e., the sensor for low-Vtarray is designed with low-Vt devices). As “Calibrate” switchesfrom “high” to “low” during regular operation, the supply ofthe sensor is gated to minimize its static power dissipation.

2) Reference Generator Circuit: The on-chip reference volt-ages (0.5 V and 1 V) are designed to have a small positive tem-perature coefficient (similar to Vout, realized using NMOSand ) and low sensitivity to inter-die Vt shift (Fig. 17).Simulation of the proposed design in IBM 0.13- m technologyshows the small positive temperature coefficient of the refer-ence voltage and its weak sensitivity to the inter-die Vt shift[simulation for the circuits designed using low-Vt and high-Vtdevices, Fig. 17(b)]. Measured values of the reference voltageshow low sensitivity to supply variation and low chip-to-chipvariation [Fig. 17(c)].

3) Body-Bias Generation and Application: Measurementresults show that the proposed self-repair system can generateproper body bias generation signal based on the obtained sensoroutput and reference voltages. For example, measurement re-sults from different chips show that the sensor output fromlow-Vt array is higher than the reference voltages (Fig. 18).Hence, monitoring the low-Vt array leakage and comparing it



Fig. 19. Measured body bias voltage for different chips. (a) Measured value of body bias at different supply voltage. (b) Measured value of body bias obtainedfrom different dies.

Fig. 20. Application of body bias. (a) Reverse bias with external bias. (b) Reverse bias with internal bias (longer transition time).

with the reference voltages (we implemented a sense-amplifier[13] based comparator to minimize the offset voltage) willgenerate signal for application of reverse body bias. Let us nowconsider the design of the multiplexer logic shown in Fig. 6.Let us assume that the FBB generation signal is high (i.e.,the die is in high-Vt corner) and RBB generation signal (i.e.,selection signal for the top pass-transistors) is low. It should benoted that if a negative RBB voltage is applied at the sourceof the pass transistors even if the gate of the NMOS is 0 V,Vgs of the NMOS is . Since the magnitude of RBB isexpected to be larger than Vt of the NMOS, it will weakly turnon the NMOS. Therefore, even if only FBB generation signalis “high”, the pass transistor corresponding to RBB will alsobe weakly “on”. This will reduce the final body voltage fromthe applied FBB. To solve this problem, we use a simple levelconverter circuit which changes all logic “0” values from 0 V tothe value of applied RBB (Fig. 6). This ensures the NMOS inpass transistor corresponding to RBB selection remains “off”if RBB selection signal is low.

To show the feasibility of the complete on-chip system, wealso implemented FBB and RBB generators. To reduce the sub-strate noise originating from the high activity column (includingread/write circuits and sense-amplifiers) and row driver circuits,they were designed in isolated p-well (using the triple-well op-tion) and the array was placed in substrate [6]. Since in the pro-posed design body bias is applied statically and the high-activity

circuits are placed in triple-well, the fluctuation in the body cur-rent is low, which simplifies the on-chip design of the body biasgenerators. Also, the nature of the memory-failure probabilitycurve shown in Fig. 2(b) suggests that a large body bias (upperbounded by maximum tolerable leakage values) can be usedsince the probability of shifting a die from region A to C (orvice versa) is low (as region B is reasonably wide) [3]. More-over, the sharp transition of Vt curve at theregion boundary also suggests that a small change in the Vt isrequired to shift a large number of dies from region A and C toregion B [3].

From the above observations, we can conclude that the sta-bility requirement of the applied body bias is less severe andonly two levels (one positive and one negative) of body biascan give significant yield improvement (a continuous value ofoutput bias is not required from the bias generators). The lowstability requirement of the body voltage allowed us to designthe bias generators using a reference circuit followed by anoperational amplifier [6]. Measured FBB ( 0.5 V) and RBB( 0.5 V) values from the designed on-chip bias generators showgood stability against supply variation (Fig. 19). The measuredbody bias values from different dies are also close to each other(Fig. 19).

Measurement body voltage transition waveforms in Fig. 20(for RBB application; FBB application also shows similar wave-form) shows successful application of proper body bias based



Fig. 21. Built-in test circuit for failure measurement. (a) Schematic of the tester. (b) Schematic of the starter block. (c) Simulation waveform of the tester operations(in 0.13-�m CMOS technology).

on the comparator output using both off-chip and on-chip biasgenerators. It can be observed that the body voltage transitiontime is longer for the on-chip bias generator. The transitiontime for the on-chip generator can be reduced by increasing thedrivability of the bias generator at the expense of higher powerdissipation.

D. Testing Scheme for Failure Measurement

To measure the different types of failures in the proposedSRAM array, on-chip variable frequency oscillators and built-intest circuits are designed. The variable frequency on-chip oscil-lator is designed based on the circuit proposed in [14] and im-plemented for clock generation.

To measure the different types of failures in the proposedSRAM array, built-in test circuits are designed as shown inFig. 11(d) and 21(a). The heart of the proposed circuit isSTARTER [Fig. 21(b)]. Depending on the input signals Reset,Feed, and Clock, this block either simultaneously turns “on”all the word-lines (which ensures a stable write to the cells) orturns “on” one word-line at a time (for normal operation). When

all the word-lines are turned “on” simultaneouslyand enough time is given to ensure a proper write operation.This step essentially initializes all the cells in the array. In thenext step, Reset is set to zero and the negative edge of Resetgenerates a Start pulse with a pulse width equal to that of theClock (generated using an on-chip/off-chip clock). This pulsepropagates through the row driver circuit (which is essentially a

256-bit shifter) to turn “on” one word-line at a time. This pulsealso resets the counter and flag generation circuit [Fig. 21(a)].At each clock cycle (i.e., when the word-line is “on” due to thestart pulse) the cell in the selected row and column is read andoutput of the sense-amplifier is compared against the writtendata (Write-In) (using an XOR circuit). If the read data is dif-ferent from the written data, the XOR circuit generates a pulseindicating a failure. This sets the output of the flag generationcircuit to “high” and advances the state of the counter. After thestart pulse exits from the shifter (i.e., a pulse appears at Srout)the counter is disabled and the counter state is latched. The datastored in the latch indicates the total number of failures whileFlag indicates whether at least one failure exists. Fig. 21(c)shows the simulation waveform for the tester operation in IBM0.13- m technology. Fig. 22 shows measured waveforms ofReset, Start, Srout, Flag, and Tout during a read failure testing.The Start pulse is generated as soon as Reset goes to “0”.Fig. 22(b) shows the Srout signal and generation of the Tout(output of the counter). In this particular case, change of Toutfrom “0” to “1” indicates that a failure has been registeredin the counter. Initialization of the cells is performed at verylow frequency to ensure proper write operation. The followingread/write operations are performed at the desired speed.For read failure testing, two consecutive reads are performed(second read is performed at low speed to avoid access failure).To test for hold failure, after the initialization (i.e., the slowwrite), the supply voltage of the array is reduced to the desiredhold voltage. After a sufficient time, the voltage is increased



Fig. 22. Measured waveforms of the SRAM with built-in tester. (a) Start andReset. (b) Srout and Tout.

back to the operational level and a slow (to avoid access failure)reading is performed to test for hold failures.

To predict access failure the bit-differential is measured usinga specialized test circuit. It consists of an additional sense-am-plifier which is directly operated using the complement of theword-line signal. After the word-line is turned “off”, the senseamplifier becomes enabled and the voltage of the discharged bit-line is compared against an external reference voltage .If the voltage of the discharged bit-line is less than , theOUT is high. On the contrary, if the voltage bit-line is higherthan , then the OUT goes low. For a given clock frequency,by finding out the reference voltage at which the OUTis changing, we can measure the bit-differential at the time ofsense-amplifier firing.

VI. CONCLUSION

In this paper, we proposed a self-repairing SRAM usingon-chip current and delay monitoring technique. In the pro-posed SRAM array, array leakage and/or delay of an inverterchain are monitored and used to separate different SRAMdies in appropriate inter-die Vt corners. Adaptive body bias isapplied to the dies in the different Vt corners, resulting in asignificant reduction in failures. The self-repairing SRAM withleakage monitors was designed and implemented in 0.13- mCMOS technology. Measurement of the test-chip successfullydemonstrated the operation of the self-repair system. Sinceparametric failures in SRAMs are becoming an increasingproblem, the proposed self-repairing SRAM can be very effec-tive in achieving high yield in nanometer technologies.

ACKNOWLEDGMENT

Thanks go to Dr. A. Datta, K. Kang, and D. Park, PurdueUniversity, for helpful discussions and help with the design.

REFERENCES

[1] A. Bhavnagarwala et al., “The impact of intrinsic device fluctuationson CMOS SRAM cell stability,” IEEE J. Solid-State Circuits, vol. 36,no. 4, pp. 658–665, Apr. 2001.

[2] S. Mukhopadhyay et al., “Modeling of failure probability and statisticaldesign of SRAM array for yield enhancement in nanoscaled CMOS,”IEEE Trans. Comput.-Aided Des., vol. 24, no. 12, pp. 1859–1880, Dec.2005.

[3] S. Mukhopadhyay et al., “Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring,” in Int. TestConf. (ITC2005).

[4] J. W. Tschanz et al., “Adaptive body bias for reducing impacts ofdie-to-die and within-die parameter variations on microprocessorfrequency and leakage,” IEEE J. Solid-State Circuits, vol. 37, no. 11,pp. 1396–1402, Nov. 2002.

[5] J. T. Kao et al., “A 175-MV multiply-accumulate unit using an adap-tive supply voltage and body bias architecture,” IEEE J. Solid-StateCircuits, vol. 37, no. 11, pp. 1545–1554, Nov. 2002.

[6] K. Itoh, VLSI Memory Chip. New York: Springer, 2001.[7] BPTM 70 nm: Berkley Predictive Technology Model. [Online]. Avail-

able: http://device.eecs.berkeley.edu/~ptm/[8] A. Papoulis, Probability, Random Variables and Stochastic Process.

New York: McGraw-Hill, 2002.[9] R. Rao et al., “Parametric yield estimation considering leakage vari-

ability,” in Proc. DAC 2004, Jun. 2004, pp. 442–447.[10] ecircuitcenter. [Online]. Available: http://ecircuitcenter.com/Op-

Models/V_Limit/[11] H. Mahmoodi et al., “Dual-edge triggered level converting flip-flops,”

in Proc. ISCAS 2004, vol. 2, pp. II-661–II-664.[12] C. H. Kim et al., “On-die CMOS leakage current sensor for measuring

process variation in sub-90 nm generations,” in Symp. VLSI Circuits2004, pp. 250–251.

[13] B. Wicht et al., “Yield and speed optimization of a latch type voltagesense amplifier,” IEEE J. Solid-State Circuits, vol. 39, pp. 1148–1158,Jul. 2004.

[14] H. R. Lee et al., “A fully integrated 0.13-/spl mu/m CMOS 10 Gb Eth-ernet transceiver with XAUI interface,” in IEEE ISSCC 2004 Dig. Tech.Papers.

Saibal Mukhopadhyay (S’99–M’07) received theB.E. degree in electronics and telecommunicationengineering from Jadavpur University, Calcutta,India, in 2000, and the Ph.D. degree in electrical andcomputer engineering from Purdue University, WestLafayette, IN, in 2006.

He is currently a Research Staff Member atthe IBM T. J. Watson Research Center, YorktownHeights, NY. His research interests include analysisand design of low-power and robust circuits innanometer technologies.

Dr. Mukhopadhyay received the IBM PhD Fellowship award for 2004–2005.He received the SRC Technical Excellence Award in 2005, the Best in Sessionaward at 2005 SRC TECNCON, Best Paper Awards at 2003 IEEE Nano and2004 International Conference on Computer Design.

Keejong Kim received the M.S. and Ph.D. degreesin electronic and electrical engineering from PohangUniversity of Science and Technology (POSTECH)in 1992 and 1997, respectively.

He worked at LG-Philips LCD during 1997–2004in TFT-LCD and AMOLED driver circuit designfor portable applications. Since 2004, he has beena Postdoctoral Research Engineer in the Schoolof Electrical and Computer Engineering at PurdueUniversity, West Lafayette, IN. His research interestsinclude low-power and robust VLSI circuit design

(logic and memory).



Hamid Mahmoodi (S’00–M’06) received the B.S.degree in electrical engineering from the Iran Uni-versity of Science and Technology, Tehran, Iran, in1998, and the M.S. degree in electrical and computerengineering from the University of Tehran, Iran, in2000. He received the Ph.D. degree in electrical andcomputer engineering from Purdue University, WestLafayette, IN, in 2005.

He is currently an Assistant Professor of elec-trical and computer engineering in the School ofEngineering at San Francisco State University. His

research interests include design of low-power, robust, and high-performancecircuits and architectures for nanoscale technologies. He has more than 50publications in journals and conferences and 5 patents pending.

Dr. Mahmoodi was a recipient of the Best Paper Award of the 2004 Interna-tional Conference on Computer Design and the 2006 IEEE Circuits and SystemsSociety VLSI Transactions Best Paper Award.

Kaushik Roy (SM’95–F’01) received the B.Tech.degree in electronics and electrical communicationsengineering from the Indian Institute of Technology,Kharagpur, India, and the Ph.D. degree in electricaland computer engineering from the University ofIllinois at Urbana-Champaign in 1990.

He was with the Semiconductor Process andDesign Center of Texas Instruments, Dallas, wherehe worked on FPGA architecture development andlow-power circuit design. He joined the Electricaland Computer Engineering Faculty at Purdue Uni-

versity, West Lafayette, IN, in 1993, where he is currently a Professor andholds the Roscoe H. George Chair of Electrical and Computer Engineering.He is Purdue University Faculty Scholar. He is the Chief Technical Advisor ofZenasis Inc. and Research Visionary Board Member of Motorola Labs (2002).His research interests include VLSI design/CAD for nanoscale silicon andnon-silicon technologies, low-power electronics for portable computing andwireless communications, VLSI testing and verification, and reconfigurablecomputing. He has published more than 400 papers in refereed journals andconferences, holds 8 patents, and is co-author of two books on low powerCMOS VLSI design.

Dr. Roy received the National Science Foundation Career DevelopmentAward in 1995, the IBM faculty partnership award, the ATT/Lucent Foundationaward, 2005 SRC Technical Excellence Award, SRC Inventors Award, and bestpaper awards at 1997 International Test Conference, IEEE 2000 InternationalSymposium on Quality of IC Design, 2003 IEEE Latin American Test Work-shop, 2003 IEEE Nano, 2004 IEEE International Conference on ComputerDesign, 2006 IEEE/ACM International Symposium on Low Power Electronicsand Design, and 2005 IEEE Circuits and Systems Society Outstanding YoungAuthor Award (Chris Kim), 2006 IEEE TRANSACTIONS ON VLSI SYSTEMS BestPaper Award. He has been on the editorial board of IEEE DESIGN AND TEST,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS

ON VLSI SYSTEMS. He was Guest Editor for the Special Issue on Low-PowerVLSI in the IEEE DESIGN AND TEST (1994) and IEEE TRANSACTIONS ON

VLSI SYSTEMS (June 2000), and IEE Proceedings—Computers and DigitalTechniques (July 2002).


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