Semester design review A TEST VEHICLE FOR RESEARCH ON THERMAL MANAGEMENT FOR INTEGRATED CIRCUITSKarl Peterson , Emmanuel Owusu, and Joshua Ellis

12/8/2009Iowa State UniversityEE491 - Senior Design I

Our project is special…

International collaboration

Product conceptualization & specification in addition to design

Integrated circuit (IC) rather than system design

Research-orientated objectives

Problem Statement

Design an integrated circuit (IC) for testing activities related to Iowa State University research activities in the area of thermal measurement and management for high-performance chips

Research in this area is being conducted by Dr. Randy Geiger and Dr. Degang Chen and members of their research group

Problem Statement

Experimental activities related to this research have not been specifically planned

Part of our job has been to anticipate the type of tests for which the IC might be used

Flexibility and configurability are key features of the solution we have proposed

In preparation for the design, we imagined possible tests scenarios in detail and discussed them with the research team

Types of IC testing activities

1. Evaluation of existing or novel analog temperature sensing circuits

2. Study of failure mechanisms affecting the long-term reliability of high-performance chips

3. Development of dynamic thermal management strategies taking advantage of the products of items (1) and (2)

Solution approach

Flexibility can be achieved by realizing complex testing functionality on a programmable external controller

The IC itself allows test measurements to be taken and experimental conditions to be set while the controller manages these operations according to the specific test being conducted

Top-level block diagram

Analog test unit - subcircuits

Digital functionality

Design approach

‘Divide-and-conquer’ Top-down design

methodology Levels of design

Behavioral (Verilog, Verilog-A) Transistor level (schematic) Layout (mask description)

All descriptions (and documentation) are organized in Cadence design environment

Shared library

Schedule

Based around January 20th submission deadline for MOSIS educational program

Very aggressive!

Resources

Design & fabrication are separated in modern integrated circuit operations

Design itself is really a software task, resources include: Software tools (Cadence front-to-back

tool-set, ModelSim, etc.) Engineering labor

Resources - labour

Team Member

Hours Hourly Rate Total Cost

Emmanuel 600 $30 $18,000

Josh 400 $30 $12,000

Karl 600 $30 $18,000

TOTAL $48,000

Table 7 - Labor costs for team members (September 2009 - April 2010)

Risks & risk mitigation

Aggressive schedule, tight deadline Risk of not meeting deadline In this case, our product cannot be used

for research or its use may be delayed Near-impossibility of modification

after fabrication Statistical variations in the fabrication

process Oversights in verification

Thank you!

Any questions? Details about sub-blocks?

BACKUP SLIDES

CMOS Temperature sensors Research centers

around compact, low power designs

Most temperature sensors in this category are based off of a view basic architectures

Many details of their performance and operation on not well understood!

VDD

VO1(T)

VO2(T)

M1 M2

M3

M5 M4

V3

ADC – Sigma-delta modulator

Test interconnect

Maximum current-density section(also uniform current density and linear)

Current DAC – Basic architecture

(to test interconnect)

D<0> D<1> D<2> D<3> ...D<7>

(W/L) 2(W/L) 4(W/L) 8(W/L)