Disciplina: ELD0001 Lista de exercícios 2 Joinville, 16 de março de 2016

Curso de engenharia elétricaProfessor Renan Sebem

Aluno(s):

Exercícios1. Dados 2 decodificadores de 4 saídas habilitadas em “1” e pino de Chip Select ativo em “0”, implemente um

decodificador de 8 saídas com a lógica (portas) extra necessária.

2. Dados 5 decodificadores de 4 saídas habilitadas em “0” e pino de Chip Select ativo em “0”, implemente umdecodificador de 16 saídas. Será necessária alguma lógica extra? Qual? Por que?

3. Implemente a função F(C,B,A) =∑

m (0,2,4,6,7) utilizando um decodificador de 8 saídas ativas em “1”.

4. Implemente a função F(D,C,B,A) =∑

m (1,2,3,5,6,8,10,12,15) utilizando um decodificador de 16 saídasativas em “0”.

5. Implemente a função F(D,C,B,A) = DCB + DCA + BA utilizando um decodificador de 16 saídas ativasem “0”.

6. Projetar um decodificador de display de 7 segmentos com saídas ativas em 1 que escreva sequencialmenteas letras “ELd_” neste display. Utilizar 2 variáveis de seleção B e A. O display é do tipo cátodo comum.

7. Descreva brevemente como o somador da Figura 1 funciona. Por que ele é mais compacto que outrossomadores multi-bit? Por que ele é mais lento que os outros?

Implementation examples for both expressions are depicted in Figure 12.2. In Figure 12.2(a), the sum is computed by a conventional XOR gate and the carry-out bit is computed by conventional NAND gates. In Figure 12.2(b), a more effi cient (transistor-level) CMOS design is shown, where the computation of the sum and carry-out are combined (that is, the computation of s takes advantage of computations that are necessary for cout, which reguires 28 transistors. In Figure 12.2(c), a mux-based full-adder is shown, which requires 18 transistors if the multiplexers are implemented with TGs (Figure 11.16(b)) or just 8 transistors (at the expense of speed) if implemented with PTs (Figure 11.16(c)).

12.2.2 Carry-Ripple AdderFundamental concepts related to addition and subtraction were studied in Sections 3.1–3.2. Figure 12.3(a) illustrates the operation of a multibit adder. The values in the gray area are given, while

12.2 Basic Adders 291

FIGURE 12.3. (a) In-out signals in a multibit adder; (b) Carry-ripple adder (4 bits); (c) Carry-ripple adder without the inverters in the FA units (Figure 12.2(b)) to reduce the delay of the critical path.

FIGURE 12.2. Full-adder implementations: (a) Sum and carry-out computed by conventional gates; (b) 28T CMOS design, with combined computations for s and cout; (c) Mux-based full-adder, which requires 18T when the multiplexers are constructed as in Figure 11.16(b) or just 8T ( at the expense of speed) if implemented as in Figure 11.16(c).

Figura 1: Somador carry-ripple.

8. Utilizando o somador da Figura 1, realize a soma de a = "0101", b = "1101"e cin = ’1’ aplicados às suasentradas (Obs: a3, b3 e c3 são os MSB). Escreva os valores de todos os bits da soma da soma e de carry.Verifique se o resultado está correto.

9. Compare o somador da Figura 1 com o da Figura 2. Qual deles é mais rápido? Qual é mais compacto? Ésimples criar um somador manchester carry-chain com 10 bits? Por quê?

Any architecture intended to make the circuit faster falls in one of the following two general categories: (i) faster carry propagation (reduction of the time required for the carry signal to propagate through the cell) or (ii) faster carry generation (local computation of the carry, without having to wait for signals produced by preceding stages).

Both approaches are depicted in Figure 12.5, with Figure 12.5(a) indicating a faster carry propagation and Figure 12.5(b) indicating a faster carry generation (each stage generates its own carry-in bit). To attain a high performance adder, both aspects must be considered. However, some emphasize mainly a faster carrier transmission (e.g., Manchester carry-chain adder), while others concentrate fundamentally on faster carry generation (e.g., carry-lookahead adder).

12.3.3 Manchester Carry-Chain AdderThe Manchester carry-chain adder falls in the category of fast adders depicted in Figure 12.5(a), that is, it is a carry-propagate adder in which the delay through the carry cells is reduced. It can be static or dynamic. An example of the latter is presented in Figure 12.6(a), where the individual cells are from Figure 12.4(b). This circuit implements Equations 12.13–12.16, with G and P given by Equations 12.10–12.11. Alternatively, Pi = ai + bi can be used to compute P. Thanks to these parameters (G and P), the delay in each cell is just one gate-delay, which is an improvement over the carry-ripple adder seen earlier. The critical path corresponds to P0 = P1 = P2 = P3 = . . . = '1'and G0 = G1 = G2 = G3 = . . . = '0', in which case all P-controlled transistors are serially inserted into the carry path (that is, the last carry bit is determined by cin). However, the parasitic capacitance of this long line limits the usefulness of this approach to about 4 to 8 bits. (Note that c0 is just a buffered version of cin.)

Another representation for the Manchester carry-chain adder is presented in Figure 12.6(b), in which the critical (longest) path mentioned above can be easily observed.

FIGURE 12.5. General approaches for the design of fast adders: (a) Faster carry propagation (reduction of time needed for the carry to propagate through the cells) and (b) faster carry generation (each stage com-putes its own carry-in bit).

12.3 Fast Adders 295

Figura 2: Somador manchester carry-chain.

10. Escreva as expressões booleanas para o incrementador da Figura 3. Suponha que a = ”10111”, quais sãoos bits de saída? Suponha que a = 11111, qual é o resultado esperado e por que?

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Disciplina: ELD0001 Lista de exercícios 2 Joinville, 16 de março de 2016

304 CHAPTER 12 Combinational Arithmetic Circuits

12.7 ComparatorsAn equality comparator is illustrated in Figure 12.15(a). The circuit compares two vectors, a and b, bit by bit, using XOR gates. Only when all bits are equal is the output '1'.

Another comparator, which is based on an adder, is shown in Figure 12.15(b). It compares two unsigned (nonnegative) numbers, a and b, by performing the operation a − b = a + b! + 1. If the carry-out bit of the last adder is '1', then a " b. Moreover, if all sums are '0', then a and b are equal.

Finally, another unsigned magnitude comparator is shown in Figure 12.15(c), which, contrary to the circuit in Figure 12.15(b), is not adder-based (it employs multiplexers instead, which are controlled by XOR gates). By changing a reference bit from '0' to '1' the circuit can compute a > b as well as a " b, respectively.

EXAMPLE 12.4 SIGNED COMPARATOR

Modify the traditional unsigned comparator of Figure 12.15(b) so it can process signed numbers.

SOLUTION

We saw in Section 3.2 that when adding two N-bit signed numbers to produce an (N + 1)-bit out-put the last carry bit must be inverted if the signs of the inputs are different. Hence, for the circuit of Figure 12.15(b) to be able to process signed numbers, c4 must be inverted when a3 and b3! are

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FIGURE 12.14. (a) Area-ineffi cient adder-based incrementer implementation; More effi cient (b) incrementer, (c) decrementer, and (d) two’s complementer circuits.

Figura 3: Incrementador unitário.

304 CHAPTER 12 Combinational Arithmetic Circuits

12.7 ComparatorsAn equality comparator is illustrated in Figure 12.15(a). The circuit compares two vectors, a and b, bit by bit, using XOR gates. Only when all bits are equal is the output '1'.

Another comparator, which is based on an adder, is shown in Figure 12.15(b). It compares two unsigned (nonnegative) numbers, a and b, by performing the operation a − b = a + b! + 1. If the carry-out bit of the last adder is '1', then a " b. Moreover, if all sums are '0', then a and b are equal.

Finally, another unsigned magnitude comparator is shown in Figure 12.15(c), which, contrary to the circuit in Figure 12.15(b), is not adder-based (it employs multiplexers instead, which are controlled by XOR gates). By changing a reference bit from '0' to '1' the circuit can compute a > b as well as a " b, respectively.

EXAMPLE 12.4 SIGNED COMPARATOR

Modify the traditional unsigned comparator of Figure 12.15(b) so it can process signed numbers.

SOLUTION

We saw in Section 3.2 that when adding two N-bit signed numbers to produce an (N + 1)-bit out-put the last carry bit must be inverted if the signs of the inputs are different. Hence, for the circuit of Figure 12.15(b) to be able to process signed numbers, c4 must be inverted when a3 and b3! are

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FIGURE 12.14. (a) Area-ineffi cient adder-based incrementer implementation; More effi cient (b) incrementer, (c) decrementer, and (d) two’s complementer circuits.

Figura 4: Complementador de 2.

11. Escreva as expressões booleanas para o complementador de 2 da Figura 4. Suponha que a = ”01101”, quaissão os bits de saída? Suponha que a = ”11111”, qual é o resultado esperado e por que?

12. Qual é o “complemento de 2” do número 4 em 4 bits e em 8 bits? Por que são diferentes?

13. Verifique a operação do multiplicador de 2 bits da Figura 5 aplicando a = 11 e b = 10. Indique o nívellógico nas entradas e saídas de cada porta. Obs: o circuito utilizado para som é o somador incompleto -half-adder.

Figura 5: Multiplicador de 2 bits.

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