(12) ulllted states patent (10) patent n0.: us 8,637,849 b2...

US008637849B2

(12) Ulllted States Patent (10) Patent N0.: US 8,637,849 B2 Deligianni et al. (45) Date of Patent: Jan. 28, 2014

(54) VERTICAL NANOWIRE FET DEVICES 6,838,297 B2 1/2005 Iwasaki 6,843,902 B1 1/2005 Penner

. - - - - - . 6,911,373 B2 6/2005 Kellar

(75) Inventors. Harlklllg DehgrgnnnTen?ly, NJS(I~JS), 7,230,286 B2 6/2007 Cohen et a1‘ Qlang “2mg, 551111139 _ (U 2’ 2003/0047749 A1 * 3/2003 Chaudhry et a1. .......... .. 257/135 Lubomyr T- Romanklw, Brlarcllff 2004/0005258 A1 1/2004 Fonash Manor, NY (US) 2004/0238367 A1 12/2004 Penner et a1.

2005/0110145 A1 5/2005 Elers (73) Assignee: International Business Machines Zoos/0167655 A1 8/2005 Furukawa

Cor oration Armonk NY (Us) 2005/0167740 A1 8/2005 Fur'ukawa et a1. P ’ ’ 2005/0172370 A1 8/2005 Haq et a1.

_ _ _ _ _ 2005/0179029 A1 8/2005 Furukawa et a1.

( * ) Notrce: Subject to any d1scla1mer, the term of this 2006/0011972 A1 1/2006 Graham patent is extended or adjusted under 35 2006/0128088 A1 6/2006 Graham et a1.

U.S.C. 154(b) by 514 days. (Continued)

(21) Appl. NO.Z 12/9s4,653 OTHER PUBLICATIONS

- _ H. T. Ng et a1, “Single Crystal Nanowire Vertical Surround-Gate (22) F?ed' Jan‘ 5’ 2011 Field-Effect Transistor Nanotechnology Letters”, vol. 4, pp. 1247

(65) Prior Publication Data 1252 (2004)‘

Us 2011/0108803 A1 May 12, 2011 (Commued)

Primary Examiner * Kimberly RiZkallah Related U-s- APPhcatmn Data Assistant Examiner * Duy T Nguyen

(62) Division of application No. 11/860,459, ?led on Sep. (74) AZwmWAgwL 0" Firm * Louis J- Percello; Ryan, 27, 2007, noW Pat. NO. 7,892,956. Mason & LeWIS, LLP

(51) Int. Cl. (57) ABSTRACT H01L 29/06 (2006-01) A Vertical Field Effect Transistor (VFET) formed on a sub

(52) US. Cl. strate, With a conductive bottom electrode formed thereon. A USPC ................................... .. 257/24; 257/E29.245 bottom dielectric spacer layer and a gate dielectric layer sur

(58) Field of Classi?cation Search rounded by a gate electrode are formed thereabove. There USPC .................. .. 257/24, 220, 302, 329, B29245; above is an upper spacer layer. A pore extends therethrough

977/762, 938 betWeen the electrodes. A columnar Vertical Semiconductor See application ?le for complete search history. Nanowire (VSN) ?lls the pore and betWeen the top and bot

tom electrodes. An FET channel is formed in a central region (56) References Cited of the VSN betWeen doped source and drain regions at oppo

site ends of the VSN. The gate dielectric structure, that is US‘ PATENT DOCUMENTS formed on an exterior surface of the VSN above the bottom

2 690 422 A 9/1954 szekeley dielectric spacer layer, separates the VSN from the gate elec 53203736 A 6/1994 Stickney et a1. trode 5,581,091 A 12/1996 Moskovits 5,612,563 A 3/1997 Fitch 20 Claims, 21 Drawing Sheets

230’ 242

212 240 230

220

/' 310 200

US 8,637,849 B2

(56) References Cited

U.S. PATENT DOCUMENTS

2006/0249726 A1 2006/0273389 A1 2007/0199826 A1

OTHER PUBLICATIONS

11/2006 Choi et al. 12/2006 Cohen et al. 8/2007 Son et al.

J. Goldberger et al, “Silicon Vertically Integrated Nanowire Field Effect Transistors”, American Chemical Society, Nano Letters, vol. 6, pp. 973-977 (2006). J. Chen et al, “Vertical nanowire transistor in ?exible polymer foil”, Applied Physics Letters, vol. 82, pp. 4782-4784 (2003). J. Chen et al, “Vertical nanowire transistors With low leakage cur rent”, Applied Physics Letters, vol. 85, pp. 1401-1403 (2004). Heydon et al., “Magnetic Properties of Electrodeposited NanoWires” J. Phys. D: Appl. Phys. vol. 30, pp. 1083-1093 (1997).

Zhang et al. “Fabrication of Highly Ordered InSb Nanowire Arrays by Electrodeposition in Porous Anodic Membranes”, Journal of the Electrochemical Society 152 (10), pp. C664-C668 (2005). Martin, “Nanomaterials: A Membrane-Based Synthetic Approach” Science Vol . 266, No. 5193, pp. 1961-1966 (1994). P. Nguyen et al, “Direct Integration of Metal Oxide Nanowire in Field-Effect Nanotransistor”, American Chemical Society, Nano Letters 4 (4), pp. 651-657 (2004). T. Bryllert, “Vertical Wrap-gated nanowire Nanotechnology, vol. 17, p. $227-$230 (2006). T. Bryllert, “Vertical High-Mobility Wrap-Gated InAs Nanowire Transistor”, IEEE Electron Device Letter, vol. 27, pp. 323-335 (2006). V. Schmidt et al, “Realization of a Silicon Nanowire Vertical Sur round-Gate Field-Effect Transistor”, Small, vol. 2, pp. 85-88 (2006). Whitney et al., “Fabrication and Magnetic Properties of Arrays of Metallic Nanowires”, Science, vol. 261, No. 5126, pp. 1316-1319 (1993).

transistors”,

* cited by examiner

US. Patent Jan. 28, 2014 Sheet 1 0f 21 US 8,637,849 B2

PRIOR ART FIG. 1A

PRIOR ART FIG. 1B 100


242

FIG. 2A

242

FIG. 2B 230’

242

212 240

230

220

/v 210 200 FIG. 2C


230’ 230, 242 242

212 240 240 230 230

220

210

200 / FIG. 2D

270

230’

242 212 240

230

220

210

200 / FIG. 2E

212

210

200 FIG. 2F


230’ 230’ 242 242

212 240 240 230

230

220 22°

210

200 / FIG. 2G

22o’ 230’ 230,

242 242 212 240 240

230 23°

220 220

210 200 / FIG. 2H

312

30° 31° FIG. 3A


FIG. 3C

FIG. 3D


FIG. SE

300

/ FIG. 3F 300


FIG. 3G

370 380 370

330’

392 390 380 330

320

310

FIG. 3H 300/

U S. Patent Jan. 28, 2014 Sheet 8 0f 21 US 8,637,849 B2

412

410

FIG. 4A 400

412

400 FIG. 4B


412

/ FIG. 4c

412

410

/ 400 FIG. 41)

U S. Patent Jan. 28, 2014 Sheet 10 0f 21 US 8,637,849 B2

412

FIG. 4E

400

412

FIG. 4F 400

US. Patent Jan. 28, 2014 Sheet 11 0121 US 8,637,849 B2

412

/ FIG. 4G

480 444 480

412

FIG. 4H


412

/ FIG. 41

412

FIG. 4.]

US. Patent

512

512

500

Jan. 28, 2014 Sheet 13 0f 21 US 8,637,849 B2

514 540 542 514 550 560 550 550

520’

542 '

540 530

520

510

FIG. 5A

500

522 520’

530’ 542 540 530

520

510


522 520’

530’

512 540

530’ 542

512 540

530

520

510

500


514 514

522i 540 530” 542 l 5221

530’

512 540

512

/ \ / FIG. 5F


512

\ /

/ 560 FIG. SG

512


512

572” l 572” i

512

500 / \ / FIG. 5J


512

\

/ 56° FIG. 5K

512

/ \ / FIG. 5L

(12) ulllted states patent (10) patent n0.: us 8,637,849 b2...

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