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A Current-Mode DRAM for CVNS
R f A W k I P
A Current Mode DRAM for CVNS
Report of A Work In Progress
Golnar KhodabandehlooGolnar Khodabandehloo
Dr. M. Ahmadi
Dr. M. Mir
June 13 2008June 13 , 2008
Outline2
MotivationCVNSCVNS
IntroductionDigit GenerationError Correction
Current-Mode DRAMIntroductionStorage Cell
DRAM for CVNSCircuits, Simulations results
XORD-LatchD LatchCVNS to BinaryBinary to CVNSRefresh Circuit
Future WorkFuture Work
Motivation3
Memory DesignCompactness
More than 1 bit storage on each cell
Low refreshing rate
Fast read/write
CVNS, a potential candidate
Introduction to CVNS4
Continuous Valued Number System
Non-integer modular arithmetic with positive radix
Uses classical analog circuits for implementation
Analog arithmetic advantages High Speed
Limited interconnectionsLimited interconnections
Reduced Area
Reduced system and cross-talk noise
Allows for arbitrary accuracy of arithmetic circuits
Digit Generation in CVNS5
Cascade Digit Generation
Modular Digit GenerationCalculates the radix- B CVNS digits in serial, starting from MID
M 99 84 100a < M
((a))n= (a. B) / M (MID)
99.84 < 100
((a))1 = (99.84×10) / 100=9.984
((a))n-1 = {((a))n - ⎣((a))n ⎦ }× B ((a))0 = (9.984 - 9) × 10 = 9.84
((a))n-2 = {((a))n-1 - ⎣((a))n-1 ⎦ } × B
…
((a))-1 = (9.84 - 9) × 10 = 8.4
…
Digit Generation in CVNS6
Cascade Digit Generation
Modular Digit GenerationComputes all of the radix- B CVNS digits in parallel, independent of each other
a < M
((a))n =(a. Bn-n+1 / M) mod B
99.84 < 100
((a))2 =(99.84 / 10) mod 10= 9.984
((a))n-1 =(a. Bn-(n-1)+1 / M) mod B
((a))n 2 =(a. Bn-(n-2)+1/ M) mod B
((a))1 =(99.84 ×1) mod 10= 9.84
((a)) =(99 84×10) mod 10= 8 4((a))n-2 (a. B / M) mod B
…
((a))0 =(99.84×10) mod 10= 8.4
…
(α)mod β = α – β ⎣ α / β ⎦
… …
Error Correction in CVNS7
Digit RecoveringChain-like relationship between digits (overlap)
Reverse Evolution (RE) MethodReverse Evolution (RE) MethodIncreases the accuracy of analog digitsA sequential process
Error Correction in CVNS (Cont.)8
RE method
((a))i (original digit) k ≤ i ≤ n(( ´)) ( d di it) (( ))((a´))i (errored digit) = ((a))i + εi
[((a´))i ]R = [((a´))i - ((a″))i-1 / B] R mod+B ((a´))≥ 0[((a´))i ]R = [((a´))i - ((a″))i 1 / B] R mod-B ((a´))< 0
((a))″i (corrected digit) = [((a´))i]R + ((a″))i-1 / B i > K
((a´)) i = K
[((a ))i ]R [((a ))i ((a ))i-1 / B] R mod B ((a ))< 0
- (a) mod+ B = (a mod B + B)mod B 0 ≤ (a) mod+ B < B
((a ))i i = K
- (a) mod- B = (a mod B - B)mod B -B < (a)mod- B ≤ B
Error Correction in CVNS (Cont.)9
Example for a random value; a = 9.9845, B= 10, error=±0.4
((a))i 9.9845 9.845 8.45 4.5 5
i 2 1 0 -1 -2
Error is introduced to each digit
8.05((a´))i 10.3845 10.245 4.9 5.4
----
Error is introduced to each digit
5.4 / 104.54 / 10
[ 7.596 ]R = 8
8.454 / 10
[9.3996 ]R = 9
9.8454 / 10
[9.39996]R = 9 [4.36] R = 4
5.44.548.4549.84549.98454
Error propagation from LID to MID ε´n = εk / Bn-k
Introduction to Current-Mode DRAM10
Dynamic Random Access Memory Memory cells requiring constant refreshing
Capacitor
Transistor
Current-Mode DRAMFast sensing speed for the stored values
C fCapability of operating at lower power supply voltages
Storage Cell in Current-Mode DRAM11
Current Copier Cell as a Storage Element
Current-Mode DRAM for CVNS12
Correction Using CVNSa15 a14 a13 a12a14 a13 a12 a11a13 a12 a11 a10a a a a
→ ((a))15 → ((a))14 → ((a))13 → ((a))a12 a11 a10 a9
a11 a10 a9 a8a10 a9 a8 a7a9 a8 a7 a6
→ ((a))12 → ((a))11 → ((a))10 → ((a))9
a8 a7 a6 a5a7 a6 a5 a4a6 a5 a4 a3a5 a4 a3 a2
→ ((a))8 → ((a))7 → ((a))6 → ((a))5a5 a4 a3 a2
a4 a3 a2 a1 a3 a2 a1 a0a2 a1 a0
→ ((a))5 → ((a))4 → ((a))3 → ((a))2
(( ))a1 a0a0
→ ((a))1→ ((a))0
Current-Mode DRAM for CVNS (Cont.)13
Block Diagramg
Binary Input Binary/CVNS Storage Cells CVNS/BinarySynchronousLess number of switches
1-Bit Latch
Less number of switches
More faultError
CorrectionUnit
Asynchronous Faster
More switches
Better correctionBetter correction
XOR14
Circuit
Simulation Result
D-Latch15
Circuit
Simulation Result
Q
D
E
Binary To CVNS16
Circuit
Simulation Result
MIDB=1
LMID
MLID
LID
Binary To CVNS (for 4-bit)17
Circuit
Simulation Result
B3= 1B2= 1B1= 0B1 0B0= 1
10*1+5*1+2.5*0+1.25*1= 16.25uA16.25uA
CVNS To Binary18
Circuit
CVNS To Binary (for 4-bit)19
Circuit
Simulation Result
I_In= 16.25uA
B0
B1
B2
B3
Refresh Circuit20
Simulated Circuit
Corrected Current
Refresh Circuit (Cont.)21
Simulation Result
B3C t I 3
B2
Current-In
Current-Out
B1
BVC
B0
XORCorrected-Current
Future Work22
Extend for 16-bit
Draw the Layout