CSC414ComputerSystemFundamentals

THINK BIG WE DO

U R Ihttp://www.forensics.cs.uri.edu

Digital Forensics CenterDepartment of Computer Science and Statics

The Central Processing Unit

CPU

The Central Processing Unit

CPU

The CPUCentral Processing Unit- Intel CPUs- 8086/8088 (XT), 80286 (AT)

- 80386DX/SX/SL, 80486DX/DX2/DX4

- Pentium Series

- Celeron, Celeron M

- XEON, Itanium, Atom, i5, i7 and more

- Other common CPUs- AMD - Intel Compatible

- IBM/Motorola PowerPC, PPC

- ARM Cortex

CPU ArchitectureComputers have a Von Neumann Architecture- Instructions and data stored in memory- Complex Instruction Set Computing (CISC)- Intel and AMD Processors

- Reduced Instruction Set Computing (RISC)- PowerPC (Power Macintosh)- ARM Processors- Smartphones- Tablets- Dec Alpha- IBM RISC 6000

Instructionsand Data

Mem

ory

Bus

CPU ArchitectureCU (Control Unit)- Performs fetch/execute cycle- Accesses program instructions and issues

commands to the ALU- Moves data to and from CPU registers and other

hardware componentsALU (arithmetic logic unit)- Performs calculations and comparisons- FPU - Floating Point UnitMMU (Memory Management Unit)- supervises fetching instructions and data from

memory

Mem

ory

Bus

ALU

CUMMU

FPU

CPU ArchitectureRegisters- Small storage locations within the CPU- Manipulated directly by the Control Unit- Each register is wired for specific function- Can hold data, an address or an instruction- Scratchpad for currently executing programCaches- Fast (expensive) memory close to CPU- Stores frequently used instructions and dataI/O Interface- sometimes combined with memory

management unit as Bus Interface Unit

CU

I/O Interface

CachesMMU

Registers

ALU

FPU

RegistersSpecial Purpose Registers- Program Count Register (PC)- Memory location of next instruction

- Instruction Register (IR)- Stores instruction fetched from memory

- Memory Address Register (MAR)- Where to Store/Fetch

- Memory Data Register (MDR) - What is stored/fetched

- Status Registers- Status of CPU and currently executing program

- I/O Registers

Memory

RegistersAccessing Memory from the CPU- Each memory location has a

unique address

- Address from an instruction is copied to the MAR which finds the location in memory

- CU determines if it is a store or retrieval

- Transfer takes place between the MDR and memory

- MDR is a two way register

One Bit

1010111000001000

Mem

ory Address R

egister

Address D

ecoder

0000011000001000Memory Data Register

Set Bits

CPU InstructionsData Movement (load, store)- Involve memory and registers

Arithmetic and Boolean Logic- Integers and floating point

- Testing AND OR XOR

Bit manipulation instructions- Flags to test for conditions

- Shift and rotate

Program control (branching)I/O and machine control

CPU InstructionsInstructions are comprised of- Operation (op code)- Use of specific registers can be implied by op code

- Address Field- Where to get the data for the operation

Instruction sets differ by CPU type- Length of the op code

- Number of operands

- Length of operands01000010011011110110110101100010Example 32-bit Instruction Format

011011110110110101100010010000108-bit

op code24-bit

address field

Fetch - Execute CycleFetch- (bring instructions & data to CPU)- Decode or find instruction- Load from memory into register- Prepare ALU Execute- Performs operation that matches

op code- Moves or transforms dataInstruction Pipelining- Getting next instruction and data

during previous instruction's execute cycle

Program Counter (PC) Memory Address Register (MAR)

Memory Data Register (MDR) Instruction Register (IR)

Instruction Data Address

(IR[address])

Memory Address Register (MAR)

Fetch

Exe

cute

Accumulator

Accumulator

Memory Data Register (MDR)

Memory Data Register (MDR)

Accumulator / MDROperation

Accumulator

Program Counter (PC)Increment Program Counter (PC)

THINK BIG WE DO

U R Ihttp://www.forensics.cs.uri.edu

Digital Forensics CenterDepartment of Computer Science and Statics

Central Processing Unit

Central Processing Unit