Advanced Semiconductor on Insulator Substrates for Low Power and High Performance Digital CMOS Applications

Bich-Yen Nguyen*, Mariam Sadaka*, Nicolas Daval, Walter Schwarzenbach, Cecile Aulnette,

Konstantin Bourdelle, Fabrice Letertre, Christophe Maleville, Carlos Mazure

Email: bich-yen.nguyen@soitecusa.com *SOITEC USA, 1010 Land Creek Cv, Austin, TX 78746, USA

SOITEC, Parc Technologique des Fontaines, Bernin 38926 Crolles Cedex, France Abstract It has become increasingly difficult to scale CMOS transistors beyond 130nm, yet still maintain high drive currents and reduce supply voltage (Vdd). Much attention has been focused on high mobility for boosting performance of the short channel devices. In this paper we will review the latest development in substrate engineering using the Smart CutTM technique, new device architecture and challenges for III-V/Ge CMOS co-integration on the Si platform. INTRODUCTION The concept of shrinking semiconductor device dimensions according to Moore’s law has been the mainstay of CMOS integrated circuits over many generations of technology and continues today relatively unabated. However, it has become increasingly difficult to scale CMOS transistors beyond 130nm, yet still maintain high drive currents and reduce supply voltage (Vdd). Therefore, much attention has been focused on high mobility channels that exhibit increased inversion layer mobility and higher carrier velocities, especially for boosting performance of the short channel devices. Such devices exhibit higher drive current enabling high speed, low power IC applications. Starting at 90nm technology node, uniaxial strain have been implemented into existing Si CMOS process for boosting the performance of both N-type and P-type transistors (1), however the performance booster factor by the uniaxial stressors is

reduced with technology scaling (2). As a result, despite of increasing strain level for each technology node, performance of N-type transistor seems to saturate with scaling as shown in Figure 1, and both p-type and N-type transistors need much more boosters to meet performance requirement at each technology node starting at 15nm.

Figure 1: Saturation drain current vs gate pitch From this viewpoint, attention has recently been paid to high mobility channel material for boosting the performance and lowering the operating voltage for low power consumption. These high mobility channel materials include biaxial strain Si, SiGe, Ge and III-V and Ge (3-9). The new III-V high-mobility materials are expected to replace silicon in the channel of the transistor for further boosting performance and/or reducing the Vdd for beyond 11nm technology node. As such, MOSFETs using these new materials must be fabricated on Si

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substrates in order to fully utilize the Si CMOS platform & infrastructure. This implies, the necessity to co-integrate III-V/Ge on Si substrates. This heterogeneous integration is expected to realize novel LSIs utilizing a variety of device families along More Moore, More-than-Moore and Beyond-CMOS approaches (9). In this paper we will review the latest development including substrate engineering using the Smart Cut technique as shown in Figure 2 (10-11), new device architecture and challenges for III-V/Ge CMOS co-integration on the Si platform.

Figure 2: Smart Cut Process for SOI, GeOI and III-V on Insulator DISCUSSION Germanium or III-V Channel engineering for high performance Logic: To extend Moore’s law beyond 11nm technology node, high-mobility materials are expected to replace silicon in the channel of transistors for further boosting performance and lowering power consumption. The most studied high-mobility materials for NMOS are biaxial strain Si (3-5) and III/V materials (7-9), in particular GaAs, InGaAs, and InAs. Compressive strain SiGe alloy or pure Ge with optimum surface orientation (3-4) and channel direction are usually contemplated

for boosting PMOS mobility or performance (8-9). Good progress has been made in achieving the high performance unipolar MOSFET with the physical gate length of sub-50nm for Ge and III-V channel. Recently the heterogeneous integration of Ge and III-V channel was realized for high speed logic CMOS (9), but still suffers from high subthreshold swing (100mV/decade or higher) and high drain-induced barrier lowering (DIBL) even with long gate length. Defectivity: Figure 3 shows the lattice constant of the Si, Ge and III-V materials. So selection of the appropriate buffer layer is necessary to reduce the lattice mismatch between the buffer and channel materials as illustrated in Figure 4 (7), in order to reduce threading dislocations which have direct impact on the leakage and yield. Another approach includes growing the thin III-V film on the Germanium on Insulator (GeOI), with its thickness below the critical thickness. The thickness of the thin transferred III-V film can be increased beyond critical thickness by additional epitaxial growth after the transfer. Furthermore, ultra-thin compound semiconductor on Insulator (XOI) structures have been demonstrated. The substrates comprise one or more thin layers of semiconductor materials on a buried insulating layer [9-10], covering a support substrate, generally made of silicon.

Figure 3: Lattice constant vs.Band-Gap for semiconductors

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Figure 4: Thick GaAs/InAlAs buffer is designed to provide the thin InGaAs channel film. (Courtesy by Sematech) Scalability and low leakage: Planar Ultra-Thin Body (UTB) devices are considered among the best candidates to improve the short channel effect (SCE). The ultra-thin SOI, sSOI, GeOI and III-V substrate have been produced using the Smart Cut technique, which enables the UTB GeOI or III-V transistor fabrication for reducing the source-drain leakage, DIBL and vertical field, thus further enhancing scalability, low-field mobility, and reducing standby power consumption for low power/high performance logic (8-9). System on Chip (SoC) Option for Ge/III-V HP Logic: For further enhancing the scaling and performance and enabling the SoC solution as shown in Figure 5; the BOX thickness can be reduced to less than 50nm, thus improving the SCE of the devices due to better gate control. More importantly, the memory and other non-logic devices can also be co-integrated either on SOI or on Si bulk to satisfy all the required elements of the SoC (12).

Figure 5: Main elements of System on Chip and various semiconductors possible substrate solution CONCLUSIONS To meet HP and LP circuit requirements, increasing channel mobility is required to boost transistor performance and/or reduce Vdd for lower power dissipation without performance penalty. The UTB devices with undoped and high mobility channels on the thin insulator film can enable the heterogeneous integration of various device functions for SoC application. Still much integration challenges need to be addressed for further improving the performance, leakage and yield of the Ge and III-V devices. REFERENCES [1] M. Horstmann et al.”Integration and optimization of embedded SiGe, compressive and tensile stressed liners film, and stress memorization effect in advanced SOI CMOS technologies”. IEDM 2000 [2] P. Grudowski et. al.,”1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations”, VLSI Symp. Proceedings, 2006 [3] F. Andrieu et al,”25 nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack”,

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VLSI Symp. Proceedings, 2006 [4] A. Thean et al, Uniaxial Biaxial Stress hybridization For Super-Critical Strained-Si Directly on Insulator PMOS with different Channel Orientations. IEDM 2005 [5] F. Andrieu et al.”Co-Integrated Dual Strained Channel on fully depleted sSOI CMOSFET with HfO2/TiN gate stack down to 15nm gate Length”. IEEE SOI Conference 2005 [6] G. Kaurve et al,” Dual Surface Orientation integration for high performance (110) PMOS”, The 210th ECS Proceeding, 2006 [7] R.J.W. Hill et. al, “Self-Aligned III-V MOSFETs Heterointegrated on a 200mm Si-Substrate Using an Industry Standard Process Flow”. IEDM 2010 [8] H. Ko et al. “Ultra-thin compound semiconductor on insulator layers for high-performance nanoscale transistors”, Nature, pp 286-289, Vol 468, Nov. 2010 [9] Takagi et. al., “III-V/Ge CMOS technologies on Si platform”, 2010 VLSI Conference. [10] A.J. Auberton-Hervé et. Al., IEEE SOI Conference,2002, p. 1. [11] C. Maleville et al., IEEE SOI Conference 2001, p.155. [12] A. Khakifirooz et al, VLSI-TSA 2010

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