IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, APRIL 2009 1041

A Low Power 6-bit Flash ADC With ReferenceVoltage and Common-Mode Calibration

Chun-Ying Chen, Michael Q. Le, Member, IEEE, and Kwang Young Kim

Abstract—In this paper, a low power 6-bit ADC that uses refer-ence voltage and common-mode calibration is presented. A methodfor adjusting the differential and common-mode reference voltagesused by the ADC to improve its linearity is described. Power dissi-pation is reduced by using small device sizes in the ADC and relyingon calibration to cancel the large non-ideal offsets due to devicemismatches. The ADC occupies 0.13 mm� in 65 nm CMOS anddissipates 12 mW at a sample rate of 800 MS/s from a 1.2 V supply.

Index Terms—Analog-to-digital (A/D) conversion, calibration,mixed analog–digital integrated circuits, offset cancellation.

I. INTRODUCTION

I N MANY mobile applications, a low power and low res-olution (6 bits) ADC is required to cover a wide range of

sampling rates up to 800 MS/s [1]–[5]. A flash ADC is suitablefor such applications because of its simplicity and inherentlyfast operation [6], [7]. However, a flash ADC exhibits a tradeoffbetween power and linearity as will be explained below. Theperformance of a flash ADC is determined mostly by its sam-pling rate and the random offset in each of the comparison cir-cuits. Techniques such as averaging and offset sampling havebeen used to reduce the effects of these random offsets [8]–[16].As the minimum channel length is reduced in advanced processtechnologies, the power can also be reduced by using a constantW/Lmin ratio (where Lmin is the minimum channel length) forthe devices in the comparison circuits. However, the device mis-match parameter [17]–[19] has not reduced at the samerate as Lmin in the latest process technologies. Thus, circuitsthat have been scaled with a constant W/Lmin ratio will exhibitlarger random offsets than in the previous process technologyusing the same W/L ratio. In order to maintain the same lin-earity performance when compared to older process technolo-gies, the devices here must be sized relatively large to keep therandom mismatches below an acceptable level. In contrast, thearea and power of digital circuitry scales well with the channellength reduction. The presented flash ADC in this paper utilizesdigital calibration techniques to both save power and improvelinearity [20]. It thus overcomes the inherent power versus lin-earity tradeoff associated with this type of data converter.

This paper is organized as follows. Section II provides back-ground. Section III introduces our digital calibration techniques.Measured results are presented in Section IV, which is followedby the conclusion in Section V.

Manuscript received August 21, 2008; revised November 07, 2008. Currentversion published March 25, 2009.

The authors are with Broadcom Corporation, Irvine, CA 92618 USA (e-mail:cychen@broadcom.com).

Digital Object Identifier 10.1109/JSSC.2009.2014701

Fig. 1. Fully differential preamplifier.

II. BACKGROUND

In a 6-bit flash ADC, the input signal is first sampled using atrack-and-hold amplifier (THA). Then, 63 comparison circuitsmake binary decisions based on the difference between the sam-pled signal and 63 reference voltages. Each comparison circuitconsists of a preamp and a comparator. The preamp amplifiesthe difference between the sampled signal and its correspondingreference voltage. The difference is then quantized by a com-parator (CMP).

Fig. 1 shows the circuit for the preamp. The output of thepreamp is

(1)

where is the gain of preamp, and andare the differential input signal and reference voltage,

respectively. Random static and dynamic offsets in the compar-ison circuits usually limit the linearity of a flash ADC. Due torandom device mismatches, transistor M1 is not exactly equalto transistor M2. Likewise, transistor M3 is not equal to tran-sistor M4. This mismatch can be modeled as an offset voltagethat appears at the input of the preamp. Each comparison circuithas a different input referred offset. The random nature of theinput referred offset will cause non-linearity in the output of theADC and results in poor DNL and INL.

The standard deviation of the random offset in each preampwith two differential pairs (as shown in Fig. 1) can be approxi-mated as

(2)

where is a process specific parameter and is thetransistor gate area. For a 6 bit ADC to achieve better than

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1042 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, APRIL 2009

5.7 ENOB, the preamps are usually sized large enough to keepthe standard deviation of random offset below 0.1 LSB,where 1 LSB is equal to the full scale voltage divided by [15].Therefore, the transistor gate area can be expressed as

(3)

where is the full-scale input voltage of the ADC. There-fore, the gate area for each input transistor of the preamp is de-termined by and the , both of which are limited bythe process technology and supply voltage. Increasing the sizeof the input transistors in the preamps increases the load ca-pacitance of the track and hold amplifier (THA) which then in-creases the required THA power dissipation to operate at a givenspeed. The power dissipation is proportional to the preamp inputtransistor gate area, which is inversely proportional to .Hence, the THA power dissipation is also limited by the devicemismatch parameter which is fixed for a given process tech-nology. To save power dissipation, the devices in the preampof the ADC are intentionally sized small (about 0.5 ) in ourdesign. With only Vt mismatch, the resulting 1 sigma input-re-ferred offset for the differential pairs shown in Fig. 3 is about1.7 LSB for the technology used in this design. Calibration canbe used to improve the performance of the ADC that has beenoptimized for low power.

III. CALIBRATION TECHNIQUE

For an ideal comparison circuit, the offset due to device mis-match is zero and the input signal is always compared againstits ideal reference voltage is Ref[k]. However, in the practicalcase each comparison will have an error because the effectivereference voltage for each comparison circuit is shifted from itsideal value due to random mismatches. The basic idea of ourcalibration technique is to determine the offset voltage that ex-ists in each comparison circuit and then use a different referencevoltage, Ref_cal[k], that cancels the offset voltage in each com-parison circuit.

Fig. 2 shows a block diagram of the ADC with calibration. Aresistor ladder generates the reference voltages for the compar-ison circuits. In addition to having 1 LSB steps for the ideal ref-erence voltages, the resistor ladder also generates 1/3 LSB stepsto allow for finer adjustments of the reference voltages used forcalibration. Two switches are connected to the signal input ofevery preamp. During calibration, the signal input is bypassedand the corresponding “ideal” reference voltage (Ref[63:1]) isapplied to the signal input of the preamp. Switches are alsoplaced in front of the reference voltage input of each preamp.These switches allow different voltages to be selected as the ref-erence voltage to the preamp (Ref_cal[63:1]). Since the extravoltages used for calibration are generated from the same re-sistor ladder and the switches negligibly load the normal signalpath of the comparison circuits, no extra power is required.

The reference voltage step size is 1/3 LSB with a 5 bit controlsignal. Thus, the reference voltage calibration range is about

5 LSBs which is enough to cover a 3 sigma variation in the Vtmismatch. The devices in each differential pair are sized suchthat the one sigma offset of each differential pair is less than

1.7 LSB. Compared to a design that achieves 0.1 LSB offset

Fig. 2. Block diagram of ADC with reference voltage calibration.

without any calibration, the size of preamp has been reduced by278 times in our design. This will reduce the power dissipationof the preamp and THA circuits dramatically.

At the start of calibration, the selected reference voltage is thesame as the “ideal” reference voltage Ref[k] that is applied to thesignal input of the kth preamp. If there is zero offset

, the comparison circuit output dithers between 1 with amean value of zero. However, if there is a nonzero offset be-tween the signal input and the reference input, the output has anonzero mean value. The comparison circuit output is integratedto determine which direction to adjust the reference voltage. Thereference voltage is adjusted until the comparison circuit outputhas a mean value of zero. Once this condition is reached, theinput referred offset Vos[k] (which includes both static and dy-namic offsets) is cancelled and the calibrated reference voltageused by the kth preamp is

(4)

Since the matching of resistors is much better than required for6-bit ADC resolution, the reference voltages from the resistorladder are treated as ideal, having negligible random errors.Thus, the maximum residual offset voltage should be bounded to

1/3 LSB after calibration is complete. The calibration processis only required to be done once at power up. After the ADChas been calibrated, the digital calibration circuit is disabledand therefore consumes no power during normal operation.

The number of control bits that are required for the calibra-tion of each comparison circuit is set by the ratio of the desiredcorrection range divided by the calibration step size. This ratiodetermines how many reference voltages are required for eachcomparison circuit. If the correction range is wide, the com-parison circuits can tolerate large device mismatches. This al-lows the device sizes inside the comparison circuits to be sizedsmaller allowing for lower power operation. When a small cal-ibration step size is used, the reference voltage adjustment ismore accurate and the performance of ADC will be improved.However, more digital control bits are required when a large cor-rection range and small calibration step size are desired. Thus,there is an area tradeoff in choosing the correction range and stepsize. Fig. 3 plots the simulated ENOB when using different cal-ibration step sizes as a function of the comparison circuit offset(1 sigma). Here, the calibration range is from negative 15 steps

CHEN et al.: A LOW POWER 6-bit FLASH ADC WITH REFERENCE VOLTAGE AND COMMON-MODE CALIBRATION 1043

Fig. 3. ENOB as a function of the comparison circuit offset for different cali-bration step sizes.

to positive 15 steps (using a 5 bit control signal). If the cali-bration step size is small, the ENOB is high (due to the finercalibration steps), but the ENOB will fall off quickly when therandom mismatch (3 sigma) is outside the reduced calibrationrange. However, if the calibration step is large the maximum at-tainable ENOB is lower in the practical range of comparison cir-cuit offsets. In our design we choose to implement 31 selectablereference voltages that are 1/3 of an LSB apart as a tradeoff be-tween the power/performance and cost. This allows us to cor-rect for up to approximately 3 sigma random offsets which isrequired for good production yield.

During calibration, the comparison circuit that is beingcalibrated has its output applied to the input of the digitalaccumulator. A single digital calibration circuit is sharedamong all of the comparison circuits to save area at the expenseof a longer calibration time. The digital accumulator acts asan integrator. If the mean output in the comparison circuitis nonzero, the accumulator will ramp until it overflows orunderflows. When an overflow/underflow condition occurs, thereference ladder voltage is incremented or decremented by 1/3LSB, respectively, and the digital accumulator is reset to zero.A digital gain control in the accumulator allows the loop gain tobe adjusted. A larger loop gain will allow the calibration loopto converge more quickly for each comparison circuit at theexpense of having more variance in the steady-state calibratedvalues. At the start of calibration, each comparison circuit hasa random offset voltage. The offset gradually gets reduced untilthe error is within about 1/6 of an LSB in optimum case.

For the preamp circuit shown in Fig. 1, the gain is verysensitive to the common mode mismatch between the refer-ence ladder common mode voltage and the THA commonmode output voltage in the hold mode. Aconventional common-mode feedback loop will force thecommon-mode output voltage of the THA to be equal to thereference ladder common-mode voltage in track mode. How-ever, the common mode voltages can be significantly differentin the track and hold modes due to charge injection or the clockfeed through from the THA switches. Thus, the hold modecommon-mode output voltage will be shifted from the referenceladder common-mode voltage. This difference has to be muchless than Vdsat of the input transistors in the preamp otherwise

the effective gain of the preamp will be reduced dramatically.For a low power preamp design, the differential pair is usuallyoperating near (or in) the subthreshold region where its Vdsat issmall. Thus, the common-mode mismatch needs to be small tohave sufficient gain from the preamp. To reduce this commonmode mismatch, a common mode calibration loop is used.

Fig. 4(a) shows the block diagram of common mode calibra-tion circuit. One additional comparison circuit is required bythe common-mode calibration loop. This comparison circuit iswired differently to the preamp than in the previous comparisoncircuits used by the ADC. In Fig. 1 the preamp compares the dif-ference between the input signal and reference voltage. But forthe configuration in Fig. 4 it compares the difference betweenthe THA common mode and the reference ladder mid-point . The output of the differential preamp is

(5)

Hence, the preamp amplifies of the common mode differencebetween and when wired in this configuration. Thepreamp output is then quantized by a comparator. The com-parator output is then integrated to determine the direction toadjust . Once the common-mode voltage is adjusted to itsproper value, the output of the comparator will have a meanvalue of zero. At this point, the common mode voltage differ-ence between the THA output and the reference ladder will beminimized and limited by the residual offset of the comparisoncircuit. However, the comparison circuit offset is small relativeto the common mode mismatch between the THA output andthe reference ladder.

Since the clock used in this comparison circuit is the same asthe one used in the other 63 comparison circuits, the comparatormakes its binary decision only when the THA is in the holdmode. Since this comparator output is used to adjust the THAcommon-mode level, the loop ignores the THA while it is in thetrack mode which is desired. The same digital calibration circuitthat was used by the other 63 comparison circuits is used here tosave area. The disadvantage of sharing this circuitry is that thecalibration time will be longer since it is done serially.

IV. MEASURED RESULTS

Fig. 5(a) shows a histogram of the 5-bit calibration codevalues after the reference voltages for 40 test chips have beencalibrated. The 5 bit reference voltage adjustment gives a codethat ranges from 15 to 15. Each step in the code correspondsto a 1/3 LSB step. The measured 1 sigma offset is about 4.36steps which is equal to 1.5 LSB’s. Thus, the 3 sigma value isabout 13 steps which is equal to 4.5 LSB’s. Since our designhas a 5 LSB correction range, the measured results show thatwe have sufficient coverage in our calibration loop to handle3 sigma offset variations which will provide good productionyield. Fig. 5(b) shows a histogram of 5 bit codes after theTHA output common-mode voltage has been calibrated. Inthe common mode calibration loop, each code correspondsto a 1 LSB change in the common-mode voltage. Again, the

1044 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, APRIL 2009

Fig. 4. (a) Block diagram of common-mode calibration. (b) Preamp compares the common mode difference between signal and reference.

Fig. 5. Histogram of codes for (a) reference voltage calibration and (b) common mode calibration from 40 chips.

Fig. 6. (a) ENOB versus temperature for three chips. (b) ENOB versus input frequency at 800 MS/s.

3 sigma variation plus the mean value of the offset is less thanour correction range. Here, the average offset is nonzero. Themean value gives a measure of the offset introduced by chargeinjection and clock feed through in the THA.

ENOB as a function of temperature for three test chips isshown in Fig. 6(a). The ADC was initially calibrated at roomtemperature. Next, the temperature was varied from 25 C to125 C. The measured variation in ENOB over this temperaturespan is within 0.15 bits. Since the variation over temperatureis small, it is sufficient to calibrate the ADC only once duringthe initial startup. Fig. 6(b) plots the measured ENOB as a func-tion of input frequency at a sampling frequency of 800 MS/s.The ENOB is better than 5.2 up to the Nyquist frequency. TheENOB falls off as a function of frequency because of bandwidthlimitations in the THA circuit since we optimized the design forlow power operation in a frequency band around 200 MHz.

The measured output spectrum before and after calibration isshown in Fig. 7. The spurious free dynamic range of the ADC isabout 35 dB before calibration and about 54 dB after calibration.This represents roughly a 19 dB improvement in SFDR whenusing calibration.

The plots in Fig. 8 show the measured INL and DNL beforeand after calibration. Before calibration, both the INL and DNLare greater than 2 LSB’s which results in a measured ENOB ofless than 3. After calibration, the measured INL and DNL areboth less than half a LSB and the ENOB is about 5.6. So, thereis greater than 2.5 bit improvement in the ADC linearity.

This 6 bit ADC was fabricated in a 65 nm digital CMOS tech-nology and occupies 0.13 mm . A die photo is shown in Fig. 9.Table I provides a performance summary for this ADC. ThisADC shows a better figure of merit compared to two recent pub-lished papers [20].

CHEN et al.: A LOW POWER 6-bit FLASH ADC WITH REFERENCE VOLTAGE AND COMMON-MODE CALIBRATION 1045

Fig. 7. Output spectrum before and after calibration.

Fig. 8. INL and DNL before and after calibration.

Fig. 9. Die photograph.

V. CONCLUSION

A 6-b ADC that uses reference voltage and common-modecalibration has been presented. This ADC uses digital calibra-tion to both reduce power and improve linearity allowing usto overcome the inherent power versus linearity tradeoff in theADC design. This ADC may be of interest in high speed, lowpower applications and is suitable for implementation in deep

TABLE IPERFORMANCE SUMMARY

submicron process technologies where the mismatch propertiesof the process have not scaled proportionally with the channellength reduction.

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Chun-Ying Chen received the B.S. degree inelectrical engineering from National Taiwan Uni-versity, Taipei, Taiwan, in 1989, and the M.S. andPh.D. degrees in electrical engineering from Uni-versity of Michigan, Ann Arbor, in 1993 and 1997,respectively.

From 1991 to 1993, he served as a second rankLieutenant in the Taiwanese army. In 1997, he joinedMotorola Inc., Tempe, AZ. Two years later, he joinedNational Semiconductor Corporation, Santa Clara,CA, working on CMOS analog circuit design. Since

2000 he has been with Broadcom Corporation, Irvine, CA, doing analog andmixed-signal circuit design. He has 40 U.S. patents granted or pending in theareas of PLLs/frequency synthesizers, power management, filters, and highspeed data converter.

Michael Q. Le (S’97–M’08) received the B.S., M.S.,and Ph.D. degrees in electrical engineering from theUniversity of California, Davis, in 1994, 1998, and2000, respectively.

From 1994 to 1995, he was with Level One Com-munications, Sacramento, CA. Since April 2000, hehas been a member of the technical staff at BroadcomCorporation, Irvine, CA, where he has been involvedin the development of high-speed serial gigabit trans-ceivers, analog front ends for HDD read channels,and analog front ends for Blu-ray readers/writers.

His research interests include mixed-signal integrated circuits, adaptiveequalization, timing recovery, and calibrated ADCs.

Kwang Young Kim was born in Seoul, Korea, in1960. He received the B.S. degree in electronics en-gineering from Seoul National University, Korea, in1984, the M.S. degree in electrical engineering fromMarquette University, Milwaukee, WI, in 1986 andthe Ph.D. degree in electrical engineering from theUniversity of California, Los Angeles, in 1996.

From 1996 to 1998, he worked on CMOS ADC atRockwell Semiconductor Systems, Newport Beach,CA. In 1998, he joined Broadcom Corporation,Irvine, CA. His current interests are in low power

analog and mixed-signal circuit.