10 lecf 12 components

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9/17/12

1

CS61C:GreatIdeasinComputerArchitecture

ComputerComponents

Instructors:

KrsteAsanovic,RandyH.Katz

hDp://inst.eecs.Berkeley.edu/~cs61c/fa12

1Fall2012--Lecture#109/17/12

New-SchoolMachineStructures(It’sabitmorecomplicated!)

• ParallelRequests

Assignedtocomputere.g.,Search“Katz”

• ParallelThreadsAssignedtocore

e.g.,Lookup,Ads

• ParallelInstruc]ons>1instruc]on@one]me

e.g.,5pipelinedinstruc]ons

• Parallelata>1dataitem@one]me

e.g.,Addof4pairsofwords

• Hardwaredescrip]onsAllgates@one]me

• ProgrammingLanguages9/17/12 Fall2012--Lecture#10 2

SmartPhone

WarehouseScale

Computer

So-wareHardware

Harness

Parallelism& AchieveHigh

Performance

LogicGates

Core Core…

Memory(Cache)

Input/Output

Computer

CacheMemory

Core

Instruc]onUnit(s) Func]onalUnit(s)

A3+B3A2+B2A1+B1A0+B0

Today’sLecture

FiveComponentsofaComputer

• Control

• atapath

• Memory

• Input

• Output

9/17/12 Fall2012--Lecture#10 3

Processor

Control

Datapath

ComponentsofaComputer

9/17/12 Fall2012--Lecture#10 4

PC

MemoryInput

Output

Enable?

Read/Write

Address

Write

ata

Read

ata

Processor-MemoryInterface I/O-MemoryInterfaces

RealityCheck:TypicalMIPSChipiePhotograph

9/17/12 Fall2012--Lecture#10 5

Integer

Controland

64-bitatapath

Performance-

Enhancing

On-Chip

Memory

(16KBI-Cache+16KB-Cache)

Floa]ng-Point

Controland

atapath

Protec]on-

oriented

VirtualMemory

Support

TypesofMemory

Vola]le(needspowertoholdstate)

• Sta]cRAM(SRAM),builtfrombistablesthatuselocalposi]vefeedbacktoholdvalue

• ynamicRAM(RAM),holdsvaluesoncapacitorsthatmustbeperiodicallyrefreshed

Non-Vola]le(holdsstatewithoutpower)

• Read-OnlyMemory(ROM)–holdsfixedcontents

• Magne]cmemory–Core,plusnewerMRAM

• Flashmemory–canbewriDenonly10,000’s]mes

9/17/12 Fall2012--Lecture#10 6



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2

EarlyRead-OnlyMemoryTechnologies

7

Punchedcards,Fromearly

1700sthroughJaquard

Loom,Babbage,andthen

IBMPunchedpapertape,

instruc]onstreamin

HarvardMk1

IBMCardCapacitorROS

IBMBalancedCapacitor

ROS

iodeMatrix,ESAC-2

µcodestore

EarlyRead/WriteMemoryTechnologies

8

WilliamsTube,

ManchesterMark1,1947

Babbage,1800s:igits

storedonmechanicalwheels

MercuryelayLine,Univac1,1951

9

CoreMemory• Corememorywasfirstlargescalereliablemainmemory

– inventedbyForresterinlate40s/early50satMITforWhirlwindproject

• Bitsstoredasmagne]za]onpolarityonsmallferritecoresthreadedontotwo-dimensionalgridofwires

• CoincidentcurrentpulsesonXandYwireswouldwritecellandalsosenseoriginalstate(destruc]vereads)

DEC PDP-8/E Board,4K words x 12 bits,

(1968)

• Robust,non-vola]lestorage

• UsedonspaceshuDlecomputersun]lrecently

• Coresthreadedontowiresbyhand(25billionayearatpeakproduc]on)

• Coreaccess]me~1µs

10

One-TransistorynamicRAM[ennard,IBM

TiN top electrode (VREF)

Ta2O5 dielectric

W bottomelectrode

polyword

lineaccesstransistor

1-T DRAM Cell

word

bit

access transistor

Storagecapacitor (FET gate,trench, stack)

VREF

Intelformedtoexploitmarket

forsemiconductormemory

FirstcommercialDRAMwas

Intel1103,held1Kbin1970

ModernRAMStructure

11[Samsung,sub-70nmRAM,2004

12

RAMPackaging(Laptops/esktops/Servers)

• IMM(ualInlineMemoryModule)contains

mul]plechipswithclock/control/addresssignals

connectedinparallel(some]mesneedbuffersto

drivesignalstoallchips)

• atapinsworktogethertoreturnwideword(e.g.,

64-bitdatabususing16x4-bitparts)

Address lines multiplexedrow/column address

Clock and control signals

Data bus(4b,8b,16b,32b)

DRAMchip

~12

~7



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3

RealityCheck:SamsungLPR24Gb

RAMChip(May2012)

9/17/12 Fall2012--Lecture#10 13

RAMPackaging,Mobileevices

14[AppleA4packagecrosssec@on,iFixit2010]

Twostacked

RAMdie

Processorplus

logicdie

[AppleA4packageoncircuitboard]

Moore’sLaw“Thecomplexityforminimum

componentcostshasincreasedata

rateofroughlyafactoroftwoper

year.…Thatmeansby1975,the

numberofcomponentsper

integratedcircuitforminimumcost

willbe65,000.”(from50in1965)

“Integratedcircuitswillleadtosuch

wondersashomecomputers--orat

leastterminalsconnectedtoacentral

computer--automa]ccontrolsfor

automobiles,andpersonalportable

communica]onsequipment.The

electronicwristwatchneedsonlya

displaytobefeasibletoday.”

9/17/12 Fall2012--Lecture#10 15

GordonMoore,“Crammingmorecomponents

ontointegratedcircuits,”Electronics,Volume

38,Number8,April19,1965

Moore’sLaw

9/17/12 Fall2012--Lecture#10 16

Predicts:2XTransistors/chipevery2years

GordonMoore

IntelCofounder

B.S.Cal1950! #

o f t r a n s i s t o r s o n a

n

i n t e g r a t e d c

i r c u i t ( I C )

Year

MemoryChipSize

9/17/12 Fall2012--Lecture#10 17

4xin3years 2xin3years

Growthinmemorycapacityslowing

EndofMoore’sLaw?

• It’salsoalawofinvestmentinequipmentas

wellasincreasingvolumeofintegratedcircuits

thatneedmoretransistorsperchip

• Exponen]algrowthcannotlastforever

• Moretransistors/chipwillendduringyour

careers

– 2020?2025?

– (When)willsomethingreplaceit?

9/17/12 Fall2012--Lecture#10 18



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TechnologyTrends:UniprocessorPerformance(SPECint)

9/17/12 Spring2012--Lecture#9 19

ImprovementsinprocessorperformancehaveslowedWhy?

LimitstoPerformance:FasterMeansMorePower

9/17/12 Spring2012--Lecture#9 20

P=CV2f

61CintheNews

9/17/12 Fall2012--Lecture#10 21

InteleveloperForum,September2012

TechnologyUpdatefromMarkBohr,IntelSeniorFellow:

”Confidenttohit5nmbyendofdecade”

Administrivia

• Labs4,Project1bposted

• Midtermisnowonthehorizon(TuesOct9):

– Nodiscussionsec]onsduringexamweek

– Smallnumberofspecialconsidera]oncases,dueto

classconflicts,etc.—contactRandyandme

9/17/12 Fall2012--Lecture#10 22

Projects

• Project2coming:MIPSISAsimulatorinC

– Add~200(repe]]ve)linesofCcodeto

framework

– LotsofCut&Paste

– AppendixBdescribesallMIPSinstruc]onsin

detail

– Makeyourownunittests!

9/17/12 Fall2012--Lecture#10 23

Boilextracted“wort”for90minutes,

addhops,thencooltoaddyeast

Fermentsfor5-7days

Condi]onfor1weekto2years

Ge}ngtoKnowYourProf• MissingthealesIgrewupwithinEngland,I

learnthowtomakebeer.

• Startfromgrains,about5-10gallons/batch

• Brewedover50batchessofar

4/12/11 24Spring2011--Lecture#22

Grainsaremashed

~45-60minutesto

convertstarchtosugar

Needthirstyfriendstohelpconsumeexperiments!

BelgianTrappist12%ABV

Bri]shBarleywine8%ABV

Incellar:

GravensteinCider7.1%ABVMixedCider7.2%ABV

OrdinaryBiDer4.1%ABV

BelgianPaleI~5%ABVBelgianPaleII~5%ABV

ESBI~6%ABV

ESBII~6%ABV



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5

ComputerEras:Mainframe1950s-60s

9/17/12 Fall2012--Lecture#10 25

“BigIron”:IBM,UNIVAC,…build$1Mcomputers

forbusinesses=>COBOL,Fortran,]mesharingOS

Processor(CPU)

I/O

Memory

TheARMInsidetheiPhone

9/17/12 Fall2012--Lecture#10 26

ARMArchitecture

• hDp://en.wikipedia.org/wiki/

ARM_architecture9/17/12 Fall2012--Lecture#10 27

FlashCardQuiz

HowmanyARMprocessorsinaniPhone?

9/17/12 Fall2012--Lecture#10 28

iPhoneInnards

9/17/12 Fall2012--Lecture#10 29

1GHzARMCortex

A8

Youwilllearnaboutmul]pleprocessors,data

levelparallelism,cachesin61C

I/O

I/O

I/O

Processor

Memory

ManydifferentARM

implementa]ons

insideasingle

system!

FlashCardQuiz

Whichoffollowingstatementsistrue?

9/17/12 Fall2012--Lecture#10 30



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6

TheProcessor

• Processor (CPU):theac]vepartofthecomputer,whichdoesallthework

(datamanipula]onanddecision-making)

– Datapath:por]onoftheprocessorwhichcontains

hardwarenecessarytoperformopera]ons

requiredbytheprocessor(“thebrawn”)

– Control :por]onoftheprocessor(alsoin

hardware)whichtellsthedatapathwhatneedsto

bedone(“thebrain”)

9/17/12 31Fall2012--Lecture#10

Processor

Control

Datapath

ComponentsofaComputer

9/17/12 Fall2012--Lecture#10 32

PC

Memory

Enable?

Read/Write

Address

Write

ata

Read

ata

Processor-MemoryInterface

PhasesofInstruc]onExecu]on

• Canbreakuptheprocessof“execu]ngan

instruc]on”intostagesor phases,andthen

connectthephasestocreatethewhole

datapath

– Smallerphasesareeasiertoreasonaboutand

design

– Easytoop]mize(change)onephasewithout

touchingtheothers

9/17/12 33Fall2012--Lecture#10

Project2Warning

• YouaregoingtowriteasimulatorinCfor

MIPS,implemen]ngthese5phasesof

execu]on

9/17/12 Fall2012--Lecture#10 34

Phasesoftheatapath(1/5)

• ThereisawidevarietyofMIPSinstruc]ons:sowhatgeneralstepsdotheyhaveincommon?

• Phase1:Instruc@onFetch

– NomaDerwhattheinstruc]on,the32-bit

instruc]onwordmustfirstbefetchedfrommemory(thecache-memoryhierarchy)

– Also,thisiswhereweIncrementPC(thatis,PC=PC+4,topointtothenextinstruc]on:byteaddressingso+4)

• Simulator:Instruc]on=Memory[PC;PC+=4;

9/17/12 35Fall2012--Lecture#10


• Phase2:Instruc@onDecode

– Uponfetchingtheinstruc]on,wenextgatherdatafromthefields(decodeallnecessaryinstruc]ondata)

– First,readtheopcodetodetermineinstruc]ontypeandfieldlengths

– Second,readindatafromallnecessaryregisters

• Foradd,readtworegisters

• Foraddi,readoneregister

• Forjal,noreadsnecessary

9/17/12 36Fall2012--Lecture#10



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SimulatorforecodePhase

Register1=Register[rsfield;Register2=Register[rƒield;

if(opcode==0)…

elseif(opcode>5&&opcode<10)…

elseif(opcode…)…

elseif (opcode…)…

• BeDerCstatementforchainedifstatements?

9/17/12 Fall2012--Lecture#10 37


• Phase3: ALU(Arithme]c-LogicUnit) – Realworkofmostinstruc]onsisdonehere:

arithme]c(+,-,*,/),shi†ing(<<,>>),logic(&,|),comparisons(<,>)

– Whataboutloadsandstores?• lw$t0,40($t1)

• Addressweareaccessinginmemory=thevaluein$t1PLUSthevalue40

• Sowedothisaddressaddi]oninthisstage

• Simulator: Result=Register1opRegister2; Address=Register1+Addressfield

9/17/12 38Fall2012--Lecture#10


• Phase4:MemoryAccess

– Actuallyonlytheloadandstoreinstruc]onsdoanythingduringthisphase;theothersremainidleduringthisphaseorskipitalltogether

– Sincetheseinstruc]onshaveauniquestep,weneedthisextraphasetoaccountforthem

– (Asaresultofthecachesystem,thisphaseisexpectedtobefast:talkaboutnextweek)

• Simulator: Register[rƒield=Memory[Addressor Memory[Address=Register[rƒield

9/17/12 39Fall2012--Lecture#10


• Phase5:RegisterWrite

– Mostinstruc]onswritetheresultofsome

computa]onintoaregister

– E.g.,:arithme]c,logical,shi†s,loads,slt

– Whataboutstores,branches,jumps?

• on’twriteanythingintoaregisterattheend

• Theseremainidleduringthisfi†hphaseorskipitall

together

• Simulator: Register[rdfield=Result

9/17/12 40Fall2012--Lecture#10

AndinConclusion

• FiveComponentsofaComputer

– Processor/Control+atapath

– Memory

– Input/Output:Humaninterface/KB+Mouse,isplay,Storage…evolvingtospeech,audio,video

• TechnologyScaling(Moore’sLaw)slowingdown,butnotoveryet.Powerlimitssequen]alperformance

• ArchitecturalFamily:OneInstruc]onSet,ManyImplementa]ons

• Fivephasesofinstruc]onexecu]on:

– Fetch/ecode/Execute/Memory/Writeback

9/17/12 Fall2012--Lecture#10 41

10 lecf 12 components

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