10 gbps serial backplanes using virtex-ii pro x
TRANSCRIPT
![Page 1: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/1.jpg)
10 Gbps
Serial
Backplanes
using Virtex-II
Pro X
Xilinx, Inc.
![Page 2: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/2.jpg)
2
Networking
Telecom
Computing
Storage
VideoVirtex-4
RocketPHY
Serial I/O Landscape
0.622 1.0 2.0 3.0 5.0 10.0 11.0
OC-12 OC-48 OC-192
GbE XAUI 10GbECEI (OIF)
SATA3
SATA2SATA
1GFC 2GFC
PCIE
HD-SDI
SATAGbE
1.45
1.25 2.51.5 3.0
0.622 2.488
3.1251.25 10.3136.25
1.5 3.0 6.0
1.06 2.12
9.952
10GFC
6.0
10.519
SATA2
Rate (Gb/s)
CEI (OIF)11G
Virtex-II Pro
4GFC4.25
Virtex-II Pro
X
8GFC8.5
![Page 3: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/3.jpg)
3
Introduction• Why are better models, techniques, and tools needed?
– Speed = Problems
• Evolution of a short circuit
– Once interconnects stop behaving as transmission lines, SPICE
models and SPICE like tools can not predict performance
SPEED
A. Fraser, S. Argyrakis, “Does Signal Integrity Engineering have a Future”, DesignCon 2003,.
![Page 4: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/4.jpg)
4
Introduction• Why are better models, techniques, and tools needed?
– Co-dependent terms
• Example: As speed increases, the connector performance
begins to depend on the board integration
?
![Page 5: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/5.jpg)
5
At these high data rates…..
Courtesy: Agilent Technologies – Educator’s corner
![Page 6: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/6.jpg)
6
Without the proper tools….
Rules of Thumb???
![Page 7: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/7.jpg)
7
Estimated Backplane
Prototyping Costs28 Layers, approx 16"X18", 0.240" thick
0
1000
2000
3000
4000
5000
6000
PCB T
oolin
gPC
B Tes
t5
boar
ds (5
-day
)
10 b
oard
s (5
-day
)
5 bo
ards
(4W
KS)
10 b
oard
s (4
WKS)
Assem
bly
Pe r
Bo
ard
Co
st
(in
$)
FR-4
Nelco13
Numbers based on estimates from Whizz Systems
![Page 8: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/8.jpg)
8
Board Re-spins Cost
Time & Money
Courtesy: Agilent Technologies – Educator’s corner
![Page 9: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/9.jpg)
9
Project Schedules Slip…..
Manager
You!!
Courtesy: Agilent Technologies – Educator’s corner
![Page 10: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/10.jpg)
10
Physical Channel Design
Challenges
• There can be significant degradation to the data
after it has passed through the transmission path.
– Degradation includes loss of signal amplitude,
reduction of signal rise time, and a spreading at the
zero crossings.
DRIVER RECEIVER
Board
Interconnect
![Page 11: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/11.jpg)
11
Channel is a low-pass filter
Courtesy: Agilent Technologies – Educator’s corner
![Page 12: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/12.jpg)
12
Virtex Features: Backplanes
Direct interface to other
devices, reduces
component count
YesYesIntegrated AC coupling
Equalizes stringent channel;
allows legacy backplanes
to be upgraded
Linear and
DFELinearReceive Equalization
Yes
Yes
Yes
Yes
Equalizes simple channelsYesYesTransmit Pre-Emphasis
Automatically finds optimum
EQ setting for a given
channel; eases design
and ensures Signal
Integrity
Automatic EQ Settings
Algorithm
Reduces Power
Reduces Reflections
Benefit
YesYesProgrammable Voltage
Swing
YesYesProgrammable
Termination
Feature
![Page 13: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/13.jpg)
13
Equalization Options: Summary
6-tap6-zeros
9-poles
3-tap
(pre- and post-cursor)
-4-zeros
7-poles
2-tap
(post-cursor)
--2-tap
(post-cursor)
DFE Rx
EqualizationDiscrete-time
Linear Rx
EqualizationContinuous-time
Tx
Pre-EmphasisDiscrete-time
Any combination of the three techniques can be combined simultaneously
![Page 14: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/14.jpg)
14
Physical Channel Design
Challenges
• It is critical to model the transmission path whendesigning a high-performance, high-speed serialinterconnect system
– Transmission path may include long transmission lines,connectors, vias and crosstalk from adjacent interconnect
DRIVER RECEIVER
Board
Interconnect
![Page 15: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/15.jpg)
15
So many handles….
![Page 16: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/16.jpg)
16
Enter Gigabit Virtual Design
Kit• Xilinx teamed with Ansoft to provide customers with an
extendable methodology for 10 Gb/s serial channel design
– (Virtex II Pro-X Board design kit available at Xilinx
“SICentral’ website:
http://www.xilinx.com/products/design_resources/highs
peed_design/resource/si_gig.htm)
• Parameterized Board Design Kit for Virtex–II Pro X
• Optimization and rapid what-if analyses made simple, to
serve Xilinx high-speed FPGA customers!!
![Page 17: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/17.jpg)
17
Agenda
• Board Design for Virtex–II Pro X
– BGA Package Modeling
– Transmission Line Models
– Via Modeling
– SMA Connector Modeling
– Using the Models in Nexxim
Simulation = Measurement for nominal
design
![Page 18: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/18.jpg)
18
Design Example: Virtex-II Pro
X Evaluation BoardRX Pair TX Pair
![Page 19: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/19.jpg)
19
Evaluation Board High-Speed
Interconnect
• Transmission path includes the FPGA package, a
differential microstrip transmission line in FR4, a
differential via structure, a stripline transmission
line, and an SMA connectorDRIVER RECEIVER
BGA
Package
Microstrip
Transmission
Line
Differential
Via
SMA
Connector
Stripline
Transmission
Line
![Page 20: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/20.jpg)
20
Design Methodology• Where possible, segregate the system into individual
components
• Chain together the individual components for a complete
system design
Package
Stripline
Microstrip
Connector
Via
![Page 21: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/21.jpg)
FF896 Flip-FF896 Flip-
ChipChip
PackagePackage
![Page 22: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/22.jpg)
22
FF896 Flip Chip Package• TX Differential Pair – HFSS Version 9.2
• 4-Port Single Ended Lumped Ports
Differential S-Parameters
![Page 23: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/23.jpg)
MK322MK322
EvaluationEvaluation
BoardBoard
![Page 24: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/24.jpg)
24
Vias
Microstrip
Stripline
MK322 Evaluation Board•12 Layer Board
•100 Ohm Differential Signaling
•Board Material: FR4
•Trace & Plane Layers: 0.5 oz. copper (0.65 mil thick)
Virtex II Pro X Evaluation Board
TX PairRX Pair
![Page 25: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/25.jpg)
25
MK322 Stack Up
Stripline
Microstrip
![Page 26: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/26.jpg)
26
MK322 Evaluation Board –
Microstrip ModelsDesigner Version 2.0
– Circuit Models
• Multi-Coupled Line Model
– A Four-Layer Substrate stackup was used to account for the solder mask
4-Layer Model
Circuit ModelDifferential S-Parameters
![Page 27: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/27.jpg)
27
• Designer Version 2.0
– PlanarEM used to model Part 7
– Circuit Components used to model Parts 1 – 6
• The stripline is approximately 2.5 inches long
Part1
Part3
Part2
Part4
Part5 Part7
Part6
MK322 Evaluation Board –
Stripline Model
![Page 28: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/28.jpg)
28
• MK322 Evaluation Board – Differential Via
– Through Hole Via
• The via will have the largest impact on
the overall channel so it is important to
be able to study the effect of variations
in this structureDifferential S-Parameters
MK322 Evaluation Board –
Via Model
![Page 29: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/29.jpg)
29
50 Ohm Stripline Launch on Layer 10
Single-ended S-Parameters
MK322 Evaluation Board
– Connector Model • MK322 Evaluation Board – Differential Via
– Connector model from Rosenberger• Connector ground pin stubs – 37 mils long
• Connector signal pin stub – 22 mils long
• Output for the MK322 board
![Page 30: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/30.jpg)
FullFull
ChannelChannel
ResultsResults
![Page 31: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/31.jpg)
31
Full Channel Model in Designer(frequency domain)
• Nexxim
– Frequency Profile Extraction
• Group Delay
• Transmission (Insertion Loss)
• Reflection (Return Loss)
![Page 32: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/32.jpg)
32
Full Channel Model Results
(frequency domain)
Group Delay
855ps
Differential S-Parameters
• Nexxim Circuit Simulator– Frequency Domain Data
• Group Delay
• S-Parameters
![Page 33: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/33.jpg)
33
Full Channel Model in Designer(time domain)
• System Model
– Transient Simulation
– Measurement Correlation
![Page 34: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/34.jpg)
34
• System Model
– Eye Diagram Comparison• Pseudo-Random Bit Source (2^31 – 1 pattern)
• Eye Opening
Full Channel Model Results(time domain)
Xilinx Measured Data
Eye Height = 292 mV
Eye Width = 70.8 ps
Ansoft Designer System Simulator
Eye Height = 318 mV
Eye Width = ~ 90 ps
![Page 35: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/35.jpg)
35
• Quad AAAA Pattern
– Alternating 1’s and 0’s
– Risetime (10-90%)
• System Simulation: ~53ps
• Measured: 51.7ps
Full Channel Model Results(time domain)
![Page 36: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/36.jpg)
What What –– If If
AnalysisAnalysis Alternate Via Route Alternate Via Route
LayersLayers
Alternate Line Alternate Line
LengthsLengths
Alternate Data RatesAlternate Data Rates
![Page 37: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/37.jpg)
37
• Through Hole Via– Parameterized Geometry
• Antipad Radius
• Via Radius
• Via Pad Radius
• Route Layer
• Trace Width
• Ground Via Distance
MK322 Evaluation Board –Differential Via Antipad Radius
Pad RadiusVia Radius
![Page 38: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/38.jpg)
38
• MK322 Evaluation Board –
Differential Via– Through Hole Via
– Parameterized Geometry
• Route Layer
MK322 Evaluation Board –Differential Via
![Page 39: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/39.jpg)
39
• Via Route Layer
– Through Hole Via
• Stripline Traces can be
routed on:
– Layer 3
– Layer 5
– Layer 10 (nominal)
MK322 Evaluation Board –Differential Via
![Page 40: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/40.jpg)
40
• Via Route Layer
– Through Hole Via
• Stripline Traces can be routed on:
– Layer 3
– Layer 5
– Layer 10 (nominal case)
Single-ended S-Parameters
MK322 Evaluation Board –Differential Via
Differential S-Parameters
![Page 41: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/41.jpg)
41
•Nominal Length is approximately 2.5 inches
•Data Rate is 10 GbpsLength = 2.5 inches
Length = 5.0 inches
Stripline Length – Eye Diagrams
Length = 7.5 inches
Length = 10.0 inches
![Page 42: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/42.jpg)
42
Stripline Length –
Differential S-Parameters•Nominal length is approximately 2.5 inches
•Frequency swept from 0.1 to 40 GHz
L=2.5 inches
L=5.0 inches
L=7.5 inches
L=10.0 inches
![Page 43: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/43.jpg)
43
•30ps Rise TimeData Rate 2.5 Gbps
Data Rate 3.125 Gbps
Data Rate 5 Gbps
Data Rate 10 Gbps
Data Rate 10 Gbps
Channel – Data Rate
![Page 44: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/44.jpg)
44
These bad boys can be
managed !
Courtesy: Agilent Technologies – Educator’s corner
![Page 45: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/45.jpg)
45
Surf’s Up!!
![Page 46: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/46.jpg)
46
Board Design Kit
• The models shown in this presentation have been
assembled into a “Design Kit” for Virtex-II Pro-X
customers, which is available at the Xilinx
“SICentral”.
– Design kit will include parameterized HFSS and
Designer models for transmission lines, differential
vias, and connectors
– A white paper that describes the use methodology
will be included
![Page 47: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/47.jpg)
47
Board Design Kit
• Customers of Xilinx and Ansoft may use the
parameterized design kit to evaluate board and
system design in a virtual environment to
accelerate the ability to design high-speed
systems, right the first time!!
![Page 48: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/48.jpg)
48
Additional Considerations
• Predicting pre-emphasis/optimization settings
• Inclusion of driver/receiver models
• SIwave results are being worked on to show post
layout verification… the ability to incorporate
decoupling capacitor strategies into the overall
backplane design
![Page 49: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/49.jpg)
AppendixAppendix
![Page 50: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/50.jpg)
50
• AnsoftLinks 3.0 creates models from the following layout tools:
– Cadence
• APD
• Allegro
• Virtuoso
– Mentor
• Expedition
• Board Station
– Zuken
• CR5000
– Synopsis
• Encore
Translation Path
AnsoftLinks
Zuken Synopsis
Mentor
Cadence
Ansoft
TPA
Ansoft
Q3D
Ansoft
SIWave
Ansoft
HFSS
Ansoft
Designer
![Page 51: 10 Gbps Serial Backplanes using Virtex-II Pro X](https://reader031.vdocuments.site/reader031/viewer/2022021010/6203ce3545d3a268f4270974/html5/thumbnails/51.jpg)
51
• Pads to Mentor Expedition
• Mentor Expedition to AnsoftLinks 3.0
Translation Path –
MK322 Board
AnsoftLinks
PADS
Mentor Expedition
Ansoft
SIWaveAnsoft
HFSS
Ansoft
Designer