(1) the need for pll. - laboratoire d'informatique de …hassan/cirf10_pll_lecture.pdf · pll...
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Ahmed Ashry
Introduction to PLL
Outline
1. The need for PLL
2. PLL Specifications
3. PLL Structure
4. Type-I PLL Design
5. More PLL Types
6. Exercise (written + Matlab)
Introduction to PLL Ahmed Ashry 2
(1) The need for PLL.
•Why PLL is needed?
•Why not simple Oscillator?
•Why not simple VCO?
Outline (1/6)
Introduction to PLL 3Ahmed Ashry
Frequency selection
• LO frequency choose which channel to select.
• Error in LO frequency = wrong channel or more distortion
Introduction to PLL Ahmed Ashry 4
LO needed
• Very accurate.
– Example: GSM 900MHz ± 0.1ppm = ± 90Hz
– On-chip LC oscillator = ± 10% = ± 90MHz
– Crystal Oscillators (XO) are accurate, but:
• Low Frequency ~ 10MHz.
• Fixed.
• Programmable:
– It is always needed to change the channel.
– XOs are fixed.
– What about VCO (Voltage Controlled Oscillator) ?
Introduction to PLL Ahmed Ashry 5
VCO is possible?
• Ideally, VCO can be used
to produce any desired
frequency.
• However, practically this
is impossible.
Introduction to PLL Ahmed Ashry 6
VCO is possible? No!
• Process and
temperature variations
make it more difficult
Introduction to PLL Ahmed Ashry 7
• The needed accuracy
requires very stable
control voltage
VCO is possible? No! (2)
• VCO (or generally free-running oscillator) has
poor close-in phase noise compared to PLL.
Introduction to PLL Ahmed Ashry 8
(2) PLL Specifications.
•Tuning Range
•Step Size
•Settling Time•More…….
Outline (2/6)
Introduction to PLL 9Ahmed Ashry
PLL Specifications (1)
• Tuning Range:
• The frequency band covered by the PLL.
• It must cover the target application.
• GSM: 890MHz – 915MHz
• Step size:
• Must be at least equal to channel spacing.
• GSM: 200kHz
Introduction to PLL Ahmed Ashry 10
PLL Specifications (2)
• Settling Time:
• Fast switching between channels.
• GSM: 280us (90Hz error)
Introduction to PLL Ahmed Ashry 11
PLL Specifications (3)
• Frequency Stability:• Accuracy of reference source.
• GSM: 90Hz/900MHz =
0.1ppm
• Inaccurate frequency
wrong selection worst BER
Introduction to PLL Ahmed Ashry 12
PLL Specifications (4)
• Spurs (undesired
harmonics): cause
interferes with other
channels.
• Phase noise (random
fluctuation of carrier
frequency): cause
interferes with other
channels.
Introduction to PLL Ahmed Ashry 13
(3) PLL Structure.
•PLL Block diagram.•PLL Linear Model.•PLL Main Blocks.•PLL Simple Design.•PLL Phase Noise
Outline (3/6)
Introduction to PLL 14Ahmed Ashry
What is “Phase” ?
• It is simply the number of cycles.
• 1 cycle = 2π
• If the frequency is constant:
• Or, generally:
Introduction to PLL Ahmed Ashry 15
( ) ( )otAtV ϕω +⋅⋅= sin
( ) ( )( )tAtV ϕsin⋅=( ) ott ϕωϕ +⋅=
( ) ( )∫ ⋅=t
dttt0
ωϕ
( ) ( )tdt
dt φω =
PLL (Phase-Locked Loop)
• PLL is a negative feedback system.
• It compares “Phase” not “Amplitude”
• When PLL is in lock (steady-state), feedback phase is
equal to the input phase.
Introduction to PLL Ahmed Ashry 16
PLL Linear Model
• PLL is a non-linear system.
• However, under certain conditions (near lock), it
can be “linearized”.
• State variable is the phase.
Introduction to PLL Ahmed Ashry 17
PLL Blocks (1-Phase detector) 1
• XOR is the simplest PD
Introduction to PLL Ahmed Ashry 18
0%00 =→=→=∆ dVDφ
2/%502
VddVD d =→=→±=∆π
φ
PLL Blocks (1-Phase detector) 2
• For stable operation,
the loop should be
designed, such that
the nominal output
of the PD is Vdd/2
• Kd=Vdd/π
Introduction to PLL Ahmed Ashry 19
2/%502
VddVD d =→=→±=∆π
φ
PLL Blocks (2-Divider)
• Toggle Flip-Flop T-FF can acts a divide by 2.
• Cascading T-FFs can divide by 2n
• Adding some logic can extend the division ratio
to any integer.
Introduction to PLL Ahmed Ashry 20
PLL Blocks (3-LPF)
• Filters the PD output.
• Weak filtering (Wide BW) leads to “Spurs”.
• Small BW leads to longer settling time.
• Filter structure determines PLL type.
Introduction to PLL Ahmed Ashry 21
PLL Blocks (4-VCO)
• VCO: Voltage Controlled Oscillator.
• Kvco: VCO sensitivity.
• fo: Free-running frequency.
Introduction to PLL Ahmed Ashry 22
( ) ( )∫ ⋅=t
dttt0
ωϕ
( ) CVCO VKt ⋅=ω
( ) CVCO Vs
Ks ⋅=ϕ
PLL Design
• Given:
– Output frequency fout
– Channel spacing. df
• Required:
– fref=?
– N=?
• Steps:
• fref = df
• N=fout / fref
Introduction to PLL Ahmed Ashry 23
Fractional PLL
• What if the required channel spacing is smaller than
the available reference frequency?
– Solution (1): Fractional-N PLL (out of our lecture scope)
– Solution (2): Reference division:
Introduction to PLL Ahmed Ashry 24
Design Example
• Design a PLL for GSM (fout = 900MHz, df=200kHz)
• Available reference is 13MHz.
• Solution:
– M=13MHz/200kHz = 65
– N= 900MHz/200kHz = 4500
Introduction to PLL Ahmed Ashry 25
PLL Phase noise (1)
• PLL phase noise is mainly
due to main sources:
1. Reference (input)
Low phase noise (clean source).
Noise gain (N).
Low-pass Filter.
2. VCO
Higher phase noise.
Unity noise gain.
High-pass Filter.
Introduction to PLL Ahmed Ashry 26
Phase noise (2)
• Each noise source is shaped with the corresponding
transfer function
– Reference: Gain=N LPF. (Close-in noise)
– VCO: Gain=1 HPF (Far-out noise)
• It is clear that (N) and (BW) determine PLL Phase Noise.
Introduction to PLL Ahmed Ashry 27
(4) Type-I PLL.
•Type-I Design Equations.
•Design Example.
Outline (4/6)
Introduction to PLL 28Ahmed Ashry
Type I PLL
• Type I means there is only “one” integrator,
which is the VCO itself.
• Very simple structure.
• Rarely used in communication systems. (Type-II is preferred)
• Open-loop gain:
Introduction to PLL Ahmed Ashry 29
( ) ( )Ns
KsFKsA vco
d
1⋅⋅⋅=
( )( )sRCs
KsA
+=
1 N
KKK vcod ⋅
=
• Natural frequency:
• Damping coefficient:
Type I PLL
• Second order
feedback system
• Open loop gain:
• Closed loop gain:
Introduction to PLL Ahmed Ashry 30
( )( )sRCs
KsA
+=
1
( )22
2
2 nn
n
ssNsB
ωξω
ω
++=
( ) ( )( )sA
sANsB
+=
1RC
Kn =ω
RCK ⋅=
2
1ξ
Zeta effect
• Low values
cause
overshoot
• High values
cause slow
settling
• Optimum is
0.707
Introduction to PLL Ahmed Ashry 31
0 1 2 3 4 5 6 70
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
step response
Time (sec)
Am
plit
ude
0.1
0.5
0.7
3
5
ξ BW effect
• Higher BW
means fast
settling.
• Settling with 5%
error,
Approximately:
Introduction to PLL Ahmed Ashry 32
0 1 2 3 4
x 10-6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
step response
Time (sec)
Am
plit
ud
e
0.3MHz
1MHz
3MHz
nn
sf
t16.4
≈⋅
≈ωξ
nn f⋅= πω 2
PLL Type-I Design (1)
• Given:
– Output frequency fout
– Channel spacing. df
– Settling time. ts
– XOR detector
• Required:
– fref=?
– N=?
– Ko=?
Introduction to PLL Ahmed Ashry 33
PLL Type-I Design (2)
Steps:
fref = df
N=fout / fref
fn = 1/ts
Introduction to PLL Ahmed Ashry 34
707.0=ξnn f⋅= πω 2
n
RCξω2
1=
ξ
ω
2
nK =
• XOR detector -> Kd=Vdd/πd
vcoK
KNK
⋅=
Exercise 1
• Design a type-I PLL with the following
specifications:
– Output center frequency 60MHz.
– Channel spacing 1MHz.
– Settling time 20us
Introduction to PLL Ahmed Ashry 35
Solution (1)
• fref = df = 1MHz
• N=fout / fref = 60MHz/1MHz = 60
• fn = 1/ts = 50kHz
Introduction to PLL Ahmed Ashry 36
707.0=ξskrfnn /3102 =⋅= πω
sRCn
µξω
3.22
1== skrK n /220
2==
ξ
ω
Ω= kR 1 nFC 3.2=
Solution (2)
• Kd=Vdd/π = 0.38V/rad
Introduction to PLL Ahmed Ashry 37
VsrMK
KNK
d
vco /)/(35=⋅
=
VMHzK
K vcoo /6.5
2==
π
Matlab Verification (Linear Model)
• Matlab can be
used to verify the
linear model.
Introduction to PLL Ahmed Ashry 38
0 1 2 3 4 5 6
x 10-5
0
10
20
30
40
50
60
70phase step response
Time (sec)
Am
plit
ude
0 10 20 30 40 50 60 70 80 90 1000
0.1
0.2
0.3
0.4
0.5
0.6
0.7
time (us)
Vc
(V
)
Matlab Verification (Time Model)
• Simulink Model.
• Control voltage
settling.
• Ripples due to
reference signal.
Introduction to PLL Ahmed Ashry 39
refIn1 Out1
VCO+divider
Vc_sim
To Workspace
In1
In2Out1
Phase detector
In1 Out1
LPF (5) More PLL Types.
•Type-II PLL.
•Fractional-N PLL.
•All-Digital PLL.
Outline (5/6)
Introduction to PLL 40Ahmed Ashry
• Error due to phase step:
• Steady-state error.
Type-I Limitations (1)
• Open loop gain:
• Phase error :
• Phase step:
Introduction to PLL Ahmed Ashry 41
( )( )sRCs
KsA
+=
1
( )( )
222
1
nnss
RCss
sEωξω ++
+⋅=
( )( )sA
sE+
=1
1
( )s
sin
ϕθ
∆=
( )( )
222
1
nn
ess
RCs
sωξω
ϕθ
++
∆⋅+=
( ) 00
≠=se sθ ( ) 0≠
∞=te tθ
Type-I Limitations (2)
• Solution:
– Add extra pole at origin, i.e. additional integrator.
– This adds additional “s” to the equation:
– Now, we have “2” poles at origin (Filter + VCO) Type-II
Introduction to PLL Ahmed Ashry 42
( )( )
22
2
2
1
nnss
RCss
sEωξω ++
+⋅= ( )
( )22 2
1
nn
ess
RCss
sωξω
ϕθ
++
∆⋅+=
( ) 00
==se sθ
( ) 0=∞=te tθ
Type-II Filter Implementation (1)
• Integrator: Capacitor.
• But, with 2 poles at origin, the
root-locus lies on the imaginary
axis.
• The PLL is unstable (marginally).
• Filter modification is needed.
Introduction to PLL Ahmed Ashry 43
( )Cs
sZ⋅
=1
Type-II Filter Implementation (2)
• Adding extra RC section.
• Adds additional pole and zero.
• Z<P system is conditionally
stable.
• By proper design, the desired
BW and damping coefficient
(zeta) can be obtained.
Introduction to PLL Ahmed Ashry 44
( ) ( )( )Pss
ZsksZ
+⋅
+=
Type-II PFD (1)
• Phase detection is usually done using PFD
(Phase-Frequency Detector) “instead of XOR”
Introduction to PLL Ahmed Ashry 45
Type-II PFD (2)
• Better phase and frequency detection range.
Introduction to PLL Ahmed Ashry 46
Complete Type-II PLL
• PFD:
– Phase-Frequency
Detector.
• CP:
– Charge Pump.
• Z(s):
– Filter
• VCO:
– Voltage-Controlled
Oscillator
Introduction to PLL Ahmed Ashry 47
(6) Exercise.
•Written part.
•Matlab part.
Outline (6/6)
Introduction to PLL 48Ahmed Ashry
References
• “Introduction to Charge Pump PLL Frequency Synthesizers”,
Ayman Ahmed, Si-Ware Systems.
• National Application Note:
http://www.national.com/an/AN/AN-1001.pdf#page=1
• Fujitsu Application Note:
http://www.siliconrfsystems.com/Papers/U11614%20PLL%20Basics-%20Fujitsu.pdf
Introduction to PLL Ahmed Ashry 49
Thank you
Questions?
Introduction to PLL 50Ahmed Ashry