1 sequential digital circuits alexander titov 11 october 2014

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Sequential Digital Circuits Alexander Titov 11 October 2014

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Page 1: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

1

Sequential Digital CircuitsAlexander Titov11 October 2014

Page 2: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

2Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

Layers of Abstraction in Computes Science (CS)

Application

Algorithms

Programming Language

Operating System

Instruction Set Architecture

Microarchitecture

Gates/Register-Transfer Level (RTL)

Circuits

Physics

Topics of this lecture

Page 3: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

3Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

• But, combinational circuits have a significant limitation: they cannot remember any information

Refresher: Combinational vs. Sequential Circuits• If the output of a function is completely defined by

the current input then the function is called combinational:Qt = F(xt, yt, zt,

…)• Combinational circuit (scheme) is an implementation of a combinational function

• A lot of things can be implemented using combinational circuits• Just a few examples that we already know: summator,

decoder, multiplexer

• But, combinational circuits have a significant limitation:

Page 4: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

4Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

Sequential Circuits

• Sequential circuits are able to store information

• If the output of a function depends not only on the current input, but on the previous state, then the function is called sequential

Qt = F(xt, yt, zt, …, Qt-

1)F(xt-1, yt-1, zt-1, …, Qt-2))

F(xt-2, yt-2, zt-2, …, Qt-3)))

• Sequential circuit is an implementation of a sequential function

• Their main advantage is ability to remember the previous state• Any circuit with memory is a sequential circuits

Page 5: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

5Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

SR Flip-Flop

S R Qt-1 Qt

x y out

0 0 1

0 1 0

1 0 0

1 1 0

Q

!Q

xy

out

yout

xy

out

0≡

out

Q

!Q

reset

set

0

0

1 0

11

0

1

NOR:

SR flip-flop:

o The simplest store element:

o SR flip-flop:

0 1

0 0 Q Q

0 1 Q 0

1 0 Q 11 1 Q 0

reset

set

Q

!Q

Prohibited state

Page 6: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

6Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

SR Flip-Flopreset

set

Q

!Q

R

!QS

QS R Qt-1 Qt

0 0 Q Q

0 1 Q 0

1 0 Q 1

1 1 Q 0

S0

1

R0

1

Q0

1

!Q0

1

?

?

But, which signal will be really faster will depend on many factors (e.g., temperature).

The output will be determined by the fastest signal

Page 7: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

7Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

D Flip-Flop

• Don’t have prohibited states• Asserted by a level of the write enable signal (we)• Store one bit of information• Can be used as building block for creating static memory

arrays

S

QR

!Q

Write enable

DataD

we

QD we Qt-1 Qt

D 0 Q Q

0 1 Q 0

1 1 Q 1

Page 8: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

9Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

Single port 2^MxN Memory Array

MemoryArray

address

input data output data

M

N N

Write enable

Page 9: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

10Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

Single port 4x1 Memory Array

MemoryArray

address

input data output data

2

1 1

Write enable

Page 10: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

11Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

Single port 4x1 Memory Array

De

Q De

Q De

QDe

Q

S0 S1

IN0

Write Enable

OUT0

Multiplexer

Decoder

Writ

e co

ntro

l

Page 11: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

12Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

Single port 4x2 Memory Array

De

Q De

Q De

QDe

Q

S0 S1

IN0

Write Enable

OUT0

De

Q De

Q De

QDe

QIN1

OUT1

Multiplexer bit[0]

Decoder

Writ

e co

ntro

lMultiplexer bit[1]

Page 12: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

Critical paths

13

Page 13: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

14Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

What is a critical path of scheme?

• Critical path is the slowest logic path in the circuit

• Reliable result of whole logic path can not be ready until critical path is passed by signal

Page 14: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

15Intel Laboratory at Moscow Institute of Physics

and Technology MIPT-MIPS 2014 Project

Example of critical path finding:Multiplexer

Page 15: 1 Sequential Digital Circuits Alexander Titov 11 October 2014

Thank YouQ/A

16

Page 16: 1 Sequential Digital Circuits Alexander Titov 11 October 2014