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Pertemuan 5

Fabrikasi IC CMOS

Matakuliah : H0362/Very Large Scale Integrated Circuits

Tahun : 2005

Versi : versi/01

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Learning Outcomes

Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menyebutkan proses fabrikasiIC CMOS.

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IC Fabrication

Sumber: http://mems.cawru.edu/shortcourse/figure/I_2.1.gif

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Silicon Processing

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Silicon wafer

Sumber: http://www.amd.com

Diameter

Wafer

Die sites

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Material Growth & Deposition

Silicon oxide

Silicon wafer

O2 flow

Silicon wafer

SiO2 layerX

Si

Xox

Growth phase Final structure

Substrate

CVD oxide

SiO2 molecues

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IC Layers

Ion implanterIon source accelerator

Magnetic mass separator

Ion beam

wafer

Ion

Silicon wafer

Silicon nuclei

electron cloud

x0

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Lythography

poly

substrate

poly

substrate

After oxide deposition After CMP

Glass Pattern on underside

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Lythography

Spinning wafer

Photoresist spray

Vcuum chuck

Resist application

Photoresist coating

Coated wafer

Wafer

Flat resist

Edge bead Edge bead

Beading

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Lythography

UV

Reticle

Resist-coatedWafer surface

Reticleshadow

Projection optics(not shown)

Exposure step

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Lythography

Wafer

UV

Reticle

Resist

Exposure pattern

Wafer

After development and rinsing

Hardenedresist layer

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Lythography

Hardenedresist layer

Substrate

Initial patterning of resist

Oxide layer

After etching process

Substrate

Pattern oxide layer

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Lythography

Incoming ion beam

Substrate

Arsenic ions

Doped n-type region

Substrate

n+ n+

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CMOS Process Flow

p-epitaxial layer

p+ substrate

a. Starting wafer with epitaxial layer

n-wellp, Na

b. Creation of n-well in p-epitaxial layer

n-wellp, Na

c. Active area definition using nitride / oxide

p, Nan-well

d. Silicon etch

Nitridep, Na

n-well

e. Field oxide growth

FOX FOX FOX FOX

p, Nan-well

f. Surface preparation

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CMOS Process Flow

a. Gate oxide growth

p, Na

n-well

b. Gate oxide growthPoly gate deposition & patterning

p, Na

n-well

poly

c. pSelect mask and implant

p, Nan-well

resist

Boron implant

p+ implantd. nSelect mask and implant

p, Na

n-well

resist

Arsenic implant

n+ implant

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CMOS Process Flow

a. After anneal and CVD oxide

p, Nan-well

b. After CVD oxide active contact, W plugs

p, Nan-well

W W W W W W c. Metal 1 coating and patterning

p, Nan-well

Metal 1

Metal bonding pad

Bond

Bonding pad

Ke pin IC

Overglasswire

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Design Rules

w

p

w

p

Sp-p

poly

poly

Wp = minimum width of polysilicon line

Sp-p

= minimum poly-topoly

spacing

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RESUME

• IC Fabrication: Flow of process.

• Silicon Processing: wafer, material growth, deposition.

• Lythography: pattern, photoresist coating, exposure steps, etching, n-type.

• CMOS Process flow.

• Design rules