– 2 –

1. OUTLINE OF CIRCUIT DESCRIPTION1-1. CA1 and A PART OF CA2 CIRCUIT

DESCRIPTIONSAround CCD block

1. IC ConfigurationCA1 boardIC903 (ICX411AK) CCD imagerIC901 (CXD3400N) V driverCA2 boardIC911 (H driver, CDS, AGC and A/D converter)

2. IC903 (CCD imager)[Structure]Interline type CCD image sensor

Image size Diagonal 8.293 mm (1/1.8 type)Pixels in total 2384 (H) x 1734 (V)Recording pixels 2288 (H) x 1712 (V)

Fig. 1-2. CCD Block Diagram

Pin No.

1

Symbol

2, 3

4

5, 6

9, 15

10

11

12

13, 20

14, 19

16

17

18

Vø4

Vø2

Vø1A, Vø1B

GND

VOUT

VDD

CSUB

VL

øRG

Hø1

Hø2

Pin Description

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock

Horizontal register transfer clock

Substrate bias

Reset gate clock

Horizontal register transfer clock

GND

Signal output

Circuit power

Substrate clock

Protection transistor bias

Waveform

DC

DC

Voltage

-7.5 V, 0 V

-7.5 V, 0 V, 15 V

-7.5 V, 0 V

-7.5 V, 0 V, 15 V

15 V

0 V, 5 V

0 V, 5 V

Table 1-1. CCD Pin Description

øSUB

GND

DC

0 V

Aprox. 10 V

Approx. 8 V

12.5 V, 16 V

When sensor read-out

Vø3A, Vø3B

DCApprox. 8 V(Different from every CCD)

8 1

18 19 20

234567

13 14 15 16 17

Ye Cy

G

Ye

G

Ye

Mg

Cy

Mg

Cy Cy

Mg

Cy

MgG

Ye

G

Ye

Ye Cy

(Note)

VD

D

GN

D

SU

B

CS

UB

VL

H

1

H

2

Ver

tical

reg

iste

r

G Mg G Mg

V

4

V

3B

V

2

V

1A

V

1B

TE

ST

V

3A

TE

ST

Horizontal register

(Note) : Photo sensor

910

1211

GN

D

VO

UT

RG

H

2

H

1

Ø Ø

Ø Ø Ø Ø

Ø Ø Ø Ø Ø Ø

– 3 –

Fig. 1-2. IC911 Block Diagram

CCDIN

RG

H1-H4

VDHD SDATASCKSL

CLI

CLPOB

CLPDM

DOUT

VRBVRT

PRECISIONTIMINGCORE

SYNCGENERATOR

PxGA VGA ADC12

2~36 dB

PBLK

VREF

CLAMP

INTERNALREGISTERS

INTERNALCLOCKS

CDS

CLAMP

HORIZONTALDRIVERS4

3. IC901 (V Driver) and IC911 (H Driver)An H driver and V driver are necessary in order to generatethe clocks (vertical transfer clock, horizontal transfer clockand electronic shutter clock) which driver the CCD.IC901 is V driver. In addition the XV1-XV4 signals which areoutput from IC102 are the vertical transfer clocks, and theXSG signal which is output from IC102 is superimposed ontoXV1 and XV3 at IC901 in order to generate a ternary pulse.In addition, the XSUB signal which is output from IC102 isused as the sweep pulse for the electronic shutter. A H driveris inside IC911, and H1, H2 and RG clock are generated atIC911.

4. IC911 (CDS, AGC Circuit and A/D Converter)The video signal which is output from the CCD is input to Pin(29) of IC911. There are inside the sampling hold block, AGCblock and A/D converter block.The setting of sampling phase and AGC amplifier is carriedout by serial data at Pin (37) of IC911. The video signal iscarried out A/D converter, and is output by 12-bit.

5. Lens drive block5-1. Iris and shutter driveThe shutter and iris stepping motor drive signals (IIN1, IIN2,IIN3 and IIN4) which are output from the ASIC (IC102) areused to drive by the motor driver (IC951), and are then used todrive the iris steps.

5-2. Focus driveThe focus stepping motor drive signals (FIN1, FIN2, FIN3 andFIN4) which are output from the ASIC expansion port (IC107)are used to drive by the motor driver (IC952). Detection of thestandard focusing positions is carried out by means of thephotointerruptor (PI) inside the lens block.

5-3. Zoom driveThe zoom stepping motor drive signals (ZIN1, ZIN2, ZIN3 andZIN4) which are output from the ASIC expansion port (IC107)are used to drive by the motor driver (IC952). Detection of thestandard zoom positions is carried out by means ofphotoreflector (ZPI) inside the lens block.

– 4 –

1-2. CA2 CIRCUIT DESCRIPTION

1. Circuit Description1-1. Digital clampThe optical black section of the CCD extracts averaged val-ues from the subsequent data to make the black level of theCCD output data uniform for each line. The optical black sec-tion of the CCD averaged value for each line is taken as thesum of the value for the previous line multiplied by the coeffi-cient k and the value for the current line multiplied by thecoefficient 1-k.

1-2. Signal processor1. γ correction circuitThis circuit performs (gamma) correction in order to maintaina linear relationship between the light input to the cameraand the light output from the picture screen.

2. Color generation circuitThis circuit converts the CCD data into RGB signals.

3. Matrix circuitThis circuit generates the Y signals, R-Y signals and B-Y sig-nals from the RGB signals.

4. Horizontal and vertical aperture circuitThis circuit is used gemerate the aperture signal.

1-3. AE/AWB and AF computing circuitThe AE/AWB carries out computation based on a 64-segmentscreen, and the AF carries out computations based on a 6-segment screen.

1-4. SDRAM controllerThis circuit outputs address, RAS, CAS and AS data for con-trolling the SDRAM. It also refreshes the SDRAM.

1-5. Communication control1. SIOThis is the interface for the 8-bit microprocessor.

2. PIO/PWM/SIO for LCD8-bit parallel input and output makes it possible to switch be-tween individual input/output and PWM input/output.

1-6. TG/SGTiming generated for 4 million pixel CCD control.

1-7. Digital encorderIt generates chroma signal from color difference signal.

2. Outline of OperationWhen the shutter opens, the reset signals (ASIC and CPU)and the serial signals (“take a picture” commands) from the8-bit microprocessor are input and operation starts.When the TG/SG drives the CCD, picture data passes throughthe A/D and CDS, and is then input to the ASIC as 12-bitdata. The AF, AE, AWB, shutter, and AGC value are com-puted from this data, and three exposures are made to obtainthe optimum picture. The data which has already been storedin the SDRAM is read by the CPU and color generation iscarried out. Each pixel is interpolated from the surroundingdata as being either Ye, Cy, Mg or B primary color data toproduce R, G and B data. At this time, correction of the lensdistortion which is a characteristic of wide-angle lenses iscarried out. After AWB and γ processing are carried out, amatrix is generated and aperture correction is carried out forthe Y signal, and the data is then compressed by JPEG andis then written to card memory (smart media).When the data is to be output to an external device, it is takendata from the memory and output via the USART. When playedback on the LCD and monitor, data is transferred from memeryto the SDRAM, and the image is then elongated so that it isdisplayed over the SDRAM display area.

3. LCD BlockDuring monitoring, YUV conversion is carried out for the 12-bit CCD data which is input from the A/D conversion block tothe ASIC and is then transferred to the DRAM so that theCCD data can be displayed on the LCD.The data which has accumulated in the DRAM is passedthrough the NTSC encoder , and after D/A conversion is car-ried out to change the data into a Y/C signal, the data is sentto the LCD panel and displayed.If the shutter button is pressed in this condition, the 12-bitdata which is output from the A/D conversion block of theCCD is sent to the DRAM (DMA transfer), and after proces-sor, it is displayed on the LCD as a freeze-frame image.During playback, the JPEG image data which has accumu-lated in the flash memory is converted to YUV signals, andthen in the same way as during monitoring, it is passed throughthe NTSC endoder, and after D/A conversion is carried out tochange the data into a Y/C signal, the data is sent to the LCDpanel and displayed.The two analog signal (Y/C signals) from the ASIC are con-verted into RGB signals by the LCD driver, and these RGBsignals and the control signal which is output by the LCD driverare used to drive the LCD panel. The RGB signals are 1Htransposed so that no DC component is present in the LCDelement, and the two horizontal shift register clocks drive thehorizontal shift registers inside the LCD panel so that the 1Htransposed RGB signals are applied to the LCD panel. Be-cause the LCD closes more as the difference in potential be-tween the COM (common polar voltage: fixed at DC) and theR, G and B signals becomes greater, the display becomesdarker; if the difference in potential is smaller, the elementopens and the LCD become brighter.

– 5 –

1-3. CA3 CIRCUIT DESCRIPTION

1. OutlineThis is the main CA3 power block, and is comprised of thefollowing blocks.Switching controller (IC511)Lens system 3.4 V power output (L5106, Q5104, D5105,C5117)Backlight power output (L5102, Q5101, C5113)LCD system power output (Q5107, T5101)

2. Switching Controller (IC511)This is the basic circuit which is necessary for controlling thepower supply for a PWM-type switching regulator, and is pro-vided with six built-in channels. They are CH5 (lens system3.4 V), CH4 (backlight) and CH3 (LCD system). CH1, CH2and CH6 are not used. Feedback from 3.4 V (D) C (CH5) and+12.4 V (L) power supply output are received, and the PWMduty is varied so that each one is maintained at the correctvoltage setting level. CH4 is feedback from 10 mA power sup-ply output are received, and the PWM duty is varied so thateach one is maintained at the correct voltage setting level.

2-1. Short-circuit protection circuitIf output is short-circuited for the length of time determinedby the condenser which is connected to Pin (18) of IC511, alloutput is turned off. The control signal (P(A) ON, LCD ONand BL ON) are recontrolled to restore output.

3. Lens system 3.4 V Power Output3.4 V (D) C is output for lens. Feedback for the 3.4 V (D) isprovided to the swiching controller (Pin (8) of IC511) so thatPWM control can be carried out.

4. Backlight Power Output10 mA (L) is output. The backlighting turns on when currentflows in the direction from pin (1) to pin (2) of CN531. At thistime, a feedback signal is sent from pin (2) of CN531 to pin(12) of IC511 through R5122 so that PWM control is carriedout to keep the current at a constant level (10 mA).

5. LCD System Power Output12.4 V (L), 15 V (L) and 4 V (L) are output. Feedback for the12.4 V (L) is provided to the switching controller (Pin (28) ofIC511) so that PWM control can be carried out.