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Design Optimization of Multi-Cluster Embedded Systems

for Real-Time Applications

Paul Pop, Petru Eles, Zebo Peng, Viaceslav IzosimovEmbedded Systems Lab (ESLAB)

Linköping University, Sweden

Magnus Hellring, Olof BridalDept. of Electronics and Software

Volvo Technology Corp., Göteborg, Sweden

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...

...

Factory Systems

Heterogeneous Networks

Distributed Heterogeneous System

...

Heterogeneous NetworksMulti-Cluster Systems

...

NoCs

Automotive Electronics

...

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Distributed Safety-Critical Applications

...

...

Gateway

Applications distributed over heterogeneous networks are difficult to... Analyze (guaranteeing timing constraints) Design (partitioning, mapping,

bus access optimization)

Applications distributed over the heterogeneous networks Reduce costs:

use resources efficiently Requirements:

close to sensors/actuators

[DATE’03]

This paper!

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Outline

MotivationSystem architecture and application

model Scheduling for multi-clusters [DATE’03] Design optimization problems

Partitioning Mapping Bus access optimization

Optimization strategy Experimental results Contributions and Message

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S0 S1 S2 SG S0 S1 S2 SG

TDMA RoundCycle of two rounds

Slot

Time Triggered Protocol (TTP) Bus access scheme:

time-division multiple-access (TDMA) Schedule table located in each TTP

controller: message descriptor list (MEDL)

Controller Area Network (CAN) Priority bus, collision avoidance Highest priority message

wins the contention Priorities encoded in the frame

identifier

Hardware Architecture

Gateway

...

...

Time-triggered cluster Static cyclic scheduling Time-triggered protocol

Event-triggered cluster Fixed priority preemptive

scheduling Controller area network protocol

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CPUNG

Out C

AN

TTP Controller

S1SG

Round2

P4P1

CPUN1

TTP ControllerMBI

CPU

MBI

CAN Controller

CPUN2 CAN Controller

T

m1m2m1

S1SG

Out T

TP

T

P2 P3

Out N

2

m3

m3

Software Architecture...

...

Time-triggered cluster

Event-triggered cluster

Gateway

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Multi-Cluster Scheduling [DATE’03]

Application,Partitioning,

Mapping,Architecture

TT Bus Configuration Priorities

ScheduleTables

Responsetimes

StaticSchedulin

gMulti-Cluster Scheduling

Offsets

ResponseTimes Respons

eTime

Analysis

MultiClusterScheduling algorithm Schedulability analysis: communication delays through the gateway Scheduling: cannot be addressed separately for each cluster

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Problem Formulation

Input System architecture Application Partial partitioning and mapping,

based on the designer’s experience

Application: set of process graphs

...

...

Architecture: Multi-cluster

Output Design implementation

such that the application is schedulable Partitioning for each un-partitioned process Mapping for each un-mapped process Priorities for ET messages TDMA slot sequence and sizes for the TT bus Priorities for ET processes Schedule table for TT messages

Partitioning andmappingCommunicationinfrastructureSchedulinginformation

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P4

P5

P3 P6

P2

P1N1

Missed

(faster) N2

(slower) N3

Met

Motivational Example #1

N2 N3

TTC ETCN1

CAN

TTP

P3

P6P5

P4

P2P1

P1P2P3P4

N1 N2

X XX5070

40

90X

P5 X 40

N3

P6

70X

XX

XX 40 X

P4

P5

P3 P6

P2

P1N1

P4

Preempted

(faster) N2

(slower) N3

Met

Met

Preemptionnot allowed

P3

P4 P4

P6

P5P2

P1N1

Preempted

(faster) N2

(slower) N3

MetMet

Deadline for P6

Deadline for P5

In which cluster to place process P4?

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P1N1

P3

TTP S2

N2

S3 SG SG S3 S1 SG

P2

Missed

S2 S3 S1m1

m2

N3

CAN

NG

N4

Motivational Example #2

P1 P3P2

m1

m2 P1P2P3

N1 N2

20 XXX

40X

N4

X50X

N3

XX20

N3 N4

TTC ETCN2

CAN

TTP

N1 NG

Where to map process P2?

Met

P1N1

P3

TTP S2

T

CAN

N4 P2

NG

S2 SG S2 S3 S1 SG

T

S2 S3 S1

N4

N3

m1

m1

m2

m2

N2

Deadline

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Motivational Example #3

P1N1 P4

TTP S1

T

CAN

N2 P2

NG

SG m1 SG S1

T

m2

T

P3

T

S1 SGm4 S1SG m3

Round 4Missed

m1

m3

m2

m4

What are the priorities on ETC? Which slot should come first on the TTC?

P1P2P3P4

N1 N2

20 XXX40

40

X20

P1

P4

P2 P3

m1 m2

m3 m4

N1 N2

TTC

CAN

TTP

ETC

P1N1 P4

TTP S1

T

CAN

N2 P2

NG

SG m1 SG S1

T

m2

T

P3

T

S1 SGSG

Missed

m1

m2

m3

m4

m3 m4

P1N1 P4

TTP SG

T

CAN

N2 P2

NG

S1

T T

P3

S1 SGS1SG m4 m3

Met

Round 1m

2m

1

m4

m3

m1 m2

Deadline

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Optimization Strategy

Multi-Cluster Configuration1. Initial Partitioninig and Mapping

Determines an initial partitioning and mapping List scheduling-based greedy approach

Priority of ready processes: critical path

2. Partitioning and Mapping Heuristic Iteratively improves on the initial partitioning and mapping Intelligent design transformations that improve schedulability

Based on feedback from MultiClusterScheduling

3. Bus Access Optimization Determines the slot sequence and lengths on the TTC,

message priorities on the ETC Greedy optimization heuristic

Straightforward solution Partitioning and mapping that balances the utilization of processors

and buses Could be produced by a designer without optimzation tools

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Experimental Results

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

50 100 150 200 250Perc

enta

ge s

chedula

ble

ap

plic

ati

ons

[%]

Number of processes

Can we increase the number of schedulable applications?

Straightforwardsolution

Bus AccessOptimization

Partitioning andMapping HeuristicInitial Partitioningand Mapping

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Experimental Results, Cont.

How time-consuming is our optimization strategy?

0:000:200:401:001:201:402:002:202:403:003:203:404:004:204:405:005:20

50 100 150 200 250Avera

ge e

xecu

tion t

ime [

hours

:min

ute

s]

Number of processes

Multi-Cluster Configuration

Partitioning and Mapping Heuristic

Initial Partitioningand MappingBus Access Optimization

Case study Vehicle cruise controller Distributed over the

TT and ET clusters

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Contributions and Message

Contributions Addressed design problems characteristic to multi-

clusters Partitioning Mapping Bus Access Optimization

Proposed heuristics for design optimization

Analysis and optimization methods areneeded for the efficient

implementation of applications distributed over interconnected

heterogeneous networks.