1 nV/√Hz Low Noise210°C Instrumentation Amplifier

Data Sheet AD8229

Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.

FEATURES Designed and guaranteed for 210°C operation Low noise

1 nV/√Hz input noise 45 nV/√Hz output noise

High CMRR 126 dB CMRR (minimum), G = 100 80 dB CMRR (minimum) to 5 kHz, G = 1

Excellent ac specifications 15 MHz bandwidth (G = 1) 1.2 MHz bandwidth (G = 100) 22 V/μs slew rate THD: −130 dBc (1 kHz, G = 1)

Versatile ±4 V to ±17 V dual supply Gain set with single resistor (G = 1 to 1000) Specified temperature range

−40°C to +210°C, SBDIP package −40°C to +175°C, SOIC package

APPLICATIONS Down-hole instrumentation Harsh environment data acquisition Exhaust gas measurements Vibration analysis

FUNCTIONAL BLOCK DIAGRAM

TOP VIEW(Not to Scale)

–IN 1

RG 2

RG 3

+IN 4

+VS8

VOUT7

REF6

–VS5

AD8229

0941

2-00

1

Figure 1.

100

80

60

40

20

0

–20

–40

–60

–80

–100

V OSI

(µV)

–55 –35 –15 5 25 45 65 85 105 125 145 165 185 205 225

TEMPERATURE (°C) 0941

2-01

6

Figure 2. Typical Input Offset vs. Temperature (G = 100)

GENERAL DESCRIPTION The AD8229 is an ultralow noise instrumentation amplifier designed for measuring small signals in the presence of large common-mode voltages and high temperatures.

The AD8229 has been designed for high temperature operation. The process is dielectrically isolated to avoid leakage currents at high temperatures. The design architecture was chosen to compensate for the low VBE voltages at high temperatures.

The AD8229 excels at measuring tiny signals. It delivers industry leading 1 nV/√Hz input noise performance. The high CMRR of the AD8229 prevents unwanted signals from corrupting the acquisition. The CMRR increases as the gain increases, offering high rejection when it is most needed.

The AD8229 is one of the fastest instrumentation amplifiers available. Its current feedback architecture provides high

bandwidth at high gain, for example, 1.2 MHz at G = 100. The design includes circuitry to improve settling time after large input voltage transients. The AD8229 was designed for excellent distortion performance, allowing use in demanding applications such as vibration analysis.

Gain is set from 1 to 1000 with a single resistor. A reference pin allows the user to offset the output voltage. This feature can be useful when interfacing with analog-to-digital converters.

For the most demanding applications, the AD8229 is available in an 8-lead side-brazed ceramic dual in-line package (SBDIP). For space-constrained applications, the AD8229 is available in an 8-lead plastic standard small outline package (SOIC).

AD8229 Data Sheet

Rev. B | Page 2 of 24

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 6

Predicted Lifetime vs. Operating Temperature ........................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 17 Architecture ................................................................................ 17 Gain Selection ............................................................................. 17 Reference Terminal .................................................................... 17 Input Voltage Range ................................................................... 18 Layout .......................................................................................... 18 Input Bias Current Return Path ............................................... 19 Input Protection ......................................................................... 19 Radio Frequency Interference (RFI) ........................................ 19 Calculating the Noise of the Input Stage ................................. 20

Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21

REVISION HISTORY 2/12—Rev. A to Rev. B Added 8-Lead SOIC ........................................................... Universal Changes to Features Section and General Description Section...... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2, Thermal Resistance Section, and Table 3 ... 6 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 9/11—Rev. 0 to Rev. A Changes to Features Section and General Description Section...... 1 Changes to Table 2 ............................................................................ 6 Added Predicted Lifetime vs. Operating Temperature Section and Figure 3; Renumbered Sequentially .............................................. 6 Changes to Figure 18 and Figure 19 ............................................. 10 Changes to Figure 24 to Figure 28 ................................................ 11 Changes to Figure 29 and Figure 30 ............................................. 12 Changes to Figure 48 ...................................................................... 15 Changes to Figure 56 ...................................................................... 17 Changes to Power Supplies Section .............................................. 18 1/11—Revision 0: Initial Version

Data Sheet AD8229

Rev. B | Page 3 of 24

SPECIFICATIONS +VS = 15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.

Table 1. Parameter Test Conditions/Comments Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR)

CMRR DC to 60 Hz with 1 kΩ Source Imbalance VCM = ±10 V G = 1 86 dB

Temperature Drift TA = −40°C to +210°C 300 nV/V/°C G = 10 106 dB

Temperature Drift TA = −40°C to +210°C 30 nV/V/°C G = 100 126 dB

Temperature Drift TA = −40°C to +210°C 3 nV/V/°C G = 1000 TA = −40°C to +210°C 134 dB

CMRR at 5 kHz VCM = ±10 V G = 1 80 dB G = 10 90 dB G = 100 90 dB G = 1000 90 dB

VOLTAGE NOISE VIN+, VIN− = 0 V Spectral Density1: 1 kHz

Input Voltage Noise, eni 1 1.1 nV/√Hz Output Voltage Noise, eno 45 50 nV/√Hz

Peak to Peak: 0.1 Hz to 10 Hz G = 1 2 µV p-p G = 1000 100 nV p-p

CURRENT NOISE Spectral Density: 1 kHz 1.5 pA/√Hz Peak to Peak: 0.1 Hz to 10 Hz 100 pA p-p

VOLTAGE OFFSET VOS = VOSI + VOSO/G Input Offset, VOSI 100 µV

Average TC TA = −40°C to +210°C 0.1 1 µV/°C Output Offset, VOSO 1000 µV

Average TC TA = −40°C to +210°C 3 10 µV/°C Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V

G = 1 TA = −40°C to +210°C 86 dB G = 10 TA = −40°C to +210°C 106 dB G = 100 TA = −40°C to +210°C 126 dB G = 1000 TA = −40°C to +210°C 130 dB

INPUT CURRENT Input Bias Current 70 nA

High Temperature TA = 210°C 200 nA Input Offset Current 35 nA

High Temperature TA = 210°C 50 nA

AD8229 Data Sheet

Rev. B | Page 4 of 24

Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC RESPONSE

Small Signal Bandwidth –3 dB G = 1 15 MHz G = 10 4 MHz G = 100 1.2 MHz G = 1000 0.15 MHz

Settling Time 0.01% 10 V step G = 1 0.75 µs G = 10 0.65 µs G = 100 0.85 µs G = 1000 5 µs

Settling Time 0.001% 10 V step G = 1 0.9 µs G = 10 0.9 µs G = 100 1.2 µs G = 1000 7 µs

Slew Rate G = 1 to 100 22 V/µs

THD (FIRST FIVE HARMONICS) f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p G = 1 –130 dBc G = 10 –116 dBc

G = 100 –113 dBc G = 1000 –111 dBc THD + Noise f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p, G = 100 0.0005 %

GAIN2 G = 1 + (6 kΩ/RG) Gain Range 1 1000 V/V Gain Error VOUT = ±10 V

G = 1 0.01 0.03 % G = 10 0.05 0.3 % G = 100 0.05 0.3 % G = 1000 0.1 0.3 %

Gain Nonlinearity VOUT = −10 V to +10 V G = 1 to 1000 RL = 10 kΩ 2 ppm

Gain vs. Temperature G = 1 TA = −40°C to +210°C 2 5 ppm/°C G > 10 TA = −40°C to +210°C −100 ppm/°C

INPUT Impedance (Pin to Ground)3 1.5||3 GΩ||pF Input Operating Voltage Range4 VS = ±5 V to ±18 V for dual supplies −VS + 2.8 +VS − 2.5 V

Over Temperature TA = −40°C to +210°C −VS + 2.8 +VS − 2.5 V OUTPUT

Output Swing, RL = 2 kΩ −VS + 1.9 +VS − 1.5 V High Temperature, SBDIP package TA = 210°C −VS + 1.1 +VS − 1.1 V High Temperature, SOIC package TA = 175°C −VS + 1.2 +VS − 1.1 V

Output Swing, RL = 10 kΩ −VS + 1.8 +VS − 1.2 V High Temperature, SBDIP package TA = 210°C −VS + 1.1 +VS − 1.1 V High Temperature, SOIC package TA = 175°C −VS + 1.2 +VS − 1.1 V

Short-Circuit Current 35 mA

Data Sheet AD8229

Rev. B | Page 5 of 24

Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE INPUT

RIN 10 kΩ IIN VIN+, VIN− = 0 V 70 µA Voltage Range −VS +VS V Reference Gain to Output 1 V/V Reference Gain Error 0.01 %

POWER SUPPLY Operating Range ±4 ±17 V Quiescent Current 6.7 7 mA

High Temperature, SBDIP package TA = 210°C 12 mA High Temperature, SOIC package TA = 175°C 11 mA

TEMPERATURE RANGE For Specified Performance5

SBDIP package −40 +210 °C SOIC package −40 +175 °C

1 Total Voltage Noise = √(eni

2 + (eno/G)2)+ eRG2). See the Theory of Operation section for more information.

2 These specifications do not include the tolerance of the external gain setting resistor, RG. For G>1, RG errors should be added to the specifications given in this table. 3 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 4 Input voltage range of the AD8229 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See

the Input Voltage Range section for more details. 5 For the guaranteed operation time at the maximum specified temperature, refer to the Predicted Lifetime vs. Operating Temperature section.

AD8229 Data Sheet

Rev. B | Page 6 of 24

ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage ±17 V Output Short-Circuit Current Duration Indefinite Maximum Voltage at –IN, +IN1 ±VS Differential Input Voltage1

Gain ≤ 4 ±VS 4 > Gain > 50 ±50 V/gain Gain ≥ 50 ±1 V

Maximum Voltage at REF ±VS Storage Temperature Range −65°C to +150°C Specified Temperature Range

SBDIP −40°C to +210°C SOIC −40°C to +175°C

Maximum Junction Temperature SBDIP 245°C SOIC 200°C

ESD Human Body Model 4 kV Charge Device Model 1.5 kV Machine Model 200 V

1 For voltages beyond these limits, use input protection resistors. See the Theory of Operation section for more information.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PREDICTED LIFETIME VS. OPERATING TEMPERATURE Comprehensive reliability testing is performed on the AD8229. Product lifetimes at extended operating temperature are obtained using high temperature operating life (HTOL). Lifetimes are predicted from the Arrhenius equation, taking into account potential design and manufacturing failure mechanism assump-tions. HTOL is performed to JEDEC JESD22-A108. A minimum of three wafer fab and assembly lots are processed through HTOL at the maximum operating temperature. Comprehensive reliability testing is performed on all Analog Devices, Inc., high temperature (HT) products.

1

100k

10k

1k

100

10

120 210200190180170160150140130

PRED

ICTE

D L

IFET

IME

(Hou

rs)

OPERATING TEMPERATURE (°C) 0941

2-20

0

Figure 3. Predicted Lifetime vs. Operating Temperature

Refer to the AD8229 Predicted Lifetime vs. Operating Temperature document for the most up-to-date reliability data.

THERMAL RESISTANCE θJA is specified for a device in free air using a 4-layer JEDEC printed circuit board (PCB).

Table 3. Package Type θJA Unit 8-Lead SBDIP 100 °C/W 8-Lead SOIC 121 °C/W

ESD CAUTION

Data Sheet AD8229

Rev. B | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TOP VIEW(Not to Scale)

–IN 1

RG 2

RG 3

+IN 4

+VS8

VOUT7

REF6

–VS5

AD8229

0941

2-00

3

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input Terminal. 2, 3 RG Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (6 kΩ/RG). 4 +IN Positive Input Terminal. 5 −VS Negative Power Supply Terminal. 6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output. 7 VOUT Output Terminal. 8 +VS Positive Power Supply Terminal.

AD8229 Data Sheet

Rev. B | Page 8 of 24

TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, VS = ±15, VREF = 0, RL = 2 kΩ, unless otherwise noted.

60

50

40

30

20

10

0–60 –40 –20 200

VOSI ±15V (µV)

HIT

S

40 60

N: 200MEAN: 12.2σ: 8.2

0941

2-00

4

Figure 5. Typical Distribution of Input Offset Voltage

VOSO ±15V (µV)

HIT

S

35

30

20

25

15

5

10

0800–600 –400 –200 0 200 400 600

N: 200MEAN: 0.9σ: 161.2

0941

2-00

5

Figure 6. Typical Distribution of Output Offset Voltage

40

35

30

20

25

15

5

10

0–50 –40 –20 –10–30 100

IBIAS (nA)

HIT

S

20 30

INVERTINGNONINVERTING

N: 200MEAN: –6.1σ: 6.7N: 200MEAN: –10.1σ: 6.9

0941

2-00

6

Figure 7. Typical Distribution of Input Bias Current

IBIAS OFFSET (nA)

HIT

S

N: 201MEAN: 4.0σ: 0.7

60

50

30

40

20

10

00 2 4 6 8

0941

2-00

7

Figure 8. Typical Distribution of Input Offset Current

HIT

S

–40–60 –20 0 20 40 60

20

0

40

60

80

100

120

CMRR G1 (µV/V)

N: 200MEAN: 10.9σ: 3.7

0941

2-00

8

Figure 9. Typical Distribution of Common Mode Rejection, G = 1

HIT

S

0941

2-01

5–60 –40 –20 0 200

5

10

15

20

25

30

35

NINV G ERROR G1 10K ±15V (µV/V)

N: 198MEAN: –9.1σ: 9.9

Figure 10. Typical Distribution of Gain Error, G = 1

Data Sheet AD8229

Rev. B | Page 9 of 24

–3

–2

–1

0

1

2

3

–5 –4 –3 –2 –1 0 1 2 3 4 5

CO

MM

ON

-MO

DE

VOLT

AG

E (V

)

OUTPUT VOLTAGE (V)

G = 1, VS = ±5V 25°C210°C

0941

2-00

9

Figure 11. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, VS = ±5 V; G = 1

–10

–8

–6

–4

–2

0

2

4

6

8

10

–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12

OUTPUT VOLTAGE (V)

CO

MM

ON

-MO

DE

VOLT

AG

E (V

)

G = 1, VS = ±12V 25°C210°C

0941

2-01

0

Figure 12. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, VS = ±12 V; G = 1

–14

–10

–6

–12

–8

–4–2

0246

108

1214

–15 –10 –5 0 5 10 15

OUTPUT VOLTAGE (V)

CO

MM

ON

-MO

DE

VOLT

AG

E (V

)

G = 1, VS = ±15V 25°C210°C

0941

2-01

1

Figure 13. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, VS = ±15 V; G = 1

–3

–2

–1

0

1

2

3

–5 –4 –3 –2 –1 0 1 2 3 4 5

CO

MM

ON

-MO

DE

VOLT

AG

E (V

)

OUTPUT VOLTAGE (V)

G = 100, VS = ±5V25°C210°C

0941

2-01

2

Figure 14. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, VS = ±5 V; G = 100

–10

–8

–6

–4

–2

0

2

4

6

8

10

–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12

OUTPUT VOLTAGE (V)

CO

MM

ON

-MO

DE

VOLT

AG

E (V

)

G = 100, VS = ±12V

25°C210°C

0941

2-01

3

Figure 15. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, VS = ±12 V; G = 100

–14

–10

–6

–12

–8

–4–2

0246

108

1214

–15 –10 –5 0 5 10 15

OUTPUT VOLTAGE (V)

CO

MM

ON

-MO

DE

VOLT

AG

E (V

)

G = 100, VS = ±15V 25°C210°C

0941

2-01

4

Figure 16. Input Common-Mode Voltage vs. Output Voltage,

Dual Supply, VS = ±15 V; G = 100

AD8229 Data Sheet

Rev. B | Page 10 of 24

–12.28V

12.60V

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

0

–14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14

INPU

T B

IAS

CU

RR

ENT

(nA

)

COMMON-MODE VOLTAGE (V) 0941

2-06

8

Figure 17. Input Bias Current vs. Common-Mode Voltage

FREQUENCY (Hz)

0

20

40

60

80

100

120

140

160

1 10 100 1k 10k 100k 1M

0941

2-06

9

POSI

TIVE

PSR

R (d

B)

GAIN = 1

GAIN = 1000

GAIN = 10GAIN = 100

Figure 18. Positive PSRR vs. Frequency

FREQUENCY (Hz)

0

20

40

60

80

100

120

140

NEG

ATIV

EPS

RR

(dB

)

160

1 10 100 1k 10k 100k 1M

0941

2-07

0

GAIN = 1

GAIN = 1000

GAIN = 10GAIN = 100

Figure 19. Negative PSRR vs. Frequency

–30

–20

–10

0

10

20

30

40

50

60

70

100 1k 10k 100k 1M 10M 100M

GA

IN (d

B)

FREQUENCY (Hz)

GAIN = 1

GAIN = 1000

GAIN = 100

GAIN = 10

VS = ±15V

0941

2-01

7

Figure 20. Gain vs. Frequency

0

20

40

60

80

100

120

140

160

1 10 100 1k 10k 100k 1M

CM

RR

(dB

)

FREQUENCY (Hz)

GAIN = 1

GAIN = 1000

GAIN = 10GAIN = 100

BANDWIDTHLIMITED

0941

2-01

8

Figure 21. CMRR vs. Frequency

0

20

40

60

80

100

120

140

160

1 10 100 1k 10k 100k 1M

CM

RR

(dB

)

FREQUENCY (Hz)

GAIN = 1

GAIN = 1000

GAIN = 10GAIN = 100

BANDWIDTHLIMITED

0941

2-01

9

Figure 22. CMRR vs. Frequency, 1 kΩ Source Imbalance

Data Sheet AD8229

Rev. B | Page 11 of 24

0

2

4

6

8

10

12

0 100 200 300 400 500 600 700

CH

AN

GE

IN IN

PUT

OFF

SET

VOLT

AG

E (µ

V)

WARM-UP TIME (s) 0941

2-07

1

Figure 23. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time

–10.0

–7.5

–5.0

–2.5

0

2.5

5.0

7.5

10.0

–200

–150

–100

–50

0

50

100

150

200

–

INPU

T O

FFSE

TC

UR

REN

T(n

A)

INPU

TB

IAS

CU

RR

ENT

(nA

)

TEMPERATURE (°C) 0941

2-07

255 –25 5 35 65 95 125 155 185 215

CURRENTINPUT OFFSET

CURRENTINPUT BIAS

Figure 24. Input Bias Current and Input Offset Current vs. Temperature

–250

–200

–150

–100

–50

0

50

100

150

GA

INER

RO

R(µ

V/V)

0941

2-07

3–55 –25 5 35 65 95 125 155 185 215

TEMPERATURE (°C) Figure 25. Gain Error vs. Temperature, G = 1, Normalized at 25°C

–10

–5

0

5

10

15

20

–55 –25 5 35 65 95 125 155 185 215

CM

RR

(µV/

V)

TEMPERATURE (°C) 0941

2-02

3

Figure 26. CMRR vs. Temperature, G = 1, Normalized at 25°C

0

2

4

6

8

10

12

–55 –25 5 35 65 95 125 155 185 215

SUPP

LYC

UR

REN

T(m

A)

TEMPERATURE (°C) 0941

2-07

4

Figure 27. Supply Current vs. Temperature, G = 1

–50

–40

–30

–20

–10

0

10

20

30

40

50

SHO

RT

CIR

CU

ITC

UR

REN

T(m

A)

ISHORT–

ISHORT+

–55 –25 5 35 65 95 125 155 185 215

TEMPERATURE (°C) 0941

2-07

5

Figure 28. Short-Circuit Current vs. Temperature, G = 1

AD8229 Data Sheet

Rev. B | Page 12 of 24

+SR

–SR

0

5

10

15

20

25

30

SLEW

RATE

(V/μ

s)

–55 –25 5 35 65 95 125 155 185 215

TEMPERATURE (°C) 0941

2-07

6

Figure 29. Slew Rate vs. Temperature, VS = ±15 V, G = 1

+SR

–SR

0

5

10

15

20

25

SLEW

RATE

(V/μ

s)

–55 –25 5 35 65 95 125 155 185 215

TEMPERATURE (°C) 0941

2-07

7

Figure 30. Slew Rate vs. Temperature, VS = ±5 V, G = 1

4 6 8 10 12 14 16 18

INPU

T VO

LTA

GE

(V)

REF

ERR

EDTO

SU

PPLY

VO

LTA

GES

SUPPLY VOLTAGE (±VS)

–55°C –40°C +25°C +85°C+125°C +150°C +210°C +225°C

+VS

–VS

–1.0

–2.0

+1.0

+2.0

+2.5

–0.5

–1.5

–2.5

+1.5

+1.5

0941

2-02

8

Figure 31. Input Voltage Limit vs. Supply Voltage

4 6 8 10 12 14 16 18

OU

TPU

T VO

LTA

GE

SWIN

G (V

)R

EFER

RED

TO S

UPP

LY V

OLT

AG

ES

SUPPLY VOLTAGE (±VS)

–55°C –40°C +25°C +85°C+125°C +150°C +210°C +225°C

+VS

–VS

–0.8

+0.8

+1.6

+2.0

–0.4

–1.2

+1.2

+0.4

0941

2-02

9

Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ

4 6 8 10 12 14 16 18

OU

TPU

T VO

LTA

GE

SWIN

G (V

)R

EFER

RED

TO S

UPP

LY V

OLT

AG

ES

SUPPLY VOLTAGE (±VS)

–55°C –40°C +25°C +85°C+125°C +150°C +210°C +225°C

+VS

–VS

–0.8

+0.8

+1.6

+2.0

–0.4

–1.2

+1.2

+0.4

0941

2-03

0

Figure 33. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ

–15

–10

–5

0

5

10

15

100 1k 10k 100k

OU

TPU

T VO

LTA

GE

SWIN

G (V

)

LOAD (Ω)

–55°C–40°C+25°C+85°C+125°C+150°C+210°C+225°C

VS = ±15V

0941

2-03

1

Figure 34. Output Voltage Swing vs. Load Resistance

Data Sheet AD8229

Rev. B | Page 13 of 24

10μ 100μ 1m 5m

OU

TPU

T VO

LTA

GE

SWIN

G (V

)R

EFER

RED

TO

SU

PPLY

VO

LTA

GES

OUTPUT CURRENT (A)

+VS

–VS

+0.4

–0.4

–0.8

–1.2

+0.8

+1.2

+1.6

–1.6

VS = ±15V

+1.8

–55°C –40°C +25°C +85°C+125°C +150°C +210°C +225°C

0941

2-03

2

Figure 35. Output Voltage Swing vs. Output Current

–10

–8

–6

–4

–2

0

2

4

6

8

10

NO

NLI

NEA

RIT

Y (p

pm/D

IV)

OUTPUT VOLTAGE (V)

GAIN = 109

412-

083–10 –8 –6 –4 –2 0 2 4 6 8 10

Figure 36. Gain Nonlinearity, G = 1, RL = 10 kΩ

–10–10 –8 –6 –4 –2 0 2 4 6 8 10

–8

–6

–4

–2

0

2

4

6

8

10

NO

NLI

NEA

RIT

Y (p

pm/D

IV)

OUTPUT VOLTAGE (V)

GAIN = 1000

0941

2-08

4

Figure 37. Gain Nonlinearity, G = 1000, RL = 10 kΩ

0.1

1

10

100

1000

1 10 100 1k 10k 100k

NO

ISE

(nV/

√Hz)

FREQUENCY (Hz)

GAIN = 1

GAIN = 1000

GAIN = 10

GAIN = 100

0941

2-03

7

Figure 38. Voltage Noise Spectral Density vs. Frequency

1s/DIV

GAIN = 1000, 100nV/DIV

GAIN = 1, 2μV/DIV

0941

2-08

6

Figure 39. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000

123456789

10111213141516

1 10 100 1k 10k 100k

NO

ISE

(pA

/√H

z)

FREQUENCY (Hz) 0941

2-08

7

Figure 40. Current Noise Spectral Density vs. Frequency

AD8229 Data Sheet

Rev. B | Page 14 of 24

50pA/DIV 1s/DIV

0941

2-08

8

Figure 41. 1 Hz to 10 Hz Current Noise

0

5

10

15

20

25

30

100 1k 10k 100k 1M 10M

OU

TPU

T VO

LTA

GE

(V p

-p)

FREQUENCY (Hz)

G = 1

VS = ±15V

VS = ±5V

0941

2-08

9

Figure 42. Large Signal Frequency Response

5V/DIV

0.002%/DIV

750ns TO 0.01%872ns TO 0.001%

TIME (µs)

2µs/DIV

0941

2-09

0

Figure 43. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step,

VS = ±15 V

5V/DIV

2µs/DIV

640ns TO 0.01%896ns TO 0.001%

TIME (µs)

0.002%/DIV

0941

2-09

1

Figure 44. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step,

VS = ±15 V

50m

V/D

IV50

mV/

DIV

1μs/DIV

0941

2-04

8

G = 1

25°C 175°C210°C 225°C

Figure 45. Small Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF

20m

V/D

IV20

mV/

DIV

1μs/DIV

0941

2-04

9

G = 10

25°C 175°C210°C 225°C

Figure 46. Small Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF

Data Sheet AD8229

Rev. B | Page 15 of 24

25°C175°C210°C225°C

G = 100

2µs/DIV20mV/DIV

0941

2-09

4

Figure 47. Small Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF

G = 1000

10µs/DIV20mV/DIV

25°C175°C210°C225°C

0941

2-09

5

Figure 48. Small Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF

G = 1

1µs/DIV50mV/DIV

NO LOADCL = 100pFCL = 147pF

0941

2-09

3

Figure 49. Small Signal Response with Various Capacitive Loads, G = 1, RL = Infinity

0

200

400

600

800

1000

1200

1400

2 4 6 8 10 12 14 16 18 20

SETT

LIN

G T

IME

(ns)

STEP SIZE (V)

SETTLED TO 0.001%

SETTLED TO 0.01%

0941

2-09

2

Figure 50. Settling Time vs. Step Size, G = 1

0.00001

0.0001

0.001

0.01

0.1

1

10 100 1k 10k 100k

AM

PLIT

UD

E (P

erce

ntag

e of

Fun

dam

enta

l)

FREQUENCY (Hz)

NO LOAD2kΩ LOAD600Ω LOAD

G = 1, SECOND HARMONICVOUT = 10V p-p

0941

2-09

6

Figure 51. Second Harmonic Distortion vs. Frequency, G = 1

0.00001

0.0001

0.001

0.01

0.1

1

10 100 1k 10k 100k

AM

PLIT

UD

E (P

erce

ntag

e of

Fun

dam

enta

l)

FREQUENCY (Hz)

NO LOAD2kΩ LOAD600Ω LOAD

G = 1, THIRD HARMONICVOUT = 10V p-p

0941

2-09

7

Figure 52. Third Harmonic Distortion vs. Frequency, G = 1

AD8229 Data Sheet

Rev. B | Page 16 of 24

0.0001

0.001

0.01

0.1

1

10 100 1k 10k 100k

AM

PLIT

UD

E (P

erce

ntag

e of

Fun

dam

enta

l)

FREQUENCY(Hz)

NO LOAD2kΩ LOAD600Ω LOAD

G = 1000, SECOND HARMONICVOUT = 10V p-p

0941

2-09

8

Figure 53. Second Harmonic Distortion vs. Frequency, G = 1000

0.0001

0.001

0.01

0.1

1

10 100 1k 10k 100k

AM

PLIT

UD

E (P

erce

ntag

e of

Fun

dam

enta

l)

FREQUENCY (Hz)

NO LOAD2kΩ LOAD600Ω LOAD

G = 1000, THIRD HARMONICVOUT = 10V p-p

0941

2-09

9

Figure 54. Third Harmonic Distortion vs. Frequency, G = 1000

0.00001

0.0001

0.001

0.01

0.1

1

10 100 1k 10k 100k

THD

(%)

FREQUENCY (Hz)

GAIN = 1

GAIN = 100

VOUT = 10V p-pRL ≥ 2kΩ

GAIN = 10

GAIN = 1000

0941

2-10

0

Figure 55. THD vs. Frequency

Data Sheet AD8229

Rev. B | Page 17 of 24

THEORY OF OPERATION

A3

A1 A2

Q2Q1

C1 C2

+IN–IN

+VS

–VS

+VS

–VS

+VS

–VS

R35kΩ

R45kΩ

R55kΩ

RG–

+VS

–VS

OUTPUT

REF

NODE 1

NODE 2

IBCOMPENSATION

IBCOMPENSATION

RG

VBI I

+VS

–VS

+VS

–VS

R65kΩ

RG+

R23kΩ

R13kΩ

0941

2-05

8

Figure 56. Simplified Schematic

ARCHITECTURE The AD8229 is based on the classic 3-op-amp topology. This topology has two stages: a preamplifier to provide differential amplification followed by a difference amplifier that removes the common-mode voltage and provides additional amplification. Figure 56 shows a simplified schematic of the AD8229.

The first stage works as follows. To keep its two inputs matched, Amplifier A1 must keep the collector of Q1 at a constant voltage. It does this by forcing RG− to be a precise diode drop from –IN. Similarly, A2 forces RG+ to be a constant diode drop from +IN. Therefore, a replica of the differential input voltage is placed across the gain setting resistor, RG. The current that flows through this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs.

The second stage is a G = 1 difference amplifier, composed of Amplifier A3 and the R3 through R6 resistors. This stage removes the common-mode signal from the amplified differential signal.

The transfer function of the AD8229 is

VOUT = G × (VIN+ − VIN−) + VREF

where:

GRG

kΩ61+=

GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8229, which can be calculated by referring to Table 5 or by using the following gain equation:

1kΩ 6−

=G

RG

Table 5. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG (Ω) Calculated Gain 6.04 k 1.993 1.5 k 5.000 665 10.02 316 19.99 121 50.59 60.4 100.34 30.1 200.34 12.1 496.9 6.04 994.4 3.01 1994.355

The AD8229 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8229’s specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal.

RG Power Dissipation

The AD8229 duplicates the differential voltage across its inputs onto the RG resistor. The RG resistor size should be chosen to handle the expected power dissipation.

REFERENCE TERMINAL The output voltage of the AD8229 is developed with respect to the potential on the reference terminal. This is useful when the output signal must be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to level-shift the output so that the AD8229 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V.

AD8229 Data Sheet

Rev. B | Page 18 of 24

For best performance, source impedance to the REF terminal should be kept well below 1 Ω. As shown in Figure 56, the reference terminal, REF, is at one end of a 5 kΩ resistor. Additional impedance at the REF terminal adds to this 5 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be calculated as follows:

2(5 kΩ + RREF)/(10 kΩ + RREF)

Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR.

INCORRECT

V

CORRECT

AD8229

OP1177

+

–

VREF

AD8229REF

0941

2-05

9

Figure 57. Driving the Reference Pin

INPUT VOLTAGE RANGE Figure 11 through Figure 16 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. The 3-op-amp architecture of the AD8229 applies gain in the first stage before removing common-mode voltage with the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 56) experience a combination of a gained signal, a common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited.

LAYOUT To ensure optimum performance of the AD8229 at the PCB level, care must be taken in the design of the board layout. The pins of the AD8229 are arranged in a logical manner to aid in this task.

8

7

6

5

1

2

3

4

–IN

RG

RG

+VS

VOUT

REF

–VS+IN

TOP VIEW(Not to Scale)

AD8229

0941

2-06

0

Figure 58. Pinout Diagram

Common-Mode Rejection Ratio over Frequency

Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR over frequency high, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces.

Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), the component should be chosen so that the parasitic capacitance is as small as possible.

Power Supplies

A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect perfor-mance. See the PSRR performance curves in Figure 18 and Figure 19 for more information.

A 0.1 μF capacitor should be placed as close as possible to each supply pin. As shown in Figure 59, a 10 μF tantalum capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits.

AD8229

+VS

+IN

–IN

LOAD

RG

REF

0.1µF 10µF

0.1µF 10µF

–VS

VOUT

0941

2-06

1

Figure 59. Supply Decoupling, REF, and Output Referred to Local Ground

Reference Pin

The output voltage of the AD8229 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground.

Data Sheet AD8229

Rev. B | Page 19 of 24

INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8229 must have a return path to ground. When using a floating source without a current return path, such as a thermocouple, a current return path should be created, as shown in Figure 60.

THERMOCOUPLE

+VS

REF

–VS

AD8229

CAPACITIVELY COUPLED

+VS

REF

C

C

–VS

AD8229

TRANSFORMER

+VS

REF

–VS

AD8229

INCORRECT

CAPACITIVELY COUPLED

+VS

REF

C

R

R

C

–VS

AD82291fHIGH-PASS = 2πRC

THERMOCOUPLE

+VS

REF

–VS

10MΩ

AD8229

TRANSFORMER

+VS

REF

–VS

AD8229

CORRECT

0941

2-06

2

Figure 60. Creating an Input Bias Current Return Path

INPUT PROTECTION The inputs to the AD8229 should be kept within the ratings stated in the Absolute Maximum Ratings section. If this cannot be done, protection circuitry can be added in front of the AD8229 to limit the current into the inputs to a maximum current, IMAX.

Input Voltages Beyond the Rails

If voltages beyond the rails are expected, use an external resistor in series with each input to limit current during overload conditions. The limiting resistor at the input can be computed from

MAX

SUPPLYINPROTECT I

VVR

|| −≥

Noise-sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used at the inputs to shunt current away from the AD8229 inputs and therefore allow smaller protection resistor values. To ensure current flows primarily through the external protection diodes,

place a small value resistor, such as a 33 Ω, between the diodes and the AD8229.

SIMPLE METHOD LOW NOISE METHOD

+VS

AD8229

RPROTECT

RPROTECT

–VS

IVIN++

–

VIN–+

–

0941

2-06

6

+VS+VS

AD8229

RPROTECT 33Ω

33ΩRPROTECT

–VS

–VS

IVIN+

+

–

VIN–+

–

+VS

–VS

Figure 61. Protection for Voltages Beyond the Rails

Large Differential Input Voltage at High Gain

If large differential voltages at high gain are expected, use an external resistor in series with each input to limit current during overload conditions. The limiting resistor at each input can be computed from

−

−≥ G

MAX

DIFFPROTECT R

IVV

R1||

21

Noise-sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used across the inputs to shunt current away from the AD8229 inputs and therefore allow smaller protection resistor values.

0941

2-06

7

AD8229

RPROTECT

RPROTECT

I

VDIFF

+

–AD8229

RPROTECT

RPROTECT

IVDIFF

+

–

SIMPLE METHOD LOW NOISE METHOD Figure 62. Protection for Large Differential Voltages

IMAX

The maximum current into the AD8229 inputs, IMAX, depends on both time and temperature. At room temperature, the part can withstand a current of 10 mA for at least a day. This time is cumulative over the life of the part. At 210°C, limit current to 2 mA for the same period. The part can withstand 5 mA at 210°C for an hour, cumulative over the life of the part.

RADIO FREQUENCY INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications that have strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 63. The filter limits the input signal bandwidth, according to the following relationship:

)2(π21

CDDIFF CCR

uencyFilterFreq+

=

CCM RC

uencyFilterFreqπ2

1=

where CD ≥ 10 CC.

AD8229 Data Sheet

Rev. B | Page 20 of 24

R

R

AD8229

+VS

+IN

–IN

0.1µF 10µF

10µF0.1µF

REF

VOUT

–VS

RGCD10nF

CC1nF

CC1nF

4.02kΩ

4.02kΩ

0941

2-06

3

Figure 63. RFI Suppression

CD affects the difference signal, and CC affects the common-mode signal. Values of R and CC should be chosen to minimize RFI. A mismatch between R × CC at the positive input and R × CC at the negative input degrades the CMRR of the AD8229. By using a value of CD one magnitude larger than CC, the effect of the mismatch is reduced, and performance is improved.

Resistors add noise; therefore, the resistor and capacitor values chosen depend on the desired tradeoff between noise, input impedance at high frequencies, and RFI immunity. The resistors used for the RFI filter can be the same as those used for input protection.

CALCULATING THE NOISE OF THE INPUT STAGE The total noise of the amplifier front end depends on much more than the 1 nV/√Hz headline specification of this data sheet. There are three main contributors: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier.

In the following calculations, noise is referred to the input (RTI). In other words, everything is calculated as if it appeared at the amplifier input. To calculate the noise referred to the amplifier output (RTO), simply multiple the RTI noise by the gain of the instrumentation amplifier.

R2

RGR1

SENSOR

AD8229

0941

2-06

4

Figure 64. AD8229 with Source Resistance from Sensor and

Protection Resistors

Source Resistance Noise

Any sensor connected to the AD8229 has some output resistance. There may also be resistance placed in series with inputs for protection from either overvoltage or radio frequency interference. This combined resistance is labeled R1 and R2 in Figure 64. Any resistor, no matter how well made, has a minimum level of noise. This noise is proportional to the square root of the resistor value. At room temperature, the value is approximately equal to 4 nV/√Hz × √(resistor value in kΩ).

For example, assuming that the combined sensor and protection resistance on the positive input is 4 kΩ, and on the negative input is 1 kΩ, the total noise from the input resistance is

22 )14()44( = 1664 = 8.9 nV/ Hz

Voltage Noise of the Instrumentation Amplifier

The voltage noise of the instrumentation amplifier is calculated using three parameters: the part input noise, output noise, and the RG resistor noise. It is calculated as follows:

Total Voltage Noise = 222 )()()/( ResistorRofNoiseNoiseInputGNoiseOutput G

For example, for a gain of 100, the gain resistor is 60.4 Ω. Therefore, the voltage noise of the in-amp is

222 )0604.04(1)100/45( = 1.5 nV/√Hz

Current Noise of the Instrumentation Amplifier

Current noise is calculated by multiplying the source resistance by the current noise.

For example, if the R1 source resistance in Figure 64 is 4 kΩ, and the R2 source resistance is 1 k Ω, the total effect from the current noise is calculated as follows:

))5.11()5.14(( 22 = 6.2 nV/√Hz

Total Noise Density Calculation

To determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method.

For example, if the R1 source resistance in Figure 64 is 4 kΩ, the R2 source resistance is 1 k Ω, and the gain of the in-amps is 100, the total noise, referred to input, is

)2.65.19.8 222 = 11.0 nV/√Hz

Data Sheet AD8229

Rev. B | Page 21 of 24

OUTLINE DIMENSIONS

07-0

8-20

10-B

0.054NOM

0.032NOM

0.130 NOM

8 5

1 4

0.3200.3100.300

0.2980.2900.282

0.5280.5200.512

0.3050.3000.295

0.1250.1100.095

0.3100.3000.290

0.1050.0950.085

0.0200.0180.016

0.1050.1000.095

0.0450.0350.025

0.0110.0100.009

0.0110.0100.009

INDEXMARK

SEATINGPLANE

0.175 NOM

Figure 65. 8-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-8-1) Dimensions shown in inches

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AA

0124

07-A

0.25 (0.0098)0.17 (0.0067)

1.27 (0.0500)0.40 (0.0157)

0.50 (0.0196)0.25 (0.0099) 45°

8°0°

1.75 (0.0688)1.35 (0.0532)

SEATINGPLANE

0.25 (0.0098)0.10 (0.0040)

41

8 5

5.00 (0.1968)4.80 (0.1890)

4.00 (0.1574)3.80 (0.1497)

1.27 (0.0500)BSC

6.20 (0.2441)5.80 (0.2284)

0.51 (0.0201)0.31 (0.0122)

COPLANARITY0.10

Figure 66. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD8229HDZ −40°C to +210°C 8-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-8-1 AD8229HRZ −40°C to +175°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8229HRZ-R7 −40°C to +175°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 Z = RoHS Compliant Part.

AD8229 Data Sheet

Rev. B | Page 22 of 24

NOTES

Data Sheet AD8229

Rev. B | Page 23 of 24

NOTES

AD8229 Data Sheet

Rev. B | Page 24 of 24

NOTES

©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09412-0-2/12(B)