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L24:Crosstalk-ConcernedPhysical Design

1999. 10 Jun Dong Cho

Sungkyunkwan Univ. Dept. ECEE-Mail : Jdcho@skku.ac.kr

Homepage : vada.skku.ac.kr

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Agenda Characteristics of Crosstalk

Basic Approaches in Crosstalk Avoidance

Recent Approaches in Crosstalk Avoidance Routing

Conclusion

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Characteristics of Crosstalk Introduction Trends on Crosstalk Problem What is Crosstalk in Signal Line? Special Requirement for Crosstalk Avoidance Crosstalk Avoidance in Low Power Design Issues for Noise Algorithmic Approaches Crosstalk Avoidance

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Introduction The state-of-the-art in digital integrated circuit is rapidly

approaching a point where conventional device signal models are no longer effective in predicting the behavior of ICs. The challenge of maintaining signal integrity is present in designs implemented in deep sub-micron technology that operates at speeds quickly approaching 1GHz and above.

Smaller devices, more condensed geometry and smaller signal swing are used to achieve this high-speed performance.This high-speed approach has yielded a higher noise-coupling rate and a lower noise margin as the side effects. Consequently, signal integrity and interconnect modeling have become more critical than ever.

In the scaling from 1.8 um to 0.9 um pitch, line-to-line capacitance increases from 46% to 68% of full-loaded self capacitance

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Trends on Crosstalk Problem Crosstalk is a well-known phenomenon at all levels of electronic packaging from

system level cables through wires on printed circuit board ,multi-chip-modules to chip level routing and inside of VLSI interconnection.

Crosstalk causes undesired signal noise to be coupled from an active line (Aggressor) into a quiet line (Victim). Depending on its magnitude, the induced noise onto the victim may influence the timing behavior of the victim signal by increasing its setup time. It may even cause failure by inducing false pulses or causing false signal levels which may be propagated through the circuit.

With increasing integration density and reduced cycle times, these effects become more visible and more destructive, so they need to be handled more carefully. Crosstalk needs to be considered in particular on VLSI chips with sub-micron structures and today’s large die size.

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What is Crosstalk in Signal Line? Crosstalk is a capa

citive and inductive interference caused by the noise voltage developed on signal lines when nearby lines change state

aggressor

victim

Li

Lm

Ci

CmRout

LiCiRout

V victim

V aggressor

coupled noise

time

time

(a) (b)

It is a function of the separation between signal lines, the linear distance that signals lines run parallel with each other. The faster edge rates of today's logic devices greatly increase the possibility of coupling or crosstalk between signals. To maximize speed, crosstalk must be reduced to levels where no extra time is required for the signal to stabilize. Signals such as clocks, that are highly sensitive to crosstalk should be isolated by reference planes from signals on other layers and/or by extrawide line-to-line spacing.

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Special Requirement for Crosstalk Avoidance

Data buses : Crosstalk between buses tends to be data-patterns-sensitive and it is worse when all addresses or data lines change in the same direction at the same time. Signals common to a given bus can run next to other signals in the bus, but not with other buses or signals.

Memory address and data signals : A data-to-address-line cross-coupling may upset address lines sufficiently to cause write signals to incorrect memory locations. Therefore, high-speed memory address and data signals need to be isolated by reference planes and by extra-wide line-to-line spacing from other signals, particularly other memory chip-selects, address line, and data buses.

Clock signals and Strobes : To meet crosstalk limits, clock signals must be isolated and confined between reference layers. Other signals must not be mixed with clocks. Clock signals on a given layer must have extra spacing between lines. Clock signals of different frequencies must have extra-wide spacing, as clock signals and other signals if they are to be mixed.

ECL and analog : ECL and analog signals require a high degree of isolation from TTL-level or CMOS-level signals. They must be physically isolated in separate board areas with separate ground and voltage planes that are isolated from TTL or CMOS switching currents.

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Crosstalk Avoidance in Low Power The average dynamic power consumed by a CMOS gate is given below, where i

s the load capacity at the output of the node, is the supply voltage, is the global clock period, N is the number of transitions of the gate output per clock cycle, is the load capacity due to input capacitance of fanout gates, and is the load capacity due to the interconnection tree formed between the driver and its fanout gates.

lC ddVcycleT

gC

wC

2 2

0.5 0.5 ( )dd ddav l g w

cycle cycle

V VP C N C C N

T T

Logic synthesis for low power attempts to minimize ,whereas physical design for low power tries to minimize . Here consists of two terms , where is the capacitance of net i due to its crosstalk, and

is the substrate capacitance of net i. For low power layout applications, power dissipation due to crosstalk is minimized by ensuring that wires carrying high activity signals are placed sufficiently far from the other wires. Similarly, power dissipation due to substrate capacitance is proportional to the wire length and its signal activity. In this paper, we aim to minimize .

ig ii

C Niw i

i

C N iwC

i ix sC Cix

C

isC

i ix sC C

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Multi-layer of Lines Cross-coupling is very significant From above, below, left, or right If left and right adjacent lines are transitioning at the same time that the signal of interest transitions, we have an increased loading effect (referred to as Miller multiplication) Ctotal = Cdown + Cup + 2 Cleft + 2 Cright Tdelay = 2.3 R0 (Cline+Cload) + Rline Cline +2.3 Rline Cload

Gate delay is decreasing with dimensional scaling

Ctotal = Cdown+Cup + Cleft + Cright

Cleft Cright

Cdown

Cup

RC delay is increasing with dimensional scaling

RC delay in long lines is proportional to L square

For lines longer than “L” Vnoise = (CLL/Ctotal) Vdd, CLL is total

simultaneous switching coupling capacitance

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Design Issues for Noise Reduce coupling noise Increase driver strength Increase spacing between wires or route signal lines

alternately with power or ground. Constraint-driven routing Reducing power supply noise Ensure that power grid is sized correctly for the load it is

serving to reduce IR drop Add on-chip decoupling capacitance to reduce delta-I noise.

With increasing use of dynamic circuits, there is less NWELL capacitance on-chip.

When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network

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Approaches to Crosstalk Avoidance

Analysis Efficient mode for filtering and driver for physical design Mixture of static/ dynamic analysis tools needed

Interconnect Planning Present routing methodology increasingly inadequate Mixture of planning & constrained synthesis needed Efficient Noise metrics Noise avoidance routing Clocking - managing skew, interconnect vs. device variability Buffer Insertion - needs to better integrated into design methodology Use of design guidelines necessary in practice

Noise/ SI problems are difficult and pervasive, but are TRACTABLE!!!

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Noise Avoidance

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Interference Graph

Node: nets/segments of nets

Undirected Edges: horizontal constraint

Directed Edges: Vertical Constraints

Edge Weights: Design Rules, Coupling Rules

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Transistor Sizing X is the set (vector) of transistor sizes Minimize Area(X) subject to Delay(X) <= Tspec Minimize Power(X) subject to Delay(X) <= Tspec

x

A

B

C

D

E

Problem with interacting paths

(1) Better to size A than to size all of B,C and D

(2) If X-E is near-critical and A-D is critical,

size A (not D)

circuit designed- wellain power totalof 20%-10 than Less

n time transitio ctance,transcondu

,P f )2(V 12/

P C

T2

dd

T2

L

Tcktshort

dddynamic

VP

fVP

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Basic Approaches in Crosstalk Avoidance

Segregation / Spacing / Ground Shielding

Net Ordering

Layer Assignment

Pattern Routing

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Segregation / Spacing / Ground Shielding (1)

Noisy Region

Quiet Region

Segregation Spacing

Extra space

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Segregation / Spacing/ Ground Shielding (2)

Segregation : Dividing many (noisy) and less(quiet) signal transition wire and merging group by group.(use with shielding)

Spacing : the method that signal wire to shun each other, when signal net is close to each other (routing channel is not wide)

Shielding : blocking signal line with ground line to minimize signal interference to the other wire.(ground bounce occurs and must broaden the ground line) Shielding

Grounded Shields

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Net Ordering

Left : Unordered track permutation

Right : Ordered track permutation for minimizing crosstalk

SS

SS

LL

LL

LL

SS

SS

LL

LL

LL

Net ordering is used for minimize crosstalk-critical region between each lines. When, long line and long line is close together, crosstalk between them is more larger than long line and short line. So, we must change the permutation of track for minimizing crosstalk.

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Layer Assignment

Ordered netLayer1

Unodered net

Layer2Layer3

When using more than 3 layer in channel routing, adjacent signal wire in same layer results crosstalk. For example, left figure makes more crosstalk than right.

Layer assignment problem is solved by integer linear programming or dynamic programming method.

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Pattern Routing In global routing, global interconnection wires have more long and thick wire than l

ocal interconnection wire. Pattern routing method

Make wire pattern satisfying design specification. Choose corresponding wire pattern. Minimize total crosstalk.

Q 1Q 2

Q 3 Q 4