1 ku college of engineering elec 204: digital systems design lecture 17 design a clock synchronous...

KU College of EngineeringElec 204: Digital Systems DesignLecture 17 1

• Design a clock synchronous sequential circuit with two inputs A, B and a single output Z that is 1 if:– A had the same value at each of the two previous

clock ticks, or

– B has been 1 since the last time that the first condition was true.

– Otherwise, output should be 0.

State Assignment Example


• State definitions:– INIT: initial state

– A0: A had 10 but not 00 on the previous clock ticks.

– A1: A had 01 but not 11 on the previous clock ticks.

– OK0: A had 00, or when OK B=1 and last A=0

– OK1: A had 11, or when OK B=1 and last A=1

State Assignment Example (cont.)

A: 0 1 0 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0B: 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0Z: 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 0


How to choose the best state assignment?• Formal way: try all assignments!

– To much work, not practical.• Guidelines for reasonable state assignments:

– Choose an initial state into which the machine can easily be forced at reset (00…0 or 11…1).

– Minimize the number of state variables that change on each transition.– Maximize the number of state variables that don’t change in a group of

related states.– Exploit symmetries in the problem specifications.– Don’t limit the choice of coded states to the first m n-bit integers.– Decompose the set of state variables into individual bits or fields, where

each bit or field has a well-defined meaning wrt the input effects or output behavior.

– Consider using more than the minimum number of state variables to make, a decomposed assignment, possible.


Ex: Decomposed State Assignment

State Q1Q2Q3

INIT 000

A0 100

A1 101

OK0 110

OK1 111

•Easy to force reset state•When Q1=1

•Q2 indicates an OK state•Q3 indicates the previousvalue of A


Ex: One-hot State AssignmentState Q1—Q5 Q1—Q4

(almost one-hot)

INIT 00001 0000

A0 00010 0001

A1 00100 0010

OK0 01000 0100

OK1 10000 1000

•One bit to each state•Simple structure•Requires more thanminimum number ofFFs.


Note on unused states

• Minimal Risk:– Consider getting one of the unused (or illegal) states (can be

hardware failure, design error, etc).– Identify unused states, create next-state transitions to initial, idle or

a safe state.

• Minimal Cost:– Assumes the machine never enters to the unused states.– In the next-state table unused states can be marked as don’t cares.– Simplifies excitation logic, but may create problems.


State Minimization

• Should minimize the cost of the final sequential clocked circuit (scct) either by– Reducing the number of gates, or

– Reducing the number of FFs

• One possible way for this minimization is – Elimination of equivalent states.

• Equivalent states:– If it is impossible to distinguish them by observing the

current and future outputs of the machine.


• E G

• F D

Present State

Next State

X=0 X=1

Output

X=0 X=1

A A B 0 0

B C D 0 0

C A D 0 0

D E F 0 1

E A F 0 1

F G F 0 1

G A F 0 1

• Example on equivalent states:

Present State

Next State

X=0 X=1

Output

X=0 X=1

A A B 0 0

B C D 0 0

C A D 0 0

D E D 0 1

E A D 0 1


Other Flip-Flop Types

• J-K and T flip-flops– Behavior

– Implementation

• Basic descriptors for understanding and using different flip-flop types– Characteristic tables

– Characteristic equations

– Excitation tables

• For actual use, see Reading Supplement - Design and Analysis Using J-K and T Flip-Flops


J-K Flip-flop

• Behavior– Same as S-R flip-flop with J analogous to S and K analogous to R

– Except that J = K = 1 is allowed, and

– For J = K = 1, the flip-flop changes to the opposite state

– As a master-slave, has same “1s catching” behavior as S-R flip-flop

– If the master changes to the wrong state, that state will be passed to the slave

• E.g., if master falsely set by J = 1, K = 1 cannot reset it during the current clock cycle


J-K Flip-flop (continued)• Implementation

– To avoid 1s catchingbehavior, one solutionused is to use anedge-triggered D asthe core of the flip-flop

Symbol

D

CK

J

J

C

K


T Flip-flop

• Behavior– Has a single input T

• For T = 0, no change to state

• For T = 1, changes to opposite state

• Same as a J-K flip-flop with J = K = T

• As a master-slave, has same “1s catching” behavior as J-K flip-flop

• Cannot be initialized to a known state using the T input– Reset (asynchronous or synchronous) essential


T Flip-flop (continued)• Implementation

– To avoid 1s catchingbehavior, one solutionused is to use anedge-triggered D asthe core of the flip-flop

Symbol

C

DT

T

C


Basic Flip-Flop Descriptors

• Used in analysis– Characteristic table - defines the next state of the flip-

flop in terms of flip-flop inputs and current state

– Characteristic equation - defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and the current state

• Used in design– Excitation table - defines the flip-flop input variable

values as function of the current state and next state


D Flip-Flop Descriptors

• Characteristic Table

• Characteristic EquationQ(t+1) = D

• Excitation Table

D

01

Operation

ResetSet

01

Q(t 1)+

Q(t+1)

01

01

D Operation

ResetSet


T Flip-Flop Descriptors

• Characteristic Table

• Characteristic EquationQ(t+1) = T Q


No change

Complement

Operation

0

1

T Q(t 1)

Q(t)

Q(t)

+

Q(t+1)

Q(t)

1

0

T

No change

Complement

Operation

Q(t)


S-R Flip-Flop Descriptors• Characteristic Table

• Characteristic EquationQ(t+1) = S + R Q, S.R = 0


00

1

1

OperationS

01

0

1

R

No changeReset

Set

Undefined

0

1

?

Q(t+1)

Q(t)

Operation

No changeSet

Reset

No change

S

X

01

0

Q(t+ 1)

01

1

0

Q(t)

00

1

1

R

X0

1

0


J-K Flip-Flop Descriptors• Characteristic Table

• Characteristic EquationQ(t+1) = J Q + K Q


0011

No change

SetReset

Complement

OperationJ

0101

K

01

Q(t +1)

Q(t)

Q(t)

Q(t+1)

01

10

Q(t)

00

11

Operation

XX

01

K

01

XX

J

No changeSetResetNo Change


Flip-flop Behavior Example• Use the characteristic tables to find the output waveforms for the flip-

flops shown:

T

C

Clock

D,T

QD

QT

D

C


Flip-Flop Behavior Example (continued)

• Use the characteristic tables to find the output waveforms for the flip-flops shown:

JC

K

SCR

Clock

S,J

QSR

QJK

R,K

?

1 ku college of engineering elec 204: digital systems design lecture 17 design a clock synchronous...

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