1

Interrupts, ResetsInterrupts, Resets

Today:• First Hour: Interrupts

–Section 5.2 of Huang’s Textbook

– In-class Activity #1

• Second Hour: More Interrupts

• Section 5.2 of Huang’s Textbook

– In-class Activity #2

2

Example TaskExample TaskRead the output of the 4-bit data source every time the push

button is pressed, and display the result.Read the output of the 4-bit data source every time the push

button is pressed, and display the result.

4-bit Data

Source

Push Button

Computer(HC11 chip)

Display

3

One Method...One Method...4-bit Data

Source

Push Button

Computer(HC11 chip)

Display

START

BUTTON PRESSED?

1 ms delay

BUTTON PRESSED?

READ 4-BIT INPUTUPDATE DISPLAY

NO

NO

YES

YES

Why do we have this?Software switch debouncing

Why do we have this?Software switch debouncing

This style of computerinput/output is called

Polled I/OPolled I/Obecause we’re constantly

polling the pushbutton

This style of computerinput/output is called

Polled I/OPolled I/Obecause we’re constantly

polling the pushbutton

4

Is Is PollingPolling Bad? Bad?• Eats up a lot of CPU cycles doing nothing!

–We’re repeatedly checking the button

–Each time the button is pressed, we delay by 1 ms by going around in a loop, wasting time

– This is also called “busy wait”

• We could do better if only we could somehow grab the CPU’s grab the CPU’s attentionattention momentarily whenever the button is pressed!

• We could do even better if the 1 ms delay could be achieved without a delay loop!

5

Introducing InterruptsIntroducing Interrupts

A mechanism to interrupt the CPU,i.e., steal it for a little while to

service the interrupting device (a button in our example)

A mechanism to interrupt the CPU,i.e., steal it for a little while to

service the interrupting device (a button in our example)

6

Why are Interrupts Important?Why are Interrupts Important?

They allow multiple processes to run on a computer

They allow the CPU to be shared, greatly extending its ability

For example, the CPU can be doing something else when “waiting” for the button to be pressed

They allow multiple processes to run on a computer

They allow the CPU to be shared, greatly extending its ability

For example, the CPU can be doing something else when “waiting” for the button to be pressed

7

Interrupt MethodInterrupt Method

START

INITIALIZE

DO SOMETHING

USEFUL

useful or otherwise....

4-bit Data

Source

Push Button

Computer(HC11 chip)

Display

Suppose that the computer is doing something...Suppose that the computer is doing something...

DO SOMETHING

USEFUL

KeyPressed

8

Interrupt MethodInterrupt Method

STARTINTERRUPT SERVICE

ROUTINE

READ THE 4-BIT INPUTUPDATE THE DISPLAY

RETURNFROM

INTERRUPT

START

INITIALIZE

DO SOMETHING

USEFUL

KeyPressed

The CPU is temporarily interrupted. An Interrupt Service Routine is entered

The CPU is temporarily interrupted. An Interrupt Service Routine is entered

The CPU now resumes where it left off!The CPU now resumes where it left off!

STARTINTERRUPT SERVICE

ROUTINE

READ THE 4-BIT INPUTUPDATE THE DISPLAY

RETURNFROM

INTERRUPT

DO SOMETHING

USEFUL

9

Interrupts are Interrupts are TransparentTransparent

The program that was interrupted does not have a clue that it was interrupted!!

Interrupt Service Routines need to leave registers untouched

Interrupt Service Routines need to be extremely short and quick

WHY??

The program that was interrupted does not have a clue that it was interrupted!!

Interrupt Service Routines need to leave registers untouched

Interrupt Service Routines need to be extremely short and quick

WHY??

10

Interrupts vs. SubroutinesInterrupts vs. Subroutines

Interrupt Service routines may look a bit like subroutines, but they are very different.

Subroutines are not transparent. The calling routine is aware of the subroutine call.

Interrupt Service Routines are initiated by hardware, with some exceptions (e.g., SWI).

The CPU hardware automatically saves and restores all registers.

With subroutines, the programmer has to write code for saving and restoring. In general, not all registers are saved.

11

Interrupt SourcesInterrupt Sources

Hardware SourcesHardware SourcesExternal PushbuttonsTimersSerial Communication Systems...

Software SourcesSoftware SourcesSWI instruction

Interrupts can come from several sourcesInterrupts can come from several sources

12

Interrupt PriorityInterrupt Priority

For example, sources requiring a more timely response get higher priority.

At 9600 bits/sec, the RS-232 port on your PC produces an interrupt about once every 2000 CPU cycles.

The 68HC11 timer produces an interrupt once every 216 CPU cycles.

The timer has higher priority in this case.The timer has higher priority in this case.

Different Sources can have different prioritiesDifferent Sources can have different priorities

13

Do Activity #1 NowDo Activity #1 Now

14

What is an interrupt?

• A special event that requires the CPU to stop normal program execution and perform some service related to the event. E.g.: I/O completion, timer time-out, illegal opcodes, arithmetic overflow, divide-by-0 etc.

Functions of Interrupts:- Coordinating I/O activities and preventing CPU from being tied up- Providing a graceful way to exit from errors- Reminding the CPU to perform routine tasks

Interrupts: RecapInterrupts: Recap

15

Why do we need to use masking and priority to manage interrupts ?

Interrupt Maskability:- Interrupts that can be ignored by the CPU are called maskable interrupts. • A maskable interrupt must be enabled before it can interrupt the CPU. • An interrupt is enabled by setting an enable flag.• Interrupts that can’t be ignored by the CPU are called non-maskable interrupts.

Interrupt priority:- The order in which the CPU will service interrupts when all of them occur at the same time.

Managing InterruptsManaging Interrupts

16

68HC11 Interrupts68HC11 Interrupts

SCI serial systemSPI serial transferPulse accumulator input edgePulse accumulator overflowReal time interruptIRQ pinXIRQ pin

Timer overflowTimer output compare 5Timer output compare 4Timer output compare 3Timer output compare 2Timer output compare 1Timer input capture 3Timer input capture 2Timer input capture 1

The 68HC11 supports 16 hardware interrupts and two software interrupts. Hardware Interrupts

Software interrupts:

SWI instruction, and illegal opcode interrupt. Both are nonmaskable.

17

Who is it??Who is it??

• When an interrupt request is detected by the CPU, it needs a way to find out the source of the interrupt.

• One approach: Polling

• Better approach: Vectored interrupts

• Interrupt Vector: The starting address of the interrupt service routine (ISR), stored in a standard location.

18

Vector address Interrupt source Priority

FFC0, C1...FFD4, D5FFD6, D7FFD8, D9FFDA, DBFFDC, DDFFDE, DFFFE0, E1FFE2, E3FFE4, E5FFE6, E7FFE8, E9FFEA, EBFFEC, EDFFEE, EFFFF0, F1FFF2, F3FFF4, F5FFF6, F7FFF8, F9FFFA, FBFFFC, FDFFFE, FF

reserved...reservedSCI serial systemSPI serial transfer completepulse accumulator input edgepulse accumulator overflow

timer overflowtimer output compare 5timer output compare 4timer output compare 3timer output compare 2timer output compare 1timer input capture 3timer input capture 2timer input capture 1real timer interruptIRQ pin interruptXIRQ pin interrupt

SWIillegal opcode trapCOP failureCOP clock monitor fail

RESET

lowest

highest

Eg: 6811 Int. Vector Address & PriorityEg: 6811 Int. Vector Address & Priority

Whenever timer overflows, the

CPU executes the ISR starting at address stored

here.

19

Interrupt Service Routine (ISR): • Piece of code which handles the interrupt

Interrupt Vector:• Starting address of the interrupt service routine

Interrupt Vector Table:• A table where all interrupt vectors are stored. • Similar to I/O Jump Table

Implementing InterruptsImplementing Interrupts

ISR CodeISR Code

ISR Address ISR Address

Jump to ISR

Interrupt

Vector

Address

20

Interrupt Service Cycle Interrupt Service Cycle 1. Saving the program counter value in the stack

2. Saving the CPU status (including the CCR register and some other registers) in the stack

3. Identifying the cause of interrupt

4. Resolving the starting address of the corresponding interrupt service routine through the Interrupt Vector Table

5. Executing the interrupt service routine (ISR)

6. Restoring the CPU status and the program counter from the stack

7. Restarting the interrupted program

21

Do Activity #2 NowDo Activity #2 NowDue: End of Class Today.

RETAIN THE LAST PAGE(S) (#3 onwards)!!

For Next Class:• Bring Huang Textbook, & HC11 PRG

• Required Reading:– Sec 4.1-4.7 of Huang

• This reading is necessary for getting points in the Studio Activity!