1 interrupts input/output organization: interrupts cs 147 joko sutomo
Post on 21-Dec-2015
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TRANSCRIPT
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Why we need Why we need Interrupts?Interrupts?
Input/output devices are slower than memory and CPU.
Different device requires different amount of time from CPU.
Uncertainty of when device will be ready.
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Continuously checking the status of a peripheral; e.g. read data from an input keyboard.
Polling is relatively straightforward in design and programming with the sacrifice of system performance.
PollingPolling
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Wait StatesWait States If a device assert wait signal, the
CPU:
stays in wait states
outputting the address of I/O device
outputting value of control signal.
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Data Transfer With Data Transfer With InterruptInterrupt
1) When a peripheral is ready it sends an interrupt signal the the CPU
2) The CPU stops execution of the program
3) Accepts data from peripheral
4) Returns to the interrupted program
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Types of InterruptsTypes of Interrupts
There are three types of interrupts, each with several different uses:
External Interrupts Internal Interrupts Software Interrupts
Procedures for processing all types of interrupts are almost identical
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External InterruptsExternal Interrupts Used by CPU to interact with
input/output devices; e.g. the CPU requests a data transfer and
in input device asserts an interrupt when it is ready.
Improve system performance by allowing the CPU to execute instructions.
Also used to initiate transfers.
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Internal InterruptsInternal Interrupts
Occurs entirely within the CPU Used to handle exception that
occur during the execution of valid instructions; e.g:
Divide by zero exception Arithmetic overflow Page faults Invalid instruction codes
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Software InterruptsSoftware Interrupts
Generated by specific interrupt instructions in the CPU’s instruction set.
These interrupt act like subrutine call statements except they always go to a specific address.
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Processing Processing InterruptsInterrupts
These events only occur if the interrupt is enabled.
A handler (software to service the interrupt) is executed.
CPU returns to where it left off in the main program.
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ClassificationClassification Maskable Interrupt
Can be ignored by the CPU
Non-maskable Interrupt Cannot be disabled, always
handled. CPU responds immediately Highest priority among interrupts
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HandlerHandler
Handler is essentially a subroutine.
There may be one handler routine for each interrupt or one unified handler routine for all interrupts.
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HandlerHandler (cont.)
If handler routine is interrupted part way through: Save the contents of internal
registers of the CPU Save the state information within
Control Unit
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HandlerHandler (cont.)
To illustrate, consider this execute routine for the LDAC instruction for the Relatively Simple CPU
LDAC1: DR M, PCPC+1, ARAR+1LDAC2: TR DR, DR M, PCPC+1LDAC3: AR DR, TRLDAC4: DR MLDAC5: AC DR
HandlerHandler (cont.)
When the CPU accesses the handler routine, the following steps are performed:
• CPU pushes the current value of the program counter (PC) onto stack
•CPU loads the address of the handler routine into the PC.
•The handler routine then performs its tasks.
When it finished, it returns to the correct location by popping the value of the PC off the stack
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Getting the Address of Getting the Address of the Handler Routinethe Handler Routine
Vectored Interrupts
Non-vectored Interrupts
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Vectored InterruptsVectored Interrupts
Vectored interrupts supply the CPU with information, the interrupt vector, which is used to generate the address of the handler routine for the interrupt.
Useful for CPUs that receive interrupt request from several devices via the same control line.
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Non-Vectored InterruptsNon-Vectored Interrupts
A non-vectored interrupt uses a handler routine at a known address.
CPU does not need any additional information to generate this address and access its handler routine.
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For Non-vectored Interrupt For Non-vectored Interrupt Request:Request:
An external device sends an interrupt to the CPU by asserting its IRQ signal.
When CPU is ready, it asserts its interrupt acknowledge signal (IACK),
The device sets IRQ low, which cause CPU to set IACK low.
Handler routine proceeds and starts transferring data.
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For Vectored Interrupt Request:For Vectored Interrupt Request:
External device sends interrupt to the CPU by asserting its IRQ signal.
CPU inputs an interrupt vector from the device and call an interrupt service routine (handler)
The device sets IRQ low Handler routine proceeds and starts
transferring data.
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Prioritizing Multiple Prioritizing Multiple InterruptsInterrupts
Extension of the nonvectored interrupt hardware
Daisy chaining
Parallel priority
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Extension of the nonvectored Extension of the nonvectored InterruptInterrupt
Hardware for multiple nonvectored interrupts
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Priority of MultiplePriority of Multiplenonvectored Interruptsnonvectored Interrupts
IRQn has the highest priority and IRQ0 has the lowest. E.g. IRQ 7 Has higher priority than IRQ
5.
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Extension of the nonvectored Extension of the nonvectored Interrupt:Interrupt:
Implementation Issues This method works well when
there are only a few IRQ/IACK pairs.
Number of pins needed by CPU to accommodate signals become prohibitive.
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Daisy Chaining:Daisy Chaining:Implementation IssuesImplementation Issues
Advantages: Straightforward and easy to
implement.
Disadvantages: Configuration is sequential, thus
may introduces hardware delays as chain becomes longer.
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Handling Multiple Interrupt:Handling Multiple Interrupt:
Parallel Priority
Uses priority encoder. Unlike daisy chaining, IACK
signal simply enables a priority encoder.
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Parallel PriorityParallel Priority Advantage:
All interrupt requests require the same amount of time.
Priority of the device does not determine the time needed to acknowledge the interrupt.
Disadvantage: The system is much more difficult to
expand than the daisy chain configuration.