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Glitches/Hazards and ALUsGlitches/Hazards and ALUs

Today:

• First Hour: Glitches and HazardsGlitches and Hazards–Section 3.4 of Katz’s Textbook

– In-class Activity #1

• Second Hour: ALU• Section 5.3 of Katz’s Textbook

– In-class Activity #2

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What are Glitches?What are Glitches?

• Glitches are a kind of logic noise

• They are unwanted transients that occur in otherwise steady-state waveforms

• They are caused by propagation delays and timing defects in combinational logic circuits

• Hence, they are called 'glitches' taken from the German word "Glitsche" meaning slip or error.

• “Hazard” = potential glitch in a circuit

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Kinds of HazardsKinds of Hazards• Static Hazards–A glitch that occurs in a logically steady-state 0 or 1

output when a single input changes–A single input has a delay asymmetry in path to output»Static1-hazard (also called SOP hazard)»Static 0-hazard (also called POS hazard)

• Dynamic Hazards–Multiple transition glitches that occur in a multilevel

circuit–A single input has 3 or more delay asymmetries in path

to output• Function Hazards–A glitch that occurs when 2 or more inputs to a gate

change at (almost) the same time

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Glitch Related DefinitionsGlitch Related Definitions• Coupled Variable– is complemented in one term of the output

expression and uncomplemented in another• Coupled Term– has only one coupled variable

• Residue– is that part of a coupled term that remains after

removing the coupled variable• Hazard Cover (or Consensus term)– is the Redundant Prime Implicant (RPI)

required to eliminate the static hazard

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Example of DefinitionsExample of Definitions

• X is the coupled (complemented) variable

• X Y and X' Z or (X + Y) and (X' + Z) are coupled terms

• Y and Z are residues

and

• Y ZSOP or (Y + Z)POS is the Redundant Prime Implicant (RPI)

Consensus Theorem Forms

ZYZXYXZXYX

YZZXXYZXXY

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Static Hazard DetectionStatic Hazard Detection

00 01 11 10

0 0 1 0 0

1 0 1 1 1

ABC

SOP Hazard:

Coupled variable = A

Coupled terms = A' B, A C

Residues = B, C

RPI = B C, hazard cover X = A' B + A C + B CWhen input of X changes, a glitch occurs because the circuit needs to switch over to a new prime implicant.

Example: X = A' B + A C = (A' + C)(A + B)Example: X = A' B + A C = (A' + C)(A + B)

A B C A' B C

1 1 1 0 1 1

A B C A' B C

1 1 1 0 1 1

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Static Hazard DetectionStatic Hazard Detection

00 01 11 10

0 0 1 0 0

1 0 1 1 1

ABC

POS Hazard:

Coupled variable = A

Coupled terms = A + B, A' + C

Residues = B, C

RPI = B + C, hazard cover X = (A' + C)(A + B)(B + C)Solution: add a RPI (circuit segment) based upon the consensus theorem so that the transition is is covered in the new prime implicant (circuit segment).

Example: X = A' B + A C = (A' + C)(A + B)Example: X = A' B + A C = (A' + C)(A + B)

(A + B + C) (A' + B + C)

1 1 1 0 1 1

(A + B + C) (A' + B + C)

1 1 1 0 1 1

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Glitch ProcedureGlitch Procedure

1. Identify the coupled SOP or POS terms

2. Add RPI consensus term(s)The circuit will not longer be minimized

3. Reject any set of two terms containing more than one coupled variable

4. Read the initial and final states from the coupled terms in hazardous transition (i.e., minterms for SOP, Maxterms for POS)

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4 Variable Example - SOP4 Variable Example - SOP

00 01 11 10

00 0 1 1 0

01 1 1 0 0

11 1 0 0 1

10 1 0 0 1

ABCD

CBDCADCBFSOP

CBADBACBDCADCBFSOP

SOP HazardsSOP Hazards

hazard coverhazard cover

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4 Variable Example - POS4 Variable Example - POS

00 01 11 10

00 0 1 1 0

01 1 1 0 0

11 1 0 0 1

10 1 0 0 1

ABCD

CBDCADCBFPOS

POS HazardsPOS Hazards

hazard coverhazard cover

DBACBACBDCADCBFPOS

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Alternate ProcedureAlternate Procedure

1. Detect static 1-hazards in SOP expression for F

2. Add RPI(s) to obtain SOP hazard-free expression

3. Convert SOP-hazard free to POS for F’

4. Detect static 0-hazards in POS expression

5. Add RPI(s) to obtain POS hazard-free expression

6. Final expression is both static 1- and 0- hazard-free

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4 Variable Example - Alt.4 Variable Example - Alt.Katz Alternative MethodKatz Alternative Method

1. Get FSOP+

2. Look at (FSOP+)'

3. Check (FSOP+)' SOP and make 0-hazard free, if needed

CBADBACBDCADCBFSOP

CBADBACBDCADCBFSOP

00 01 11 10

00 0 1 1 0

01 1 1 0 0

11 1 0 0 1

10 1 0 0 1

ABCD

DCBDCACBA

DBACBF SOPSOP

0-hazard free0-hazard free

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Do Activity #1 NowDo Activity #1 Now

Apply glitch/hazard detection, elimination Apply glitch/hazard detection, elimination techniquestechniques

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Arithmetic Logic UnitArithmetic Logic Unit

C0

Bn-1 … B0 An-1 … A0

INPUTS

ALU

Si-1 … S0M

CONTROLSIGNALS

Fn-1 … F0

Cn

OUTPUTS

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S1

0011

S0

0101

Function

Fi = AiFi = not AiFi = Ai xor BiFi = Ai xnor Bi

CommentInput Ai transferred to outputComplement of Ai transferred to outputCompute XOR of Ai, BiCompute XNOR of Ai, Bi

M = 0, Logical Bitwise OperationsM = 0, Logical Bitwise Operations

Sample ALU SpecificationSample ALU Specification

M = 1, CM = 1, C00 = 0, Arithmetic Operations (with no carry in) = 0, Arithmetic Operations (with no carry in)0011

0101

F = AF = not A

F = A plus BF = (not A) plus B

Input A passed to outputComplement of A passed to outputSum of A and BSum of B and complement of A

M = 1, CM = 1, C00 = 1, Arithmetic Operations (with carry in) = 1, Arithmetic Operations (with carry in)0011

0101

F = A plus 1F = (not A) plus 1

F = A plus B plus 1F = (not A) plus B plus 1

Increment ATwos complement of AIncrement sum of A and BB minus A

Not all operations appear useful, but "fall out" of internal logicNot all operations appear useful, but "fall out" of internal logicNot all operations appear useful, but "fall out" of internal logicNot all operations appear useful, but "fall out" of internal logic

Logical and Arithmetic OperationsLogical and Arithmetic OperationsLogical and Arithmetic OperationsLogical and Arithmetic Operations

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M0

1

1

S10

0

1

1

0

0

1

1

0

0

1

1

S00

1

0

1

0

1

0

1

0

1

0

1

CiXXXXXXXXXXXX000000000000111111111111

Ai010100110011010100110011010100110011

BiXXXX01010101XXXX01010101XXXX01010101

Fi011001101001011001101001100110010110

Ci+1XXXXXXXXXXXXXXXX00010100011001111101

Sample ALU Sample ALU Bit Slice Bit Slice DesignDesign

Traditional Design Approach:Traditional Design Approach:

Truth TableTruth Table

SS00, S, S11 = Select bits= Select bits

M M = Mode (arithmetic/logic)= Mode (arithmetic/logic)

AAii,, BBii = Inputs= Inputs

CCii = Carry in= Carry in

FFii = Output= Output

CCi+1i+1 = Carry out= Carry out

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1. espressoespresso SOP implementation: 25 gates, 2 levels

2. MisIIMisII (a multilevel synthesis tool) optimized implementation: 12 gates, 2 levels

3. CleverClever hand design hand design: 8 gates, 4 levels (but uses XORXORs)

Sample ALU DesignSample ALU DesignDesign ComparisonsDesign ComparisonsDesign ComparisonsDesign Comparisons

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Multilevel ALU DesignMultilevel ALU DesignClever Hand Design ImplementationClever Hand Design ImplementationClever Hand Design ImplementationClever Hand Design Implementation

8 Gates(3 are XOR)

8 Gates(3 are XOR)

S1 = 0 S1 = 0 Bi is blocked Bi is blocked

Then operations involve Ai only

S0 controls operation of X1S0 controls operation of X1S0 = 0, X1 passes AiS0 = 1, X1 passes Ai'

The XOR gate acts as an invertering or non-inverting buffer

M = 0 M = 0 Ci is blockedCi is blocked

This decouples the bit slices

M = 1 M = 1 Carry in ripples thru Carry in ripples thru

OR gate O1 output:OR gate O1 output:Ci+1 = Ai•Ci + Bi•(Ai Ci)

XOR gate X3 output: XOR gate X3 output: Fi = Ai Bi Ci

BiS1 AiS0Ci

M

FiCi+1

X1

X2

X3

A1 A2

A3 A4

O1

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74181 TTL ALU74181 TTL ALUActive High Inputs & Outputs, Active Low CarriesActive High Inputs & Outputs, Active Low Carries

Selection M = H, Logic M = L, Arithmetic Functions

S3 S2 S1 S0 Functions Cn = H Cn = L

L L L L A' A A plus 1L L L H (A + B)' A + B (A + B) plus 1L L H L A' B A + B' (A + B') plus 1L L H H 0 minus 1 zeroL H L L (A B)' A plus A B' A plus A B' plus 1L H L H B' (A + B) plus A B' (A + B) plus A B' plus 1L H H L A B A minus B minus 1 A minus BL H H H A B' A B minus 1 A BH L L L A' + B A plus A B A plus AB plus 1H L L H (A B)' A plus B A plus B plus 1H L H L B (A + B') plus A B (A + B') plus A B plus 1H L H H A B A B minus 1 A BH H L L 1 A plus A = 2A 2A plus 1H H L H A + B' (A + B) plus A (A + B) plus A plus 1H H H L A + B (A + B') plus A (A + B') plus A plus 1H H H H A A minus 1 A

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The sense of the carry in and carry out are OPPOSITE from the input bits (no bubbles)The sense of the carry in and carry out are OPPOSITE from the input bits (no bubbles)

Fortunately, the carry lookahead generator maintains the correct sense of the signals

Fortunately, the carry lookahead generator maintains the correct sense of the signals

181A3A2A1A0B3B2B1B0

CnM

S3 S2 S1 S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

16

17

18

19

20

21

22

23182P3

P2

P1

P0

G3

G2

G1

G0

Cn

Cn+z

Cn+x

P

G

Cn+y

13

3

1

14

5

4

2

15

6

12

11

9

10

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74181 ALU & 74182 Carry Lookahead Units74181 ALU & 74182 Carry Lookahead Units

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CLU speeds up calculations of multi-chip ALU

CLU speeds up calculations of multi-chip ALU

182P3P2P1P0G3G2G1G0Cn

Cn+z

Cn+x

PG

Cn+y

1331

14542

156

12119

107

181A3A2A1A0B3B2B1B0CnM

S3S2S1S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

1617

18

19

20

21

22

23

181A3A2A1A0B3B2B1B0CnM

S3S2S1S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

1617

18

19

20

21

22

23

181A3A2A1A0B3B2B1B0

CnM

S3 S2S1S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

1617

18

19

20

21

22

23

181A3A2A1A0B3B2B1B0

CnM

S3S2S1 S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

1617

18

19

20

21

22

23

C0

C1616-bit ALU16-bit ALUwith Carry

Lookahead Unitwith Carry

Lookahead Unit

Carry in

Carry out

Group G & P

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Do Activity #2 NowDo Activity #2 NowDue: End of Class Today

RETAIN THE LAST PAGE (#3)!!

For Next Class:• Bring Randy Katz Textbook, & TTL Data Book

• Required Reading:– Sec 6.1 of Katz

• This reading is necessary for getting points in the Studio Activity!