#1. gioi thieu tong quan_2

7/25/2019 #1. Gioi Thieu Tong Quan_2

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CHNG 1

NHP MN MCH S

Gii thiu tng quan


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Mnhc: Nhp mnMch s

Ging vin: ThS. H Ngc Dim

Email: [email protected]

Gi tip SV: 15h2016h20, th 2, 3, 6 hngtun

a im: P.E6.6

2

Thng tin ging vin, Sch thamkho, Qui nh mnhc
mailto:[email protected]:[email protected]


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Sch thamkho

3

Thit k lun l sinh c Anh V, NXB

HQG TP.HCM, 2015.

Digital design - Principles and

Practices, John F. Wakerly, 4th

Edition, Prentice-Hall, 2001.

Digital Systems - principles and

applications, Ronald J. Tocci, 10th

Edition, Prentice-Hall, 2001.

Thng tin ging vin, Sch thamkho, Qui nh mnhc


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THNG TIN GING VIN, SCH THAMKHO, QUI NH MN HC

Trng s nh gi ccphn:

Thc hnh: 20%

Kim tragia k: 30%

Thicui k: 50%

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Mc tiu mnhc

Hiu c lun ls (digital logic) mc cng (gate level) v

mc chuyn mch (switch level)ca cc thnhphn logict

hp (combinational logic) v logictun t (sequential logic)

Thit k vthc thi ccmch logict hp vtun t

Phn tchc ccmch logics t n gin n phc tp

Bit s dng cc cngc (tools)h trv cc Kitthc hnhtrongthit k logicS

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V tr,i tng mnhc trongchuithit kvng dng chip

V trca mnhc

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i tng mnhc:Cng logic: AND, OR, NOT,

NAND, NOR,

Cht, Flip-flop, thanh ghi (register)

Mch logic t hp: cng, tr, so

snh, chn knh, phn knh,

Mch logic tun t: mch m ngb, bt ng b, thanh ghi dch,


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Chui cc mnhc v thit kvngdng chip

Tonri rc

Nhp mnmch s

Kin trc my tnh

Thit k lun ls

Thit k vi mch vi HDL

Thit k vi mch: s, tng t, hn hp

H iu hnh

H thng nhng

Vi x lVi iu khin7


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Nhp mnMch s

Ni dung mnhc:

Chng 1: Gii thiu

Chng 2: Biu din s trong cch c s khc nhau

Chng 3: i s Boolean v cccng lun l (logic gates)

Chng 4: Mch logic vnh giti u

Chng 5: Mch t hp

Chng 6: Mch tun t

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Chng 1: Gii thiu

Tng quan

Nhng c im ca S (digital features)

Qui trnhthit k S (digital design processing)

Ccloi chip S

Nhng thut ng ca S

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Chng 1: Gii thiu

Tng quan



Ccloi chip S

Nhng thut ng ca S

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Cngngh vi in t hay vi mch tchhp ccuc

cchmng to ln trnth gii vi ccthit b thng minh

rai: laptop, my tnhbng, in thoi thng minh,internet,

Nn cngnghipbndn c doanh thutng vt bc,

t 21 t la nm 1985 n 324 t la nm 2012

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Tng quan


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Robert Noyce, 1927 - 1990

Bit danhngch ca thunglngSilicon (Mayor of Silicon Valley)

ng snglp cng ty bndnFairchild nm 1957

ng snglp cng ty Intel nm 1968vi Gordon Moore

ngpht minh ramch tchhp(integrated circuit) vi Jack Kilby

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Tng quan

Ngun: http://en.wikipedia.org/wiki/Robert_Noyce
http://en.wikipedia.org/wiki/Robert_Noycehttp://en.wikipedia.org/wiki/Robert_Noycehttp://en.wikipedia.org/wiki/Robert_Noyce


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Gordon Moore, 1929 -

ng snglp cng ty Intel nm 1968 viRobert Noyce

Tcgi ca nh lut Moore (Moores law)ni ting:S lng transistor trnmch tchhp s

tng xp x gp i saumi 2 nm(http://en.wikipedia.org/wiki/Moore%27s_Law)

nh lut Moore cphtbiu nm 1965.

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Tng quan
http://en.wikipedia.org/wiki/Moore's_Lawhttp://en.wikipedia.org/wiki/Moore's_Lawhttp://en.wikipedia.org/wiki/Moore's_Law


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Tng quan

nh lut Moore vsphttrin vi mchbndn ngy nay


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Tng quan

Ccthit b vh thng Tng t (Analog)

X l trn cc tnhiu lintc (vd: tnhiu m thanhtruynn mt Micro)

Ccthit b vh thng S (Digital)

X l trn cc gitr ri rc ca tnhiu ti mi thi im, gitr nyhoc bng 0hoc bng 1(vd:s sng haytt ca mt

bngn)

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Tng t(Analog) vS (Digital)


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Tng quan

H thng Tng t (analog system) thng tiutn nhiu cngsut hn h thng S (digital system)

H thng S cth x l,lu tr vtruyn d liu hiu qu hn h

thng Tng t,nhng nch cth x l tnhiu ti mi thiim ringbit.

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Tng t(Analog) vS (Digital)

Analog signal Digital signal


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Tng quan

Tnhiu tng t(Analog signal)

-in p trn dydn ca mt Microphone

-m thanh truyn n mt Microphone

Tnhiu s(Digital signal)

- Ntnhn trnmtbn phm


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Vd

Phnbit nhng trng hpbndi thuc Tng t hay S?(a)ng h in t

(b) Dngin ra ngoimt cm

(c)Nhit

(d)iu khin tng/gim m thanhca Radio

Answer

(a) S (digital)(b) Tng t (analog)

(c) Tng t (analog)

(d) Tng t: nu kiu xoay/S: nu kiu bm nt

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Ccthit b v h thng s ngy nay

Ngy nay, thut ng S hoc k thut s tr nnrt quen thuc thng qua cc sn phm c s dngrng ri: computer, in thoi thng minh, my tnh bng,my nghe nhc, my chp hnh/quay phim, t ng ha,robots, giao thng, truyn thng v gii tr.

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Nh h l i khi th t


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Nhng thun li khi thao tctrnd liu s

D thit k

Thng tin c lu tr d dng

chnh xc cao v tb tcng bi nhiu (noise) Cth lp trnhc

Tc p ng nhanh

Nhiu mch s cth ch to thnh cc Chip

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Nh h h khi th t


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Cc tnhiu/thnhphn trongth gii thc ch yu tn ti dng tng t (analog): nhit , pxut, m thanh, tc ,

Vic chuyn d liu t dng tng t (analog) v dng d lius (digital) x l, thngthng 3bc sauc pdng:

Chuyn tnhiu tng t t thc ti v hnhthc s

X l trnd liu thuc dng sChuyn d liu s ng rav li hnhthc tng t ri xut

kt qu rabn ngoi.

Nhng hn chkhi thao tctrnd liu s

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ADC DAC

Tng t(analog) S(digital)

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Digital data

CD drive

10110011101

Analog

reproduction

of music audio

signalSpeaker

Sound

waves

Digital-to-analog

converterLinear amplifier

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Nhiu h thng kt hp gia x l tnhiu tng t v tnhiu s t mc ch mongmun.



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Vd thao tc trnd liu s

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Nn audio/video gim dung lng: MP3, MP4,Mt CD cth lu tr 20 bi ht khi khng nn, nhngcth lu tr 200 bi ht nnd liu.

Nnd liu s cng c dng trongx lnh: JPEG,

PNG, Mt vd v cchthc nnd liu


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Chng 1: Gii thiu

Tng quan



Ccloi chip S

Nhng thut ng ca S

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Nhng c im ca s

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Trng thi

Cao (High):in pt 2Vn 5V

Thp (Low):in pt 0Vn 0.8V

Khng xcnh (Invalid):in pt 0.8Vn 2V Cth to rali (error) trongmch s


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Dng sngkiu s (digital waveform) thayi gia mcthp (Low) vmc cao (High)hoc ngc li.Mt xungchuyn mc dng (positive-going pulse) khi

nchuyn t mc logic thp (low) n mc logic cao(high).Ngc li c gi l xungchuyn mc m(negative-going pulse).

Dng sngkiu s c hnh thnht ccchui xungkthp li.

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Nhng c im ca s

Positive-going pulse Negative-going pulse


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V d: Biu din mc in p trong h thng s

Nhng c im ca s


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Gin nh thi c dng ch ra quanh gia haihaynhiu dng sngkiu s

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Gin nh thi (timing diagram)

D liu ni tip (serial data) v


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D liu S cth c truyn gia haithit b theokiuni tip (serial)hoc theokiu song song (parallel)

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D liu ni tip (serial data) vsong song (parallel data)


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Chng 1: Gii thiu

Tng quan


Qui trnhthit k S (digital design processing) Ccloi chip S

Nhng thut ng ca S

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Qui trnhthit k S

Truyn thng

- Da vo cc m hnh tonhc- S dng ccphngphp phn

tch- Qui nh cc rngbuc- Hu chvi ccthit k nh- Khng phhp vi ccthit k

ln trongthc t

CAD (Computer-Aided Design):Thit k da vo my tnh

- S dng phn mm da trn mhnh tonhc v ccphngphp

phn tch- D dng, tin li chongi s

dng- Nhiu chi tit c tru tng ha- Rtphhp cho ccthit k trong

thc t (thit k phc tp)


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Qui trnhthit k S

Yucu thit k

Mt k thutbng s , lu

Thit k

Mphng

Thit k hotng ng?

Sa lithit k


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Th nghimthc t

Qui trnhthit k S

Kim tra

Thit k hot

ng ng vimt k thut?

Hon thnh

sn phm

Clinh?

Sa lithit k

Sa li

V d: ng d liu (data path)


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Vd: ng d liu (data path)ca mt chip n gin

37Ghi ch: hc chi tit hn trong mnKin trc my tnh


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My phn tchlun l (logic analyzer) cth hin th ngthi nhiu knh (channels)ca thng tindng s v cthhin th gitr d liu ca tng tnhiu ti tng thi imc th trn mn hnhhin th

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Thit b kim tra vo lng


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Chng 1: Gii thiu

Tng quan



Nhng thut ng ca S

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1. Cc chip tiuchun, c bn (Standard chip) Cha mt lng nh cccng logic Thc thinhng hm, chc nng n gin (NOT, AND,

OR,) Vd: cc chip h 74xx

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Ccloi chip S

A. Da voc im, tnhnng


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2. Cc chip ckh nng lp trnhc(Programmable Logic Devices (PLD)hocField-Programmable Gate Array (FPGA))

Tp hp cccng cha c kt ni, vickt ni gia cccng nyc lp trnh

bi ngi s dng thng qua cc CADtools

Chc nng ca chip cth c thit kbi ngi s dng

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Altera DE2 board with Cyclone II FPGA chip

Ccloi chip S



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3. Cc chip chuyndng thc hin mt ng dng c th(Application-Specific Integrated Circuit (ASIC))

Ti u thc thi mt chc nng c th

Ti u v hiu sut, tc thc thi

Nhiu mch logic c tchhp hn Gi thnh cao

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Ccloi chip S


A tray of ASIC chips

An ASIC-based USB Bitcoin miner. The ASIC

chip is on the bottom-left of the device
http://en.wikipedia.org/wiki/USBhttp://en.wikipedia.org/wiki/Bitcoinhttp://en.wikipedia.org/wiki/Bitcoinhttp://en.wikipedia.org/wiki/USB


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tchhp nh (Small Scale Integration - SSI):1 n 20 cng

tchhp trung bnh (Medium Scale Integration - MSI):20 n 200 cng

tchhp ln (Large Scale Integration - LSI):

200 n 1.000 .000 cng

tchhp cc ln (Very Large Scale Integration - VLSI):trn 1.000.000 cng

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Ccloi chip S

B. Da vo tchhp ca cccng logic


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Chng 1: Gii thiu

Tng quan



Nhng thut ng ca S

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Nhng thut ng ca S

Tng t(analog): tnhiu c biu din lintc

S (digital): biu din mt lng ri rc hoc tp hp ca cc

gitr ri rc

Nh phn (binary): Mt h c s 2,biu din bng hai gitr 0

hoc 1

Bit: mt kt nhphn, cth l 0 hoc 1

Chip logic lp trnhc (programmable logic chip): Mt loi

chip s ckh nng lp trnhc thc hin mt chc nng cth

Chip logic chc nng c nh (fixed-function logic chip):Nhngloi chip s cchc nng c nh, khngth thayi

FPGA

ASIC


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THO LUN ???

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