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Digital Logic Design

Week 7

Decoders, encodersand multiplexers

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• Decoders• Encoders• Multiplexers

Decoders, encoders and multiplexers

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Decoders

Decoder detects the presence of specific combinations of bits (code) at its input

Indicates presence of code by asserting outputs: active-HIGH or active-LOW

Example: two simple decoders that detect the presence of the binary code 0011

A1

A0

A2

A3

X

active-HIGH decoder for 0011

A1

A0

A2

A3

X

active-LOW decoder for 0011

(LSB)

(MSB)

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A simple decoder

1

1

1

0

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What binary number does this decoder detect?Boolean expression for the decoder output?Active-LOW or active-HIGH output?

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3-to-8 decoder

0A

1A

2A

inputs

012 AAA

012 AAA

012 AAA

3-to-8decoder

000001

111

binary numberdetected

General decoders have n inputs and 2n outputs– Precisely one output asserted for each unique bit pattern

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Decoders with active-LOW outputs

Active-LOW outputs are indicated by “bubbles” on decoder outputs

Bin/Dec

A0

0123456789

101112131415

4-bit binaryinput

Decimaloutputs

A1

A2

A3

1

1

0

1111111111101111

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Inputs Outputs

4-to-16decoder

1101

1111111111110

111

What are the decoderoutputs for the inputs shown?

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Decoders with enable input

Enable input is like an on/off switch for the decoder: E=1: decoder functions “normally” → one output asserted E=0: no outputs asserted

0A

1A

inputs

2-to-4decoder

E(enable)

outputs

0D

1D

2D

3D

E A1 A0 D0 D1 D2 D3

-----------------------------------------------0 0 0 0 0 0 00 0 1 0 0 0 00 1 0 0 0 0 00 1 1 0 0 0 01 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 1

E=0

E=1

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Logisim simulation of 74x138

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Decoder application #1• Input/output (I/O) devices

exchange data with microprocessor via a shared data bus

• At most one I/O device uses data bus at any one time

• Each I/O device has:– unique “address” A3A2A1A0– active-LOW enable input (EN)

• A3A2A1A0 inputs to 4-to-16 decoder

• Sixteen possible 4-bit I/O port addresses– 0000,0001,…,1111– ports 0–6 (decimal) used here– ports 7–15 (decimal) unused

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Decoder application #2

Recall: each decoder output corresponds to a minterm

To produce a sum of minterms expression, simply OR together the relevant decoder outputs!

0A

1A

2A

0012 mAAA

7012 mAAA

1012 mAAA

3-to-8decoder

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Decoder application #2

A B Cin Cout S-------------------------------------------0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Example: Full-adder adds three bits: A, B and carry-in (Cin) Result is sum (S) and carry-out (Cout)

7653out mmmmC

7421 mmmmS

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Decoder-based implementation of full-adder

Decoder outputs1,2,4,7

Decoder outputs3,5,6,7

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• Decoders• Encoders• Multiplexers

Decoders, encoders and multiplexers

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inputs

0D

16-to-4encoder

1D

15D

0A

1A2A outputs

3A

Encoders

Encoders perform “reverse” of decoder function Assume only one input is asserted, then output is binary code

for that input Example: if D7 is the only HIGH input, then A3A2A1A0 = 0111

In general: input Dk asserted → output is binary equivalent of decimal k

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Encoder application: keypad encoding

Keypad input

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1 2 3 45 7 89 0

0D

16-to-4encoder

1D

15D

0A

1A2A

Binary coderepresentingkey pressed

3A

What should an encoder do if multiple inputs are active?

One answer: make the device a priority encoder• respond to the highest-priority input that is active,

and ignore any lower priority inputs

74x148 : priority encoder Active-LOW inputs 0,1,2,…,7

7: highest priority 0: lowest priority

Coded output A2A1A0

highest asserted input is

Active-LOW enable input EI GS and EO outputs not

important here

012 AAA

74x148 : priority encoder

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• Decoders• Encoders• Multiplexers

Decoders, encoders and multiplexers

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Multiplexers

A multiplexer (MUX) routes data from one of the data inputs D0, D1, D2, D3 to the output Y

Select inputs S1 and S0 determine which data input is chosen

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Multiplexer – timing diagram

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Multiplexer (MUX)Data input selected by S1S0 is directed to output Y

S1S0 = 00 : Y = D0

S1S0 = 01 : Y = D1

S1S0 = 10 : Y = D2

S1S0 = 11 : Y = D3

Y

S1 S0

D0

D1

D2D3

4-to-1MUX

013012011010 SSDSSDSSDSSDY

74x151 : 8-to-1 MUX

MUX application #1

When A2A1A0 = 000, Y = D0

→ set D0 = 0When A2A1A0 = 001, Y = D1

→ set D1 = 1

Y

S2

D0

D1D2

D38-to-1MUXD4

D5D6D7

S1S0

A2 A1 A0 Y--------------------------0 0 0 0 D0

0 0 1 1 D1

0 1 0 0 D2

0 1 1 1 D3

1 0 0 0 D4

1 0 1 1 D5

1 1 0 1 D6

1 1 1 0 D7

Use an 8-to-1 MUX to implement the Boolean function in the truth table below

A2A1A0

MUX application #1

Data inputs tied LOW (= logic-0) 0,2,4,7

Data inputs tied HIGH (= logic-1) 1,3,5,6

Compare with truth table on previous page

MUX application #2• Time-division multiplexing (TDM)

– Multiple bit-streams share access to channel by “taking turns”– Sub-channel #1 in time slot 1, sub-channel #2 in time slot 2, …

c o n t r o lc o n t r o l

D E M U XM U X

TDM also used by second-generation (2G) mobile phones (GSM) to share access to radio spectrum

Data input rateon each

“sub-channel”is 64kbits/s

High-speed channel data rate = 8×64 = 512 kbits/s

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Demultiplexer (DEMUX)Data input is directed to the output line selected by S1S0

S1S0 = 00 : data input to D0

S1S0 = 01 : data input to D1

S1S0 = 10 : data input to D2

S1S0 = 11 : data input to D3Non-selected

output lines have LOW levels

Datainput

S1 S0

D0

D1

D2D3

1-to-4DEMUX

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Demultiplexer – timing diagram

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DEMUX = decoder with enableD S1 S0 D0 D1 D2 D3

-----------------------------------------------0 0 0 0 0 0 00 0 1 0 0 0 00 1 0 0 0 0 00 1 1 0 0 0 01 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 1

D=0

D=1

D

S1 S0

D0

D1

D2D3

1-to-4DEMUX

0A1A

2-to-4decoder

E(enable)

0D1D2D3D