1 design of a general purpose digital logic tester and its implementation in fpga lopamudra kundu...
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DESIGN OF A GENERAL PURPOSE DESIGN OF A GENERAL PURPOSE DIGITAL LOGIC TESTER AND ITS DIGITAL LOGIC TESTER AND ITS IMPLEMENTATION IN FPGAIMPLEMENTATION IN FPGA
Lopamudra Kundu
Reg. No. :- 0033479 of 2002-2003
Roll No.:- 91/RPE/060002
Koushik Basak
Reg. No. :- 0033425 of 2002-2003
Roll No.:- 91/RPE/060011
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Hardware testing: Why & HowHardware testing: Why & How ??
• Verification of circuit functionality
• Detection of faults, if any Manufacturing fault Stuck-at model
• Manual testing using several techniques
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Automation of TestingAutomation of Testing
• Limitations of Manual Testing
Circuit may be too large Number of circuits to be tested may be huge
• Advantages of Automation Testing
High speed process Reliable
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Design Layout of Logic Tester Design Layout of Logic Tester
• Tester
• Device under test
• Display
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Block Diagram of Logic TesterBlock Diagram of Logic Tester
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Software Aspect of DesignSoftware Aspect of Design
• Tester Memory (Stimulus &
Response)
• Device Under Test
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• 4-bit magnitude comparator Compares two 4-bit numbers A and B Gives three outputs corresponding to A>B,
A=B & A<B
• 9’s complement of 4-bit number Subtraction by addition Each digit of a decimal number subtracted
from 9 gives the 9’s complement of the number.
Device Under TestDevice Under Test
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Flow Chart of MagnitudeFlow Chart of Magnitude Comparator Comparator
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Flow Chart of 9’s ComplementFlow Chart of 9’s Complement
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Simulation of DUT & TestingSimulation of DUT & Testing• Stimuli are fetched from the memory
sequentially and input to DUT
• Output of DUT is compared with the corresponding response stored in the memory
• If they tally LED1 glows, otherwise LED2 glows
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Hardware Aspect of DesignHardware Aspect of Design
• Field programmable gate array
• Different components of FPGA
RS 232 serial port Clock source LED
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Key Components of FPGAKey Components of FPGA
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Xilinx Spartan-3 Starter Kit BoardXilinx Spartan-3 Starter Kit Board
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Algorithm of Hardware TesterAlgorithm of Hardware Tester Programmed in VHDL Programmed in VHDL
Step 1: Store n = number of stimuli in array A
Step 2: Store n = number of responses in array B
Step 3: Down convert the system clock to 1Hz
Step 4: Assign i=1
Step 5: While i<=n Go to step 6 End
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Step 6: Arrival of a clock pulse Ai goes to the input of DUT
Step7: Clear C Store DUT output in C
Step8: Compare C and Bi
Step 9: Check (C=Bi)? a) Yes: X=1,Y=0 b) No: Y=1, X=0
Contd.Contd.
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Contd.Contd.
Step 10: If X=1 Glow LED1 If Y=1 Glow LED2
Step 11: i=i+1
Step 12: Go to step 5
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Results and ConclusionsResults and Conclusions• DUT simulated by set of
stimuli stored in the memory
• Output compared with the stored response
If they tally LED1 glows If they don’t tally LED2
glows
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Further Scopes of DevelopmentFurther Scopes of Development
• Test Vector Generation
• MicroBlaze
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Test Vector GenerationTest Vector Generation
• Reduction of number of stimuli required to test a DUT
Path sensitizing technique
Random test
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MicroBlaze ArchitectureMicroBlaze Architecture
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Tester Using MicroBlazeTester Using MicroBlaze
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Thank YouThank You