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Design Considerations and Improvement by Using Chip and Package Co-Simulation

Yeong-Jar Chang, Meng-Xin Jiang, Chen-Wei Chang, Wang-Jin Chen, Faraday Technology Corporation, Taiwan, R.O.C.Charlie Shih, Jack LinCadence Design Systems

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Overview

• Traditional Package Design Consideration

• Proposed Flow

• Per-pin Inductance Checking and Improvement

• Coupling Checking and Improvement

• Co-simulation and Improvement

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Traditional Package Design Consideration

It is very difficult to get the good trade-off between Efficiency and Quality !

EstimatedPackage model

Chip model

Package modelChip model

PackagePre-layoutSimulation

PackagePost-layoutSimulation

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Proposed Flow and Methodologies

GoodEnough?

PackageDesign

FastChecking

No

GoodEnough?

ElectricalChecking

No

IC/PKG/PCBCo-sim

Finish

Yes YesGood

Enough?

No

Yes

Trace impedance Coupling Group delay Reference plane Per-pin inductance

Power impedance Pulse response Insertion/Return loss Transient power

analysis

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Per-Pin Inductance Checking and Improvement (1/2)

(a) Single Ball (b) Parallel 3 Balls (c) Effective 3 Balls

The cases to compare the P/G inductance

GND1GND1

GND2

GND3

GND1

GND2

GND3

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(a) 0.578 ~ 0.92nH (at 100MHz)

(b) 0.402 ~ 0.64nH (at 100MHz)

(c) 0.270 ~ 0.43nH (at 100MHz)

P/G

Im

ped

ance

Per-Pin Inductance Checking and Improvement (2/2)

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Design Consideration (1)

• Do not treat via, lead-frame or BGA ball as simple inductors only

• Parallel scheme can not always get the reduction as we expected

• The better position, case (c), can achieve 33% improvement than case (b) with the same number of ground balls

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Result – GND layout improvement

XIM-EPA can tell us 2% improvementin several minutes

4.267nH 4.195nH

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Example – GND layout improvement

50um 100um

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Coupling Behavior- Even Mode and Odd Mode

Odd

Even

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Coupling Behavior

Rising delay at even pattern = 523.3738 ps Falling delay at even pattern = 450.7990 ps Rising delay at odd pattern = 514.2257 ps Falling delay at odd pattern = 441.7276 ps

0000 -> 1111 faster1111 -> 0000 faster0101 -> 1010 slower1010 -> 0101 slower

LumpedCircuit

Take the EM (electro-magnetic field)Into consideration

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Design Consideration (2)

• The coupling behavior is much different from what we think in the RC-based circuit analysis.

• The corner (fast/slow) simulation will be different

• We need to take the EM into consideration if the size is large or the speed is fast. For the rule of thumb, the critical size is /20.

( = wave length = speed of light / frequency )

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Example - Coupling Improvement

Enlarging the space from 55um to 65um canreduce the coupling coefficient from 0.11 to 0.09

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Basic Co-Simulation Concepts

5v4v3v

0.5v1v

5v3.5v2v

Global GND=0

Global GND=0

REF1 REF2

S1 and S2 areS-parameter models

S1 S2

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• The S-parameter model is a mathematic model which records the relative voltage instead of the absolute voltage.

• Connecting the REFs of S-parameters and the global GND (0 or ideal GND) together is correct for co-simulation. But, it does not mean that they are all 0 voltage.

• Chip-package co-simulation is very important to know the real behavior.

Design Consideration (3)

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Example: Chip-Package Co-Sim

ChipP1 G1 P2 G2

Package

Die side

Ball side

Chip

PackageDie side

Ball side

REF1

REF2

to other REFsand the global ground

P1 G1 P2 G2

P1 G1 P2 G2 P1 G1 P2 G2

Dynamic IR drop without package model Dynamic IR drop with package model of initial design

Dynamic IR drop with package model after modification

1.070~1.079v 1.022~1.031v

1.066~1.074v

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Summary

Have proposed a new flow to improve the efficiency and quality of package design

The chip-level and package-level design concepts are totally different

Have introduced some design considerations for improving package design

Have consolidated the ground connections for chip-package co-simulation

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Appendix

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Case Studies for Model Extraction in Different GND Setting

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Case 1Case 2Case 3

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Delay Differences in PCB (W=6mils, D=6, L=1000, 50ohm)

13.58ps 10.35ps

Odd QuiescentEven

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References

[1] R. Pomerleau, S. Scearce, T. Whipple, “Using Co-design to Optimize System Interconnect Paths”, DesignCon 2011

[2] Keith Felton, “Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems”, Article on www.chipdesignmag.com

[3] Joel McGrath, "The Need for Package-Aware Methodology for IC Design" Article on www.chipdesignmag.com

[4] M. Patil, et al, "Chip-package-board co-design for Complex System-on- Chip(SoC)", in Proc. EPEPS, pp. 273-276, 2010.