1 decoupling capacitors requirements intel - microprocessor power levels in the past have increased...

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Decoupling Capacitors Requirements Decoupling Capacitors Requirements

Intel - Microprocessor power levels in the past have increased exponentially, which has led to increased complexity and cost of both power delivery and power removal. In particular, it has led to a need to exponentially lower the impedance of decoupling capacitors (lower inductance and resistance and higher capacitance).

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Powering high-slew-rate transient loads (such as LSI - microprocessors) require high frequency decoupling and typically uses parallel connection bank of capacitors (usually MLCCs, and low

ESL Polymer Electrolytic caps) to provide low impedance up to several hundred MHz

Decoupling Capacitors RequirementsDecoupling Capacitors Requirements

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Capacitors reach their minimum impedance (Z = ESR) at their resonant frequency (Fos), which is determined by the capacitance value and the ESL of the capacitor.

Fos - Resonant Freq (500KHz)

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PCB pad layout design & Inductance (nH - nanoHenry)

The 'mounted inductance'(PCB) and ESL of a capacitor both contribute to the total inductance loop that current must flow within. The larger the loop, the more the inductance, and the slower the response. Reduction in total inductance is achieved by reducing the size of the current loop. The figure below shows a comparative study of various pad layout designs.


Low Inductance Pad Layout

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ESL ESL impacts the speed of the capacitor response in transferring energy to the load

Ideal capacitorIdeal capacitor

Real world capacitorReal world capacitor

ESR Limits current rating Impacts ripple voltage Energy loss

Insulation Resistance ‘IR’ DC leakage current Energy loss

Parameter Guide

Parasitic Inductance (ESL) Lower is better

Parasitic Resistance (ESR) Lower is better

Insulation Resistance (IR) Higher is better

An ideal capacitor can transfer all its stored energy to a load instantly.

A real capacitor has parasitic inductance (ESL) that prevent instantaneous transfer of a capacitor’s stored energy. The ESL of a capacitor determines the speed of energy transfer from the capacitor to the load.


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Reverse Geometry Low ESL Ceramic Chip Capacitors – MLCCs Reduces ESL up to 60%! Decoupling and noise suppression in high-speed circuits Improved response time in power circuits Reduce the number of decoupling components used Reduce PCB size - costs and component placement costs! 0204, 0306, 0508, 0612 case sizesTCC: (Operating Temp) X7R (-55C to +125C) & X5R (-55C to +85C) Capacitance Range 0.01uF (10nF) to 1.0uF Rated Voltage Range: 6.3V to 50V

Reverse geometry low ESL (Equivalent Series ‘L’ Inductance) MLCCs are ideal for use as high speed decoupling capacitors, mounted in close proximity or adjacent to microprocessors Low inductance (low ESL) surface mount ceramic capacitors are connected directly to the power supply pins of the IC. Short traces or vias are required for this connection to minimize additional series inductance (ESL).

Eight Low ESL MLCCs usedIn microprocessor decoupling

Eight Low ESL MLCCs usedIn microprocessor decoupling


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NMC-R Series Performance Advantage Eq

uiva

lent

Ser

ies

Indu

ctan

ce (L

)Decoupling Capacitors RequirementsDecoupling Capacitors Requirements

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NMC-R Series Performance Advantage

Equi

vale

nt S

erie

s In

duct

ance

(L)

Increased Fos

ESL ≤ 0.20nH


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Low ESL Solid Polymer Aluminum Electrolytic Capacitors 3-Terminal construction reduces Series Inductance ‘ESL’ by 50% Decoupling and noise suppression in high-speed circuits Improved response time in power circuits Reduce the number of decoupling components used Reduce PCB size - costs and component placement costs! Operating Temperature Range: -55°C to +105°C Capacitance Range 68uF to 560uF Rated Voltage Range: 2.0V, 2.5V, 4.0V & 6.3VDC +260°C Reflow Soldering Compatible

ADVANTAGES: Stable with voltage, temperature and timeNo voltage derating No DC bias (weakness of MLCC) Reduce ripple voltage Eliminates piezoelectric ringing & singing Reduce number of capacitors used

ADVANTAGES: Stable with voltage, temperature and timeNo voltage derating No DC bias (weakness of MLCC) Reduce ripple voltage Eliminates piezoelectric ringing & singing Reduce number of capacitors used

Bottom view of component

Top view of component


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ESL Reduction by 3-Terminal Structure

(+) Anode

2-terminal NSP series

ESL in loop impedance is represented by L x T

WESL = k x

where k is a constant

loop impedance

3-terminal NSPL has 50% lower ESL than standard 2-terminal NSP series

3-terminal NSPL has 50% lower ESL than standard 2-terminal NSP series

3-terminal NSPL series


(+) Anode

(-) Cathode

(-) Cathode


ESL

The smaller the capacitor ESL, the smaller the impedance loop, and the faster the

capacitor response in transferring energy to the load, and the better the high frequency noise suppression ability

The smaller the capacitor ESL, the smaller the impedance loop, and the faster the

capacitor response in transferring energy to the load, and the better the high frequency noise suppression ability


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Typical ESL comparison between NSPL, NSP and MLCC 3-Terminal NSPL has low ESL, close to ESL of 0603 size MLCC

0.00E+00

5.00E- 01

1.00E+00

1.50E+00

2.00E+00

1.00E- 02 1.00E- 01 1.00E+00 1.00E+01 1.00E+02

0603 Size MLCCX5R 6.3V 22uF

NSPL181M2.5D5YATRF2.5V 180uF

NSP181M2.5D6ZATRF2.5V 180uF

Frequency (MHz)

ESL

(nH

)

0.01 1 100

2

1

00.1 10

1.5

0.5

0.1 10


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1.00E- 03

1.00E- 02

1.00E- 01

1.00E- 02 1.00E- 01 1.00E+00 1.00E+01 1.00E+02

Frequency (MHz)

Impe

danc

e (O

hm)

0.01 1 100

0.1

0.01

0.0010.1 10

Typical Impedance (Z) comparison between NSPL, NSP and MLCC 3-Terminal NSPL has low Impedance (Z) over wide frequency range

0603 Size MLCCX5R 6.3V 22uF

NSPL181M2.5D5YATRF2.5V 180uF

NSP181M2.5D6ZATRF2.5V 180uF


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0.00E+00

5.00E- 01

1.00E+00

1.50E+00

2.00E+00

1.00E- 01 1.00E+00 1.00E+01 1.00E+02

0.1 10

Frequency (MHz)

ESL

(nH

)

1 100

2

1

0

1.5

0.5

Typical ESL example for each thickness: 1.1mm, 1.4mm and 1.9mm

NSPL471M2D6YATRF2.0V 470uF, 1.9mmT




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Low ESR performance for NSPL series; 220uF, 330uF & 470uF

1.00E- 03

1.00E- 02

1.00E- 01

1.00E- 02 1.00E- 01 1.00E+00 1.00E+01 1.00E+021 100

0.1

0.01

Frequency (MHz)

ESR

(Ohm

)

0.010.001

0.1 10





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Better: lower noiseBetter: lower noise

Best: lowest noiseBest: lowest noiseNSPL

Lowest ESLLowest ESL

High ESLHigh ESL

High frequency noise High frequency noise


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SummarySummary

All decoupling capacitors should connect to a large area low impedance ground plane through a via or short trace to minimize inductance.

Reducing the ESL of the capacitor bank, results in better ‘faster’ capacitor bank that speeds energy transfer to the load.

The strategy is to place the 'fastest' low ESL capacitors as close to the load as possible, as physically close to the power pins of the chip as is possible

Mounted inductance is minimized by locating Vdd and Gnd vias close to each other and minimizing the length of via from the pad to the power planes.

Decoupling Capacitors Requirements - SummaryDecoupling Capacitors Requirements - Summary

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NIC has broad offering in Performance Passives

Additional Information Needed?

Need Samples?

NIC has broad offering in Performance Passives

Additional Information Needed?

Need Samples?

Technical Support: tpmg@niccompcom

Sales Support: [email protected]

Technical Support: tpmg@niccompcom

Sales Support: [email protected]

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1 decoupling capacitors requirements intel - microprocessor power levels in the past have increased...

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