1 cs612 algorithms for electronic design automation cs 612 – lecture 4 floorplanning mustafa ozdal...

Academic presentation for college course (globe design)

FloorplanningMustafa Ozdal Computer Engineering Department, Bilkent UniversityMustafa OzdalCS612 Algorithms for Electronic Design Automation

CS 612 Lecture 4#2Chapter 2 Netlist and System PartitioningOriginal Authors:Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

VLSI Physical Design: From Graph Partitioning to Timing ClosureSOME SLIDES ARE FROM THE BOOK:MODIFICATIONS WERE MADE ON THE ORIGINAL SLIDESVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning

KLMHLienig 33.1IntroductionENTITY test isport a: in bit;end ENTITY test;DRCLVSERCCircuit DesignFunctional Designand Logic DesignPhysical DesignPhysical Verificationand SignoffFabricationSystem SpecificationArchitectural DesignChipPackaging and TestingChip PlanningPlacementSignal RoutingPartitioningTiming ClosureClock Tree SynthesisVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning

KLMHLienig 343.1IntroductionGNDVDDModule eI/O PadsBlock PinsBlock aBlockbBlock dBlock eFloorplanModule dModule cModule bModule aChip PlanningBlock cSupply Network 2011 Springer VerlagVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig4Mustafa Ozdal Computer Engineering Department, Bilkent UniversityFloorplanningCircuit modules obtained through partitioningeither automatic or manual partitioning

Floorplanning: Assign shapes and locations for all circuit modules.

CS 612 Lecture 4#63.1IntroductionExampleGiven: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1

Task: Floorplan with minimum total area enclosed AAABBCCVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig673.1IntroductionExampleGiven: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1

Task: Floorplan with minimum total area enclosed VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig783.1IntroductionSolution:Aspect ratiosBlock A with w = 2, h = 2; Block B with w = 2, h = 1; Block C with w = 1, h = 3

This floorplan has a global bounding box with minimum possible area (9 square units).ExampleGiven: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1

Task: Floorplan with minimum total area enclosed VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig8Mustafa Ozdal Computer Engineering Department, Bilkent UniversityOptimization ObjectivesMinimize the area of the global bounding boxAspect ratio constraints due to packaging and manufacturing limitations (e.g. a square chip)

Minimize the total wirelength between blocksLong connections increase signal delays (lower performance)More wirelength can degrade routabilityMore wirelength increases power (due to wire capacitances)

CS 612 Lecture 4#Combination of area(F) and total wirelength L(F) of floorplan F

Minimize area(F) + (1 ) L(F)

where the parameter 0 1 gives the relativeimportance between area(F) and L(F)

Mustafa Ozdal Computer Engineering Department, Bilkent UniversityObjective Function: ExampleCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityFloorplan RepresentationsA floorplan can be represented based on the locations of the blocks Complicates generation of new overlap-free floorplans

Typical floorplanning algorithms are iterative in natureLocal search and iterative improvement heavily used

Topological representations based on relative block positionsThe represented floorplan guaranteed to be overlap freeEasy to evaluate and make incremental changes

CS 612 Lecture 4#123.3TerminologyA rectangular dissection is a division of the chip area into a set of blocks or non-overlapping rectangles.

A slicing floorplan is a rectangular dissection Obtained by repeatedly dividing each rectangle, starting with the entire chip area, into two smaller rectangles Horizontal or vertical cut line.

A slicing tree or slicing floorplan tree is a binarytree with k leaves and k 1 internal nodesEach leaf represents a block Each internal node represents a horizontal or vertical cut line.VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig12133.3TerminologySlicing floorplan and two possible corresponding slicing treesbdaecfacbdefHVHHVHVHdcefHVba 2011 Springer VerlagVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig13143.3TerminologyPolish expressionbdaecfacbdefHVHHVB+CADEF++Bottom up: V and H + Length 2n-1 (n = Number of leaves of the slicing tree)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig14Mustafa Ozdal Computer Engineering Department, Bilkent University

slide from M. D. F. Wong, On Simulated Annealing in EDA, ISPD 2012CS 612 Lecture 4#163.3TerminologyNon-slicing floorplans (wheels)bdaecabcde 2011 Springer VerlagVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig16173.3TerminologyFloorplan tree: Tree that represents a hierarchical floorplanabcdefghiHHHHVWhicdefgab 2011 Springer VerlagHHHorizontal division(objects to the top and bottom)HVVertical division(objects to the left and right)HWWheel (4 objects cycled around a center object)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig17Mustafa Ozdal Computer Engineering Department, Bilkent UniversityTerminology: Vertical Constraint GraphIn a vertical constraint graph (VCG), node weights represent the heights of the corresponding blocks. Two nodes vi and vj, with corresponding blocks mi and mj, are connected with a directed edge from vi to vj if mi is below mj.bdaecfabdcefst66363663663CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityTerminology: Horizontal Constraint GraphIn a horizontal constraint graph (HCG), node weights represent the widthsof the corresponding blocks. Two nodes vi and vj, with corresponding blocks mi and mj, are connected with a directed edge from vi to vj if mi is to the left of mj.bdaecfabdcefst3422343422CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityLongest Path in a VCGWhat does the longest path in the VCG correspond to?bdaecfabdcefst66363663663 The minimum floorplan heightCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityLongest Path in HCGbdaecfabdcefst3422343422What does the longest path in the HCG correspond to? The minimum floorplan widthCS 612 Lecture 4#223.3TerminologyIn a vertical constraint graph (VCG), node weights represent the heights of the corresponding blocks. Two nodes vi and vj, with corresponding blocks mi and mj, are connected with a directed edge from vi to vj if mi is below mj.

In a horizontal constraint graph (HCG), node weights represent the widths of the corresponding blocks. Two nodes vi and vj, with corresponding blocks mi and mj, are connected with a directed edge from vi to vj if mi is to the left of mj.

The longest path(s) in the VCG / HCG correspond(s) to the minimum vertical / horizontal floorplan span required to pack the blocks (floorplan height / width).

A constraint-graph pair is a floorplan representation that consists of two directed graphs vertical constraint graph and horizontal constraint graph which capture the relations between block positions. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig22233.3TerminologyConstraint graphsHorizontal Constraint GraphVertical Constraint Graphabcdefghiehidgbcfastabhisgfcdet 2011 Springer VerlagVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig23Two permutations represent geometric relations between every pair of blocks Example: (ABDCE, CBAED)

Horizontal and vertical relations between blocks A and B: ( A B , A B ) A is left of B( B A , A B ) A is below B( A B , B A ) A is above B( B A , B A ) A is right of B243.3TerminologySequence pairCABDEVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning


Horizontal and vertical relations between blocks A and B: ( A B , A B ) A is left of B( B A , A B ) A is below B( A B , B A ) A is above B( B A , B A ) A is right of B253.3TerminologySequence pairCABDE A is above BVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning


Horizontal and vertical relations between blocks A and B: ( A B , A B ) A is left of B( A B , B A ) A is above B( B A , A B ) A is below B( B A , B A ) A is right of B263.3TerminologySequence pairCABDE B is left of DVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig26Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySequence Pair: IntuitionSequence 1: ABDCE Sequence 2: CBAEDCABDEABDCEACBEDABCDECS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySequence Pair: IntuitionSequence 1: ABDCE Sequence 2: CBAEDCABDEABDCEACBEDABCDEblocks above Bblocks left of Bblocks below Bblocks right of BCS 612 Lecture 4#29293.4Floorplan Representations3.1 Introduction to Floorplanning3.2 Optimization Goals in Floorplanning3.3 Terminology3.4Floorplan Representations3.4.1 Floorplan to a Constraint-Graph Pair3.4.2 Floorplan to a Sequence Pair3.4.3 Sequence Pair to a Floorplan3.5 Floorplanning Algorithms3.5.1 Floorplan Sizing3.5.2 Cluster Growth3.5.3 Simulated Annealing3.5.4 Integrated Floorplanning Algorithms3.6 Pin Assignment3.7 Power and Ground Routing3.7.1 Design of a Power-Ground Distribution Network3.7.2 Planar Routing3.7.3 Mesh Routing

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH LienigMustafa Ozdal Computer Engineering Department, Bilkent UniversityHorizontal and Vertical ConstraintsA(xA, yA)wAhAB(xB, yB)wBhBIf xA + wA xB and ! (yA+hA yB or yB + hB yA) A is left of BABIf yA + hA yB and ! (xA+wA xB or xB + wB xA) A is below BABCS 612 Lecture 4#31Create nodes for every block. In addition, create a source node and a sink one.313.4.1Floorplan to a Constraint-Graph PairacdestbacdebVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig32Create nodes for every block. In addition, create a source node and a sink one.Add a directed edge (A,B) if Block A is below/left of Block B. (HCG)323.4.1Floorplan to a Constraint-Graph PairacdestbacdebVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig33Create nodes for every block. In addition, create a source node and a sink one.Add a directed edge (A,B) if Block A is below/left of Block B (for VCG/HCG)Remove the redundant edges that cannot be derived from other edges by transitivity.333.4.1Floorplan to a Constraint-Graph PairacdestbacdebVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH LienigMustafa Ozdal Computer Engineering Department, Bilkent UniversityFloorplan to a Sequence PairStep 1: Consider the constraints related to HCGbdaecfabdcefstHCGabecdfConstraints for SP 1abecdfConstraints for SP 2( A B , A B ) A is left of BCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityFloorplan to a Sequence PairStep 2: Consider the constraints related to VCGabecdfConstraints for SP 1abecdfConstraints for SP 2bdaecfabdcefst( B A , A B ) A is below BCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityFloorplan to a Sequence PairStep 3: Create the sequence pairs based on the constraintsSequence 1: bacefdSequence 2: abdefcbdaecf( A B , A B ) A is left of B( B A , A B ) A is below BabecdfConstraints for SP 1abecdfConstraints for SP 2CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySequence Pair to a FloorplanMethod 1 (simpler):1. Create constraint graphs: HCG and VCG2. Pack the blocks based on HCG and VCG (next slides)Complexity: O(n2)

Method 2Pack the blocks based on the sequence pair directlyComplexity: O(nlgn)CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityConstraint Graph Pair to a FloorplanGiven an HCG and a VCG, we can compute a packing solution that satisfies all the constraints.

Basic idea:Compute the longest path on HCGThe coordinate computed for each vertex will be the x-coordinate of the corresponding block in the packed floorplan.Compute the longest path on VCGThe coordinate computed for each vertex will be the y-coordinate of the corresponding block in the packed floorplan.

CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityReminder: Longest Path AlgorithmLONGEST-PATH (G)for each vertex u in Gcoord[u] = 0for each vertex u in G in topological order for each edge (uv) in G docoord[v] = max (coord[v], coord[u]+wt(u))CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Sequence Pair to a FloorplanCompute HCG and VCG for the sequence pair:S1 = bdcefaS2 = dbaefc( A B , A B ) A is left of B( B A , A B ) A is below Ba63b63c43d4e623f62CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: HCG for sequence pairdbacefstS1 = bdcefaS2 = dbaefcCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: VCG for Sequence PairS1 = bdcefaS2 = dbaefcdbacefstCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Longest Path in HCGx(s) = 0x(b) = 0x(d) = 0x(e) = 4x(c) = 4x(a) = 4x(f) = 6x(t) = 8 dbacefstw=3w=4w=3w=4w=2w=2CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Longest Path in VCGdbacefsth=6h=3y(s) = 0y(a) = 0y(d) = 0y(b) = 3y(e) = 6y(f) = 6y(c) = 12y(t) = 15h=6h=6h=6h=3CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Packing6a36b3c43d46e236f2(4,0)(0,3)(4,12)(0,0)(4,6)(6,6)dabefc815CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: SummaryThe sequence pair:S1 = bdcefaS2 = dbaefca63b63c43d4e623f62corresponds to the packed floorplan:dabefc128CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: PerturbationThe original sequence pair:S1 = bdcefaS2 = dbaefcdabefc128What happens if we swap the positionsof a and d in both sequences?i.e. S1 = bacefd S2 = abdefcCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Longest Path in HCG after Perturbationx(s) = 0x(b) = 0x(a) = 0x(e) = 3x(c) = 3x(d) = 3x(f) = 5x(t) = 7 abdcefstw=3w=3w=4w=4w=2w=2CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Longest Path in VCGabdcefsth=6h=6y(s) = 0y(a) = 0y(d) = 0y(b) = 6y(e) = 3y(f) = 3y(c) = 9y(t) = 12h=3h=6h=6h=3CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Packing6a36b3c43d46e236f2(0,0)(0,6)(3,9)(3,0)(3,3)(5,3)dabefc712CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: SummaryThe original sequence pair:S1 = bdcefaS2 = dbaefcdabefc128Swap positions of a and d in both sequences:S1 = bacefd S2 = abdefcdabefc712CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySequence Pair to a FloorplanMethod 1 (simpler):1. Create constraint graphs: HCG and VCG2. Pack the blocks based on HCG and VCG (next slides)Complexity: O(n2)

Method 2Pack the blocks based on the sequence pair directlyComplexity: O(nlgn)CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityReminder: A Common SubsequenceGiven two sequences X and Y:Z is a common subsequence of X and Y if Z is a subsequence of both X and Y.

Example:X = bdcefaY = dbaefc

Z = bef (a common subsequence of X and Y)

because X = bdcefa Y = dbaefcCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityReminder: Longest Common Subsequence (LCS)Each element in the sequence can have a weight definedExample:Elements: a b c d e fWeights: 3 3 4 4 2 2Longest common subsequence (LCS) of two sequences is the common sequence with the maximum weight

X = bdcefaY = dbaefcLCS (X, Y) = defwith weight = 4 + 2 + 2 = 8

CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityLCS of a Sequence PairSequence pair: X = bdcefaY = dbaefca63b63c43d4e623f62What does the LCS(X, Y) correspond to?dabefc128Let the weights defined as the block widthsLCS(X, Y) = def( A B , A B ) A is left of B the maximum horizontal span of the floorplanCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityLCS of a Sequence PairSequence pair: X = bdcefaY = dbaefca63b63c43d4e623f62What does the LCS(XR, Y) correspond to?dabefc128Let the weights defined as the block heightsLCS(XR, Y) = aec( B A , A B ) A is below B the maximum vertical span of the floorplanCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySequence Pair to a FloorplanHow to find the x-coordinate of block b?Consider the location of b in the sequence pair (X,Y)X = X1 b X2Y = Y1 b Y2

What does LCS (X1, Y1) correspond to?the max horizontal span of the blocks left of b

x-coord (b) = LCS(X1, Y1)( A B , A B ) A is left of BCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySequence Pair to a FloorplanHow to find the y-coordinate of block b?Consider the location of b in the sequence pair (X,Y)X = X1 b X2Y = Y1 b Y2XR= X2Rb X1R

What does LCS (X2R, Y1) correspond to?the max vertical span of the blocks below b

y-coord (b) = LCS(X2R, Y1)( B A , A B ) A is below BCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySequence Pair to a Floorplan using an LCS AlgorithmFind-LCS: Given two sequences X and Y consisting of n blocks, return the length of the LCS before each block bi.e. Return length of LCS(X1, Y1) for each block b for which X= X1 b X2 and Y = Y1 b Y2

Inputs: Block a b c d e fWeight 3 3 4 4 2 2X = bdcefaY = dbaefcOutput:LCS lengthbefore4 0 4 0 4 6CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySequence Pair to a Floorplan using an LCS AlgorithmFIND-LCS is solvable in O(nlgn) timeTang, X. Tian, R. and Wong, D.F., Fast Evaluations of Sequence Pair in Block Placement by Longest Common Subsequence Computations, DATE 2000

Sequence pair (X,Y) to a packed floorplan:x-coords = FIND-LCS (X, Y, widths)y-coords = FIND-LCS (XR, Y, heights)CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Sequence Pair to a Floorplana63b63c43d4e623f62x-coords FIND-LCS (bdcefa, dbaefc, widths)4 0 4 0 4 6x-coords = Sequence pair: X = bdcefaY = dbaefcCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Sequence Pair to a Floorplana63b63c43d4e623f62y-coords FIND-LCS (afecdb, dbaefc, heights)0 3 12 0 6 6y-coords = Sequence pair: X = bdcefaY = dbaefcCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversityExample: Sequence Pair to a Floorplan6a36b3c43d46e236f2(4,0)(0,3)(4,12)(0,0)(4,6)(6,6)dabefc815Sequence pair: X = bdcefaY = dbaefcHow will the floorplan change if we swap a and d in sequence X?CS 612 Lecture 4#643.5Floorplanning Algorithms3.1 Introduction to Floorplanning3.2 Optimization Goals in Floorplanning3.3 Terminology3.4Floorplan Representations3.4.1 Floorplan to a Constraint-Graph Pair3.4.2 Floorplan to a Sequence Pair3.4.3 Sequence Pair to a Floorplan3.5 Floorplanning Algorithms3.5.1 Floorplan Sizing3.5.2 Cluster Growth3.5.3 Simulated Annealing3.5.4 Integrated Floorplanning Algorithms3.6 Pin Assignment3.7 Power and Ground Routing3.7.1 Design of a Power-Ground Distribution Network3.7.2 Planar Routing3.7.3 Mesh Routing


KLMH Lienig6465653.5Floorplanning AlgorithmsOtten, R.: Efficient Floorplan Optimization. Int. Conf. on Computer Design, 499-502, 1983Common GoalsTo minimize the total length of interconnect, subject to an upper bound on the floorplan area or

To simultaneously optimize both wire length and area


KLMH LienigMustafa Ozdal Computer Engineering Department, Bilkent UniversityFloorplan SizingEach block has the following constraints:Area constraint: wblock . hblock areablockLower bound constraints: wblock wLB and hblock hLB Discrete wblock and hblock options

Min-area floorplan: For a given slicing floorplan, compute the locations and shapes to obtain the min floorplan area.Is this problem NP-hard?No, its polynomial time solvable!CS 612 Lecture 4#673.5.1Floorplan SizingShape functionsLegal shapesLegal shapeswhwhBlock with minimum width and height restrictionsha*aw A Otten, R.: Efficient Floorplan Optimization. Int. Conf. on Computer Design, 499-502, 1983VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig67683.5.1Floorplan SizingShape functionswhHard library blockOtten, R.: Efficient Floorplan Optimization. Int. Conf. on Computer Design, 499-502, 1983whDiscrete (h,w) valuesVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig68693.5.1Floorplan SizingCorner points52252525whVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig69703.5.1Floorplan Sizing Algorithm

This algorithm finds the minimum floorplan area for a given slicing floorplan in polynomial time. For non-slicing floorplans, the problem is NP-hard.

Construct the shape functions of all individual blocks

Bottom up: Determine the shape function of the top-level floorplan from the shape functions of the individual blocks

Top down: From the corner point that corresponds to the minimum top-level floorplan area, trace back to each blocks shape function to find that blocks dimensions and location.VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig70714224Block B:Block A: 5533Step 1: Construct the shape functions of the blocks3.5.1Floorplan Sizing ExampleVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig71724224Block B:Block A: 55333.5.1Floorplan Sizing ExampleStep 1: Construct the shape functions of the blocks24h6w26453VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig72734224Block B:Block A: 55333.5.1Floorplan Sizing ExampleStep 1: Construct the shape functions of the blocks24hw264635VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig73744224Block B:Block A: 5533w2624h46hA(w)3.5.1Floorplan Sizing ExampleStep 1: Construct the shape functions of the blocksVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig74754224Block B:Block A: 5533hB(w)w2624h46hA(w)3.5.1Floorplan Sizing ExampleStep 1: Construct the shape functions of the blocksVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig7576w2624h46hB(w)hA(w)83.5.1Floorplan Sizing ExampleStep 2: Determine the shape function of the top-level floorplan (vertical)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig7677w2624h46hB(w)hA(w)83.5.1Floorplan Sizing ExampleStep 2: Determine the shape function of the top-level floorplan (vertical)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig7778

w2624h46w2624h46hB(w)hA(w)hB(w)hA(w)hC(w)883.5.1Floorplan Sizing ExampleStep 2: Determine the shape function of the top-level floorplan (vertical)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig7879

w2624h46w2624h46hB(w)hA(w)hB(w)hA(w)hC(w)5 x 5883.5.1Floorplan Sizing ExampleStep 2: Determine the shape function of the top-level floorplan (vertical)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig7980

w2624h46w2624h46hB(w)hA(w)hB(w)hA(w)hC(w)3 x 94 x 75 x 5883.5.1Floorplan Sizing ExampleStep 2: Determine the shape function of the top-level floorplan (vertical)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig8081

w2624h46w2624h46hB(w)hA(w)hB(w)hA(w)hC(w)3 x 94 x 75 x 588Minimimum top-level floorplanwith vertical composition3.5.1Floorplan Sizing ExampleStep 2: Determine the shape function of the top-level floorplan (vertical)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig8182w2624h46w2624h46hA(w)hB(w)hC(w)hA(w)hB(w)9 x 37 x 45 x 5883.5.1Floorplan Sizing ExampleStep 2: Determine the shape function of the top-level floorplan (horizontal)Minimimum top-level floorplanwith horizontal compositionVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig82833.5.1Floorplan Sizing ExampleStep 3: Find the individual blocks dimensions and locationsw2624h468(1) Minimum area floorplan: 5 x 5Horizontal compositionVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig8384w2624h46(1) Minimum area floorplan: 5 x 5(2) Derived block dimensions : 2 x 4 and 3 x 583.5.1Floorplan Sizing ExampleStep 3: Find the individual blocks dimensions and locationsHorizontal compositionVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig84852 x 43 x 55 x 53.5.1Floorplan Sizing ExampleStep 3: Find the individual blocks dimensions and locationsw2624h46(1) Minimum area floorplan: 5 x 5(2) Derived block dimensions : 2 x 4 and 3 x 58Horizontal compositionVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig85Mustafa Ozdal Computer Engineering Department, Bilkent UniversityFloorplan SizingIteratively compose nodes in the tree bottom-up.

At the root, choose the best solution.

Backtrace the compositionsHVHdcefHVbaCS 612 Lecture 4#873.5.2Cluster GrowthwhwhwhaaabbcGrowth direction246464 2011 Springer VerlagIteratively add blocks to the cluster until all blocks are assignedOnly the different orientations of the blocks instead of the shape / aspect ratio are taken into accountLinear ordering to minimize total wirelength of connections between blocksVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig87883.5.2Cluster Growth Linear OrderingNew nets have no pins on any block from the partially-constructed orderingTerminating nets have no other incident blocks that are unplacedContinuing nets have at least one pin on a block from the partially-constructed ordering and at least one pin on an unordered block

Terminating netsNew netsContinuing netsVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig88893.5.2Cluster Growth Linear OrderingGain of each block m is calculated:

Gainm = (Number of terminating nets of m) (New nets of m)

The block with the maximum gain is selected to be placed next A BN1N4GainB = 1 1 = 0VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig8990

A B C D EN1N2N3N4N5N63.5.2Cluster Growth Linear Ordering (Example)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig9091 A B C D EN1N2N3N4N5N6--2N3,N5--C4N3,N5N3,N501--N6----CE3N3--N3-10-2--N2,N4--N5N5,N6N5,N6CDE2--N3--N30-1-2-2N1--N2--N4N5N4,N5,N6N5,N6BCDE1---3--N1,N2,N3A0Continuing NetsGainTerminating NetsNew NetsBlockIteration # A B D E CN1N2N4N5N6 N3GainA = (Number of terminating nets of A) (New nets of A)Initial blockVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig9192 A B C D EN1N2N3N4N5N6--2N3,N5--C4N3,N5N3,N501--N6----CE3N3--N3-10-2--N2,N4--N5N5,N6N5,N6CDE2--N3--N30-1-2-2N1--N2--N4N5N4,N5,N6N5,N6BCDE1---3--N1,N2,N3A0Continuing NetsGainTerminating NetsNew NetsBlockIteration # A B D E CN1N2N4N5N6 N3VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig9293 A B C D EN1N2N3N4N5N6--2N3,N5--C4N3,N5N3,N501--N6----CE3N3--N3-10-2--N2,N4--N5N5,N6N5,N6CDE2--N3--N30-1-2-2N1--N2--N4N5N4,N5,N6N5,N6BCDE1---3--N1,N2,N3A0Continuing NetsGainTerminating NetsNew NetsBlockIteration # A B D E CN1N2N4N5N6 N3VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig9394 A B C D EN1N2N3N4N5N6--2N3,N5--C4N3,N5N3,N501--N6----CE3N3--N3-10-2--N2,N4--N5N5,N6N5,N6CDE2--N3--N30-1-2-2N1--N2--N4N5N4,N5,N6N5,N6BCDE1---3--N1,N2,N3A0Continuing NetsGainTerminating NetsNew NetsBlockIteration # 2011 Springer VerlagVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig9495 A B D E CN1N2N3N4N5N6 A B C D EN1N2N3N4N5N63.5.2Cluster Growth Linear Ordering (Example)VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig95963.5.2Cluster Growth AlgorithmInput: set of all blocks M, cost function COutput: optimized floorplan F based on C

F = order = LINEAR_ORDERING(M)// generate linear orderingfor (i = 1 to |order|) curr_block = order[i] ADD_TO_FLOORPLAN(F,curr_block,C)// find location and orientation// of curr_block that causes// smallest increase based on // C while obeying constraints VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig96973.5.2Cluster Growth97The objective is to minimize the total wirelength of connections blocks

Though this produces mediocre solutions, the algorithm is easy to implement and fast.

Can be used to find the initial floorplan solutions for iterative algorithms such as simulated annealing.

AnalysisVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig983.5.3Simulated Annealing98Simulated Annealing (SA) algorithms are iterative in nature.

Begins with an initial (arbitrary) solution and seeks to incrementally improve the objective function.

During each iteration, a local neighborhood of the current solution is considered. A new candidate solution is formed by a small perturbation of the current solution.

Unlike greedy algorithms, SA algorithms can accept candidate solutions with higher cost.IntroductionVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig993.5.3Simulated AnnealingSolution statesCostInitial solutionLocal optimumGlobaloptimumVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig991003.5.3Simulated Annealing100Definition (from material science): controlled cooling process of high-temperature materials to modify their properties.Cooling changes material structure from being highly randomized (chaotic) to being structured (stable).The way that atoms settle in low-temperature state is probabilistic in nature.

Slower cooling has a higher probability of achieving a perfect lattice with minimum-energyCooling process occurs in stepsAtoms need enough time to try different structuresSometimes, atoms may move across larger distances and create (intermediate) higher-energy statesProbability of the accepting higher-energy states decreases with temperatureWhat is annealing?VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig1013.5.3Simulated Annealing101Generate an initial solution Sinit, and evaluate its cost.Generate a new solution Snew by performing a random walkSnew is accepted or rejected based on the temperature THigher T means a higher probability to accept Snew if COST(Snew) > COST(Sinit)T slowly decreases to form the final solution

Boltzmann acceptance criterion, where r is a random number [0,1)

Simulated Annealing


KLMH Lienig1023.5.3Simulated Annealing Algorithm


KLMH Lienig1021033.5.3Simulated Annealing AlgorithmInput: initial solution init_solOutput: optimized new solution curr_sol

T = T0// initializationi = 0curr_sol = init_solcurr_cost = COST(curr_sol)while (T > Tmin) while (stopping criterion is not met) i = i + 1 (ai,bi) = SELECT_PAIR(curr_sol)// select two objects to perturb trial_sol = TRY_MOVE(ai,bi)// try small local change trial_cost = COST(trial_sol) cost = trial_cost curr_cost if (cost < 0)// if there is improvement, curr_cost = trial_cost// update the cost and curr_sol = MOVE(ai,bi)// execute the move else r = RANDOM(0,1)// random number [0,1] if (r < e cost/T)// if it meets threshold, curr_cost = trial_cost// update the cost and curr_sol = MOVE(ai,bi)// execute the move T = T// 0 < < 1, T reduction 2011 Springer VerlagVLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning

KLMH Lienig103Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySimulated Annealing AnimationSource: http://www.biostat.jhsph.edu/~iruczins/teaching/misc/annealing/animation.html

CS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySimulated Annealing - NotesPractical tuning needed for good results:How to choose the T values and how to update it?Should we spend more iterations with high T or low T?High T: More non-greedy moves acceptedLow T: Accepts mostly greedy moves, but can get stuckQuality of initial solution should also be consideredCS 612 Lecture 4#Mustafa Ozdal Computer Engineering Department, Bilkent UniversitySimulated Annealing - NotesFor floorplanning:Definition of move depends on the representation usede.g. Polish expression, sequence pair, etc.Cost evaluation of a move may involve:packing (e.g. based on horizontal/vertical constraints)block sizingwirelength estimation

CS 612 Lecture 4#Given:

Netlist with five blocks A, B, C, D, E and six netsN1 = {A, B}

N2 = {A, D}

N3 = {A, C, E}

N4 = {B, D}

N5 = {C, D, E}

N6 = {D, E}

Initial block: ATask: Linear ordering with minimum netlength

1 cs612 algorithms for electronic design automation cs 612 – lecture 4 floorplanning mustafa ozdal...

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