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Cross Evaluation of Proposed PHY Structures for the IEEE 802.16m UL Primary and Secondary Fast Feedback Channels

Document Number: C802.16m-09/0125Date Submitted: 2009-01-05Source Hongmei Sun, Changlong Xu, Jong-Kae (JK) Fwu, Email: {hongmei.sun, changlong.xu, jong-kae.fwu }@ intel.com Qinghua Li, Eddie Lin, Yuan Zhu, Hujun Yin, Roshni Srinivasan, Rath Vannithamby, Sassan Ahmadi Intel CorporationVenue: Re: 802.16m-08/052, Call for Comments on 802.16m SDD (802.16m-08/003r6), Section 11.9.2.1

Base Contribution:N/A

Purpose: To be discussed and adopted by TGm for use in 802.16m SDD

Notice:This document does not represent the agreed views of the IEEE 802.16 Working Group or any of its subgroups. It represents only the views of the participants listed in the “Source(s)” field above. It is offered as a basis for discussion. It is not binding on the contributor(s), who reserve(s) the right to add, amend or withdraw material contained herein.

Release:The contributor grants a free, irrevocable license to the IEEE to incorporate material contained in this contribution, and any modifications thereof, in the creation of an IEEE Standards publication; to copyright in the IEEE’s name any IEEE Standards publication even though it may include portions of this contribution; and at the IEEE’s sole discretion to permit others to reproduce in whole or in part the resulting IEEE Standards publication. The contributor also acknowledges and accepts that

this contribution may be made public by IEEE 802.16.

Patent Policy:The contributor is familiar with the IEEE-SA Patent Policy and Procedures:

<http://standards.ieee.org/guides/bylaws/sect6-7.html#6> and <http://standards.ieee.org/guides/opman/sect6.html#6.3>.Further information is located at <http://standards.ieee.org/board/pat/pat-material.html> and <http://standards.ieee.org/board/pat >.

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Contributions on Fast Feedback Channel Design

Ericsson C80216m-UL_PHY_Ctrl-08_08_062r1 &  

C80216m-UL_PHY_Ctrl-08_052.doc

Intel C80216m-UL_PHY_Ctrl-08_065r2.ppt

LGE C80216m-UL_PHY_Ctrl-08_039r1.ppt &

C80216m-UL_PHY_Ctrl-08_FFBCH.ppt

Mediatek (pilot design for control tile)

C80216m-UL_PHY_Ctrl-08_060.ppt

Motorola Slides S802.16m-08/919r2 &

C80216m-UL_PHY_Ctrl-08_058.ppt

NextWave C80216m-UL_PHY_Ctrl-08_038.doc

Nortel C80216m-UL_PHY_Ctrl-08_064.ppt

Samsung IEEE C802.16m-08/982r2

C80216m-UL_PHY_Ctrl-08_EnhancedFFBCH_Samsung.pdf

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Outline

• Intel’s PCQICH design updated• Fast Feedback Channel Design Cross Evaluation Results using

evaluation criteria agreed upon in UL PHY Control RG– PCQICH: Intel, Samsung, MOT, Nortel

– SCQICH: Intel, LGE, Mediatek, Ericsson, Nextwave, Samsung

• Conclusions and Recommendation

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Intel’s Updated PCQICH Design

• PHY structure is as described in C80216m-UL_PHY_Ctrl-08_065r2.ppt

• Dedicated coding for different information bits– Coding table size of [112x12]

– 4bits: code sequences 1~16: (max correlation distance = 1.95)

– 5bits: code sequences 17~48 (max correlation distance = 3.117)

– 6bits: code sequence 49~112 (max correlation distance = 3.86)

• Sequence mapping:– map each message to a group of codewords or code sequences and put

each codeword in one FMT of the logical PCQICH channel

– Can effectively improve performance at high speed: ex, Veh-A 350km/hr

– Provides better performance than doing permutation proposed by LGE

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Performance Comparison of PCQICH

(Samsung, MOT, Nortel, Intel, LGE-option1)

Note: LGE’s PCQICH-option2 design is not compared due to short notice.

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PCQICH@PB3: 2x6 tile (Nortel 6x3)

• MOT: all results have been shifted left by 1.25dB(=10*log10(24/18)) to compensate for capacity difference

• 4bits: Intel, LGE outperform the rest

• 5bits/6bits: Intel outperforms the rest

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PCQICH@ VA120 : 2x6 tile (Nortel 6x3)

• MOT: all results have been shifted left by 1.25dB(=10*log10(24/18)) to compensate capacity difference

• 4bits: Intel, Nortel, LG outperform others slightly

• 5/6bits: Intel’s design is slightly better than the rest

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PCQICH@ VA350: 2x6 tile (Nortel 6x3)

• MOT: all results has been shifted left by 1.25dB(=10*log10(24/18)) to compensate capacity difference

• Nortel’s design outperforms others (by ~ 0.5dB) due to 6x3 tile vs. 2x6 tile

• W. filter based non-coherent detection: 2x6 tile can be used at 350kmph

• 2x6 tile: Intel’s design outperforms the rest• Overall: Intel’s design is preferred

(performance, legacy support, robustness)

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PCQICH@VA350: 2x6 tile: sequence mapping (cont.)

)64,...,3,2,1(),64,21mod(1 jja j

]64,...,3,2,1[0 Idx],,,[ 1

6413

12

111 aaaaIdx

],,,[ 264

23

22

212 aaaaIdx )64,...,3,2,1(),64,42mod(2 jja j

• Sequence mapping: – Map each message to a group of codewords or code sequences and put each of the

codewords to one FMT of the logical PCQICH channel Ex, 6bits inforation, code sequence index of each FMT will be1) 1st FMT: 2) 2nd FMT: 3) 3rd FMT:

– This can effectively improve performance at high speed: ex,VA350– Provides better performance than permutation proposed by LGe

Conclusion– Sequence mapping improves the performance and lower the error floor– Should be used for enhanced basic receiver– Low pass filter can be used for advanced receiver

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PCQICH@PB3: 6x2 tile (Nortel 6x3)

• 4bits: Intel’s design outperforms the rest• 5/6bits:

– Intel, Samsung are among the best• Overall: Intel’s PCQICH design is

preferred

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PCQICH@ VA120 : 6x2 tile (Nortel 6x3)

• 4bits: Intel & Nortel slightly outperform the rest

• 5/6bits: Similar performance between designs from Intel, Nortel, & Samsung

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PCQICH@ VA350 : 6x2 tile (Nortel 6x3)

• 4bits: Nortel slightly Intel & Nortel slightly outperform the rest

• 5/6bits: Intel and Samsung among the best

• Overall: 6x2 (Intel/Samsung) slightly outperform 6x3 for Veh A 350km/hr

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Summary

Scenarios 4-bit Best Performance 5/6-bit Best Performance

PCQICH@PB3, 2x6 tile Intel, LGe-option1 Intel

PCQICH@VA120 , 2x6 tile Intel, Nortel, LGe-option1 Intel

PCQICH@VA350, 2x6 tile Nortel (6x3), Intel Nortel(6x3), Intel

Summary Intel’s design is preferred (performance, legacy support and robustness)

PCQICH@PB3, 6x2 tile Intel Intel, Samsung

PCQICH@VA120 , 6x2 tile Intel, Nortel Intel, Samsung, Nortel

PCQICH@VA350 , 6x2 tile Intel, Nortel Intel, Samsung

Summary Intel’s design is preferred (performance, robustness, Legacy support)

Note: LGE’s option-1 with 6x2 tile structure is not evaluated due to time constraints, but performance is expected to be similar to that of the 2x6 tile structure

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Performance Comparison of SCQICH (Samsung, MTK, LGE, Ericsson,

Nextwave, Intel)

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SCQICH@AWGN: 2x6 tile, 7~12bits

• 7~12 bits SCQICH@AWGN: Eric ( TBCC, 1/5 rate), Samsung (block code), Intel have similar performance

• Same tile structure for the design, only AWGN is compared

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SCQICH@AWGN: 2x6 tile, 24bits

• 24bits @AWGN: Ericsson (TBCC, rate 2/5) outperforms Intel• Compared with Intel (single design for SCQICH), Ericsson’ solution

has higher design complexity since different code design is used for the two ranges of information size for 13~24 bits and 7~12bits (Needs further analysis)

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SCQICH@PB3: 2x6 tile

• 7bits: LGE, Intel & Samsung among the best

• 12/24bits: Intel/Samsung outperform LGE and Nextwave

• 24 bits Samsung design not compared yet.• Overall: Intel, Samsung’s design provides

best performance for Ped B 3km/hr

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SCQICH@VA120: 2x6 tile

• 7bits: LGE, Intel & Samsung among the best• 12/24bits: Intel & Samsung outperform LGe

and Nextwave• Samsung design with 24 bits not compared

yet.• Overall: Intel, Samsung’s design provides

best performance @ Veh A 120km/hr

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SCQICH@VA350: 2x6 tile

• Inner pilot pattern (from Samsung/MTK) is better than 2 pilots at corners

• 7bits: LGE, Intel & Samsung among the best

• 12/24bits: Intel & Samsung outperform LGe and Nextwave

• 24 bits Samsung design not compared yet.• Overall: Intel & Samsung’s design provides

best performance @ Veh A 350km/hr

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SCQICH@PB3: 6x2 tile

• 7bits: LGE & Intel outperform Nextwave• 12/24bits: Intel outperforms LGe• Overall: Intel’s design has the best

performance for Ped B 3km/hr

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SCQICH@VA120: 6x2 tile

• 7bits: LGE & Intel’s designs outperform Nextwave’s design

• 12/24bits: Intel outperforms LGE• Overall: Intel’s design provides best

performance at Veh A 120km/hr

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SCQICH@VA350: 6x2 tile

• 7bits: LGE & Intel outperform Nextwave• 12/24bits: Intel outperforms LGe • Overall: Intel’s design provides best

performance at VA350

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Summary

Scenarios 7-12bits Best Performance 24bits Best Performance

SCQICH @ AWGN, 2x6 tile Ericsson, Intel, Samsung Ericsson

(Samsung’s TBCC: TBA)

Scenarios 7-bit Best Performance 12/24-bit Best Performance

SCQICH@PB3, 2x6 tile LGE, Intel, Samsung Intel, (Samsung)^^

SCQICH@VA120 , 2x6 tile LGE, Intel, Samsung Intel, (Samsung)^^

SCQICH@VA350, 2x6 tile LGE, Intel, Samsung Intel, (Samsung)^^

Summary Single Design: Intel’s design is preferred (performance and robustness, simple design)Separate Design: Slight gain when optimized for different scenarios.

SCQICH@PB3, 6x2 tile LGE, Intel, (Samsung)* Intel, (Samsung)^^

SCQICH@VA120 , 6x2 tile LGE, Intel, (Samsung)* Intel , (Samsung)^^

SCQICH@VA350 , 6x2 tile LGE, Intel, (Samsung)* Intel , (Samsung)^^

Summary Single Design: Intel’s design is preferred (performance and robustness, simple design)Separate Design: Slight gain when optimized for different scenarios.

(Samsung)*: Does not includes results for 6x2 structure. Similar performance to 2x6 expected.

(Samsung)^^: Samsung’s block code design has similar performance as Intel. 24bit design not compared yet.

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Summary (cont.)

• PCQICH: – Intel’s design provided for 4bits, 5bits, 6bits. Design outperforms others in

most scenarios

– Sequence mapping can effectively lower the error floor for high speed scenario

• SCQICH:– 7bits/12bits: Intel’s design has similar performance as LGE’s design

– 24bits: Intel’s design outperforms all others with a single code design

– Separate code designs show small performance gain when optimized for different code rates (with added complexity).

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Backup Slides

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Simulation Setting

Note: Low pass filter based non-coherent detection: the filter is built based on

, where R is parameterized by Doppler speed. A fixed conservative time delay spread is used to get freq. domain correlation when calculating R since the channels are unknown.

Channel Bandwidth 10MHz

Over-sampling Factor 28/25

FFT Size 1024

Cyclic prefix (CP) ratio 1/8

Channel condition PB3, VA120, VA350

The number of antennas Tx:1, Rx:2

Modulation BPSK/QPSK

Channel estimation 2-D MMSE

Tile size 2x6, 6x2, 6x3

Block size 6x6

Receiver PCQICH: 6x2: non-coherent detection, MLD

2x6: low pass filter based non-coherent detection, MLD

SCQICH: coherent detection, MLD

HhhR E

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Low pass filter based non-coherent detection

• Detected CQI sequence

where

is the predefined orthogonal sequence, and r(j) is received signal of j-th subcarrier

• To reduce complexity, R can be predefined by assuming a fixed high speed and a conservative time delay spread without obvious performance loss

ii

cc

H

Nii

Nipi cc rIRrcr

121

,,1,,10 maxargmaxarg

jcjrjr ii

1c

HhhR E

Tfiii Ncc 1c

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Semi orthogonal sequence of Intel’s updated PCQICH

• 4bits: 16 code sequences (max correlation distance = 1.95)

• 5bits: 32 code sequences (max correlation distance = 3.117)

• 6bits: 64 code sequences (max correlation distance = 3.86)

PCQICH_4bits PCQICH_5bits PCQICH_6bits