1 copyright © 2013 elsevier inc. all rights reserved. chapter 4 computing platforms

1Copyright © 2013 Elsevier Inc. All rights reserved.

Chapter 4

Computing Platforms


Figure 4.1 Hardware architecture of a typical computing platform.


Figure 4.2 Software layer diagram for an embedded system.


Figure 4.3 Organization of a bus.


Figure 4.4 The four-cycle handshake.


Figure 4.5 A typical sequence diagram for bus operations.


Figure 4.6 Timing diagram notation.


Figure 4.7 Timing diagram for read and write on the example bus.


Figure 4.8 A wait state on a read operation.


Figure 4.9 A burst read transaction.


Figure 4.10 State diagrams for the bus read transaction.


Figure 4.11 A bus with a DMA controller.


Figure 4.12 UML sequence of system activity around a DMA transfer.


Figure 4.13 Cyclic scheduling of a DMA request.


Figure 4.14 A multiple bus system.


Figure 4.15 UML state diagram of bus bridge operation.


Figure 4.16 Elements of the ARM AMBA bus system.


Figure 4.17 Organization of a basic memory.


Figure 4.18 An SDRAM read operation.


Figure 4.19 The memory controller in a computer system.


Figure 4.20 Channels and banks in a memory system.


Figure 4.21 A BeagleBoard.


Figure 4.22 An ARM evaluation module.


Figure 4.23 Connecting a host and target system.


Figure 4.24 Architecture of a logic analyzer.


Figure 4.25 Use case for playing multimedia.


Figure 4.26 Use case of synchronizing with a host system.


Figure 4.27 Hardware architecture of a generic consumer electronics device.


Figure 4.28 Platform-level data flows and performance.


Figure 4.29 Times and data volumes in a basic bus transfer.


Figure 4.30 Times and data volumes in a burst bus transfer.


Figure 4.31 Memory aspect ratios.


Figure 4.32 Front panel of the alarm clock.


Figure 4.33 Class diagram for the alarm clock.


Figure 4.34 Details of user interface classes for the alarm clock.


Figure 4.35 The Mechanism class.


Figure 4.36 State diagram for update-time.


Figure 4.37 State diagram for scan-keyboard.


Figure 4.38 Preprocessing button inputs.


Figure 4.39 MPEG Layer 1 encoder.


Figure 4.40 MPEG Layer 1 data frame format.


Figure 4.41 MPEG Layer 1 decoder.


Figure 4.42 Requirements for the audio player.


Figure 4.43 Classes in the audio player.


Figure 4.44 State diagram for file display and selection.


Figure 4.45 State diagram for audio playback.


Figure 4.46 Architecture of a Cirrus audio processor for CD/MP3 players.


UN Figure 4.1


UN Figure 4.2


UN Figure 4.3


UN Figure4.4


UN Figure 4.5


UN Figure 4.6

1 copyright © 2013 elsevier inc. all rights reserved. chapter 4 computing platforms

Documents

multiple bus system

class diagram

memory system

bus operations

example bus

arm amba bus system

software layer diagram

basic bus transfer