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COMP541COMP541

State Machines – 2State Machines – 2Registers and CountersRegisters and Counters

Montek SinghMontek Singh

Feb 8, 2007Feb 8, 2007

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TopicsTopics Lab previewLab preview State machine specification stylesState machine specification styles

Functional: State tables/diagrams/graphsFunctional: State tables/diagrams/graphs Structural: Boolean equationsStructural: Boolean equations Behavioral: VerilogBehavioral: Verilog

Building blocks: registers and countersBuilding blocks: registers and counters

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Lab PreviewLab Preview Digital lockDigital lock

Recognize sequence of four 4-bit input valuesRecognize sequence of four 4-bit input values

Input:Input: Use 4 DIP switches on the boardUse 4 DIP switches on the board

Output:Output: Indicate ‘yes’/‘no’ on LED displayIndicate ‘yes’/‘no’ on LED display

Concepts learned:Concepts learned: State machine specificationState machine specification State machine synthesisState machine synthesis Generating/measuring time intervalsGenerating/measuring time intervals Switch button ‘debouncing’Switch button ‘debouncing’

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Time intervalsTime intervalsmodule cntr(output out, input clk);module cntr(output out, input clk);

reg [31:0] count;reg [31:0] count;

always @ (posedge clk)always @ (posedge clk) count <= count + 1;count <= count + 1;

assign out = count[22];assign out = count[22];

endmoduleendmodule

What does this do?

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Button and DebouncingButton and Debouncing Button Button normally highnormally high Mechanical switches can “bounce”Mechanical switches can “bounce”

Go 1 and 0 a number of timesGo 1 and 0 a number of times

We’ll want toWe’ll want to Debounce: Debounce: Any ideas?Any ideas? Synchronize with clockSynchronize with clock

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Flip-Flop for pushbuttonFlip-Flop for pushbuttonmodule button_test( output q, input btn, input clk );module button_test( output q, input btn, input clk );

reg q;reg q;

always @ (posedge clk)always @ (posedge clk)beginbegin

if(btn == 1)if(btn == 1)q <= 1;q <= 1;

elseelseq <= 0;q <= 0;

endend

endmoduleendmodule

What does this do?

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Simple Module to Begin WithSimple Module to Begin Withmodule led_on(output s6, input button, input clk);module led_on(output s6, input button, input clk);

wire clkb; //optwire clkb; //opt

cntr C1(clkb, clk);cntr C1(clkb, clk);button_test B1(s6, ~button, clkb);button_test B1(s6, ~button, clkb);

endmoduleendmodule

• clk to board clock, P88• button to pushbutton, P93

• Why ~button?• s6 to one of LED segments

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Things to Think AboutThings to Think About Can I press button and not light LED?Can I press button and not light LED? What happens if I hold button down for a long What happens if I hold button down for a long

time?time? What effect will changing period of clkb have?What effect will changing period of clkb have?

On LEDOn LED On button debouncingOn button debouncing

What does it mean to “press the button”?What does it mean to “press the button”? Think carefully about thisThink carefully about this

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Revisit sequence detector Revisit sequence detector exampleexample Design a state machine to detect the pattern Design a state machine to detect the pattern

11011101 In last class: We developed state graph for itIn last class: We developed state graph for it Today: Learn how to code this in VerilogToday: Learn how to code this in Verilog

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Verilog Case StatementVerilog Case Statement Similar to sequence of if/then/elseSimilar to sequence of if/then/else

case (case (expressionexpression)) casecase: statements;: statements; other caseother case: statements;: statements;

default: statements;default: statements; // optional// optional endcaseendcase

Example in a momentExample in a moment

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‘‘Parameter’ = defines constantParameter’ = defines constantmodule seq_rec_v(CLK, RESET, X, Z);module seq_rec_v(CLK, RESET, X, Z);input CLK, RESET, X;input CLK, RESET, X;output Z;output Z;reg [1:0] state, next_state;reg [1:0] state, next_state;

parameter A = 2'b00, B = 2'b01, parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11;C = 2 'b10, D = 2'b11;

Notice that we’ve assigned codes to the states – more later

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Next State specificationNext State specificationalways @(X or state)always @(X or state)beginbegin

case (state)case (state) A: if (X == 1)A: if (X == 1)

next_state <= B;next_state <= B; elseelse

next_state <= A;next_state <= A; B: if(X) next_state <= C;else next_state <= A;B: if(X) next_state <= C;else next_state <= A; C: if(X) next_state <= C;else next_state <= D;C: if(X) next_state <= C;else next_state <= D; D: if(X) next_state <= B;else next_state <= A;D: if(X) next_state <= B;else next_state <= A;endcaseendcase

endend

The last 3 cases do same thing.Just compact style.

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On Reset or CLKOn Reset or CLKalways @(posedge CLK or posedge RESET)always @(posedge CLK or posedge RESET)beginbegin

if (RESET == 1)if (RESET == 1)state <= A;state <= A;

elseelsestate <= next_state;state <= next_state;

endend

Notice that state only gets updatedon +ve edge of clock (or on reset)

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OutputOutputalways @(X or state)always @(X or state)beginbegincase(state)case(state)

A: Z <= 0;A: Z <= 0;B: Z <= 0;B: Z <= 0;C: Z <= 0;C: Z <= 0;D: Z <= X ? 1 : 0;D: Z <= X ? 1 : 0;

endcaseendcaseendend

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Pitfall: Beware of Unexpected Pitfall: Beware of Unexpected Latches!Latches! You can easily specify latches You can easily specify latches

unexpectedlyunexpectedly Hangover from programming in C…!Hangover from programming in C…!

alwaysalways will try to synthesize FF: will try to synthesize FF:

if (select) out <= A;if (select) out <= A;

if (!select) out <= B;if (!select) out <= B; FF added to save old value if condition is falseFF added to save old value if condition is false

To avoid extra FF, cover all possibilities:To avoid extra FF, cover all possibilities:if (select) out <= A;if (select) out <= A;

elseelse out <= B; out <= B;

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Comment on Book CodeComment on Book Code Could shortenCould shorten Don’t need Don’t need next_statenext_state, for example, for example

Can just set state on clockCan just set state on clock Note that the two are a little different in functionNote that the two are a little different in function

Don’t need three Don’t need three alwaysalways clauses clauses Although it’s easier to have combinational code to set Although it’s easier to have combinational code to set

output be separateoutput be separate Template helps synthesizerTemplate helps synthesizer

Check to see whether your state machines were recognizedCheck to see whether your state machines were recognized

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Registers and Counters: Registers and Counters: DefinitionsDefinitions Register – a set of flip-flopsRegister – a set of flip-flops

May include extensive logic to control state transitionMay include extensive logic to control state transitionMay allow shiftingMay allow shifting

registerregister also refers to fast memory for storing data in also refers to fast memory for storing data in a computera computer

CounterCounter Register that goes through sequence of states as it is Register that goes through sequence of states as it is

clockedclocked

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Simple RegisterSimple Register Store D Store D On posedge of ClockOn posedge of Clock Clear signal normally highClear signal normally high

Power-up resetPower-up reset

SymbolSymbol

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ClockingClocking Typically don’t want to load every clockTypically don’t want to load every clock Can gate the clockCan gate the clock

But added clock skew is a problemBut added clock skew is a problem

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EnableEnable

If If loadload H, then D H, then D is gated throughis gated through

Otherwise, Q is Otherwise, Q is fed backfed back Keep same valueKeep same value

No clock gatingNo clock gating

Did this because D FF doesn’t have a “no Did this because D FF doesn’t have a “no change” behaviorchange” behavior

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CountersCounters Counter is a register – has stateCounter is a register – has state Also goes through sequence of states – counts Also goes through sequence of states – counts

– on clock or other pulses– on clock or other pulses Binary counter Binary counter

Counts through binary sequenceCounts through binary sequence nn bit counter counts from 0 to 2 bit counter counts from 0 to 2nn

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Ripple CounterRipple Counter SimpleSimple So Q will alternate 1 and 0So Q will alternate 1 and 0

Why called ripple counter?Why called ripple counter?

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Synchronous CountersSynchronous Counters Ripple counter is easyRipple counter is easy Asynchronous nature may cause problems, Asynchronous nature may cause problems,

thoughthough Delay!Delay!

Synchronous counter most commonSynchronous counter most common

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Synchronous CounterSynchronous Counter Does have sequence Does have sequence

of gatesof gates Delay againDelay again

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Parallel DesignParallel Design

Now constant Now constant delaydelay

Can gang Can gang these to these to make long make long serial-parallel serial-parallel countercounter

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Verilog Counter (simple)Verilog Counter (simple)module count (CLK, EN, Q);module count (CLK, EN, Q);

input CLK, EN;input CLK, EN;output [3:0] Q;output [3:0] Q;

reg [3:0] Q;reg [3:0] Q;

always@(posedge CLK)always@(posedge CLK)beginbegin

if (EN)if (EN) Q <= Q + 4'b0001;Q <= Q + 4'b0001;

endendendmoduleendmodule

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Verilog Counter (from book)Verilog Counter (from book)module count_4_r_v (CLK, RESET, EN, Q, CO);module count_4_r_v (CLK, RESET, EN, Q, CO);

input CLK, RESET, EN;input CLK, RESET, EN;output [3:0] Q;output [3:0] Q;output CO;output CO;

reg [3:0] Q;reg [3:0] Q;assign CO = (count == 4'b1111 && EN == 1’b1) ? 1 : 0;assign CO = (count == 4'b1111 && EN == 1’b1) ? 1 : 0;always@(posedge CLK or posedge RESET)always@(posedge CLK or posedge RESET)beginbegin

if (RESET)if (RESET) Q <= 4'b0000;Q <= 4'b0000;else if (EN)else if (EN) Q <= Q + 4'b0001;Q <= Q + 4'b0001;

endendendmoduleendmodule

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Arbitrary CountArbitrary Count One more type of counter is usefulOne more type of counter is useful Count an arbitrary sequenceCount an arbitrary sequence

Maybe you need a sequence of states Maybe you need a sequence of states

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Circuit and State DiagramCircuit and State Diagram

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Shift RegistersShift Registers Capability to shift bitsCapability to shift bits

In one or both directionsIn one or both directions

Why?Why? Part of standard CPU instruction setPart of standard CPU instruction set Cheap multiplicationCheap multiplication Serial communicationsSerial communications

Just a chain of flip-flopsJust a chain of flip-flops

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Simple 4-Bit Shift RegisterSimple 4-Bit Shift Register Clocked in commonClocked in common Just serial in and serial Just serial in and serial

outout Is this a FIFO?Is this a FIFO?

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Parallel LoadParallel Load Can provide parallel outputs from flip-flopsCan provide parallel outputs from flip-flops And also parallel inputsAnd also parallel inputs

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SchematicSchematic

DetailNext

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DetailDetail

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Why is this useful?Why is this useful? Basis for serial communicationsBasis for serial communications KeyboardKeyboard Serial portSerial port

Initially to connect to terminalsInitially to connect to terminals Now mainly for modemNow mainly for modem

USBUSB FirewireFirewire

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ExampleExample

Clocked 4 times

Why do this? Maybe these are far apart

Could shift data in, or parallel load

What’s on wire at each clock?

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Table Showing ShiftTable Showing Shift

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Serial vs. Parallel TransferSerial vs. Parallel Transfer Parallel transfer – over as many wires as word Parallel transfer – over as many wires as word

(for example)(for example) Serial transfer – over a single wireSerial transfer – over a single wire

Trade time for wiresTrade time for wires Takes n times longerTakes n times longer

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Bidirectional Shift RegisterBidirectional Shift Register Shift either wayShift either way Now we have following possible inputsNow we have following possible inputs

Parallel loadParallel load Shift from leftShift from left Shift from rightShift from right Also “no change”Also “no change”

Schematic nextSchematic next

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SchematicSchematic

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Verilog for Shift RegisterVerilog for Shift Register

module srg_4_r (CLK, SI, Q, SO);module srg_4_r (CLK, SI, Q, SO);input CLK, SI;input CLK, SI;output [3:0] Q;output [3:0] Q;output SO;output SO;

reg [3:0] Q;reg [3:0] Q;assign SO = Q[3];assign SO = Q[3];

always@(posedge CLK)always@(posedge CLK)beginbegin

Q <= {Q[2:0], SI};Q <= {Q[2:0], SI};endend

endmoduleendmodule

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Next TimeNext Time How to generate a VGA signalHow to generate a VGA signal More on state machinesMore on state machines

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Optional Example: One ShotOptional Example: One Shot Help me analyze this oneHelp me analyze this one

What does it do?What does it do?