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COMP541COMP541

Combinational Logic - 3Combinational Logic - 3

Montek SinghMontek Singh

Jan 23, 2012Jan 23, 2012

Today’s TopicsToday’s Topics

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Quick tips on Lab #1Quick tips on Lab #1

Other type of gatesOther type of gates XOR, XNORXOR, XNOR compound gatescompound gates transmission gatestransmission gates

Non-Boolean valuesNon-Boolean values ““Don’t Cares”, or X valuesDon’t Cares”, or X values ““Floating values”, or Z valuesFloating values”, or Z values

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Lab #1 tipsLab #1 tips Testing your circuit using a Testing your circuit using a

Verilog test fixtureVerilog test fixture

ModuleModule module lab1_part1(module lab1_part1(

input A, B, Cin, input A, B, Cin,

output Sum);output Sum);

Ports referenced asPorts referenced as lab1_part1 uut(X, Y, Z, T)lab1_part1 uut(X, Y, Z, T)

Also asAlso as lab1_part1 uut(.A(X), .B(Y), .Sum(T), .Cin(Z))lab1_part1 uut(.A(X), .B(Y), .Sum(T), .Cin(Z))

Circuit tobe tested

(“uut”)

Stimulus:

initial begin

…end

inpu

ts

outp

uts

Verilog test fixture

Other Types of GatesOther Types of Gates

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Exclusive ORExclusive OR

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Exclusive ORExclusive OR What lay people mean by What lay people mean by

““oror”” Symbol is Symbol is

Plus in a circlePlus in a circle

Parity FunctionParity Function

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Recall how parity worksRecall how parity works Ask classAsk class

Write truth table for two input even parityWrite truth table for two input even parity What needs to be generated for parity bit?What needs to be generated for parity bit?

What function of two inputs gives you this?What function of two inputs gives you this?

XOR Gives Odd FunctionXOR Gives Odd Function

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As many inputs as necessaryAs many inputs as necessary How do you get odd parity?How do you get odd parity? Design even parity generator for 3-bit signalDesign even parity generator for 3-bit signal

Draw with XOR, then sum-of-products w/ NAND gatesDraw with XOR, then sum-of-products w/ NAND gates

How do you design a parity How do you design a parity detectordetector??

OthersOthers

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CMOS Transmission GatesCMOS Transmission Gates

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Act like electronic switchesAct like electronic switches

XOR using Transmission Gate XOR using Transmission Gate

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Introduction to CircuitsIntroduction to Circuits

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Introduction to CircuitsIntroduction to Circuits

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A logic circuit is A logic circuit is composed of:composed of: InputsInputs OutputsOutputs Functional specificationFunctional specification Timing specificationTiming specification

inputs outputsfunctional spec

timing spec

CircuitsCircuits NodesNodes

Inputs: A, B, CInputs: A, B, C Outputs: Y, ZOutputs: Y, Z Internal: n1Internal: n1

Circuit elementsCircuit elements E1, E2, E3E1, E2, E3 Each a circuitEach a circuit

A E1

E2

E3B

C

n1

Y

Z

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Types of Logic CircuitsTypes of Logic Circuits Combinational LogicCombinational Logic

MemorylessMemoryless Outputs determined by Outputs determined by

current values of inputscurrent values of inputs

Sequential LogicSequential Logic Has memoryHas memory Outputs determined by Outputs determined by

previous and current values previous and current values of inputsof inputs

inputs outputsfunctional spec

timing spec

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Rules of Combinational Rules of Combinational CompositionCompositionComposition rules:Composition rules:

Every circuit element is itself combinationalEvery circuit element is itself combinational Every node of the circuit is either designated as an Every node of the circuit is either designated as an

input to the circuit or connects to exactly one output input to the circuit or connects to exactly one output terminal of a circuit elementterminal of a circuit elementno output shortsno output shorts

The circuit contains no cyclic pathsThe circuit contains no cyclic pathsevery path through the circuit visits each circuit node at every path through the circuit visits each circuit node at

most once (latches are made via a cyclic path)most once (latches are made via a cyclic path) Example:Example:

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Aside: Circuit Schematics with Aside: Circuit Schematics with StyleStyle

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Drawing style/conventions: (where possible)Drawing style/conventions: (where possible) Inputs are on the left (or top) side of a schematicInputs are on the left (or top) side of a schematic Outputs are on the right (or bottom) side of a Outputs are on the right (or bottom) side of a

schematicschematic Gates should flow from left to rightGates should flow from left to right Straight wires are better to use than jagged wiresStraight wires are better to use than jagged wires

Circuit Schematic Rules (cont.)Circuit Schematic Rules (cont.)Wire connectionsWire connections

A dot where wires cross indicates a connectionA dot where wires cross indicates a connection Wires crossing without a dot make no connectionWires crossing without a dot make no connection Wires always connect at a T junctionWires always connect at a T junction

wires connectat a T junction

wires connectat a dot

wires crossingwithout a dot do

not connect

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Multiple Output CircuitsMultiple Output Circuits

A0

A1

PRIORITYCiIRCUIT

A2

A3

Y0

Y1

Y2

Y3

0

A1 A00 00 11 01 1

0

00

Y3 Y2 Y1 Y00000

0011

0100

A3 A20 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

Output assertedOutput asserted

corresponding corresponding toto

most significantmost significant

TRUE inputTRUE input

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Example: Priority Encoder Example: Priority Encoder HardwareHardware

A1 A00 00 11 01 1

0000

Y3 Y2 Y1 Y00000

0011

0100

A3 A20 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

A3A2A1A0Y3

Y2

Y1

Y0

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Values that are not 0’s and 1’sValues that are not 0’s and 1’s

Don’t Cares (X)Don’t Cares (X)

Floating values (Z)Floating values (Z)

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Don’t Cares (X)Don’t Cares (X)

A1 A00 00 11 01 1

0000

Y3 Y2 Y1 Y00000

0011

0100

A3 A20 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

A1 A00 00 11 XX X

0000

Y3 Y2 Y1 Y00001

0010

0100

A3 A20 00 00 00 1

X X 1 0 0 01 X

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Actually: Several Meanings of XActually: Several Meanings of X

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Don’t careDon’t care Contention (illegal input value)Contention (illegal input value) Uninitialized valueUninitialized value

In a simulatorIn a simulator

Floating: ZFloating: Z Floating, high impedance, open, high ZFloating, high impedance, open, high Z

Floating output might be 0, 1, or somewhere in Floating output might be 0, 1, or somewhere in betweenbetween

A voltmeter wonA voltmeter won’’t indicate whether a node is floatingt indicate whether a node is floating Allows connecting outputsAllows connecting outputs

E A Y0 0 Z0 1 Z1 0 01 1 1

A

E

Y

Tristate Buffer

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NextNext Wed: Full Tutorial on VerilogWed: Full Tutorial on Verilog

so you are more ready for Lab #2so you are more ready for Lab #2

Mon next week:Mon next week: Combinational building blocksCombinational building blocks

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