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Detectors R&D

D. Peter Siddonsa

P. O’Connorb

a National Synchrotron Light Source Dept.b Instrumentation Division

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Outline

• Requirements for NSLS-II Detectors

• NSLS Detector Experience

• Emerging Technologies for Sensor/Electronics Integration

• Proposed R&D Plan

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Goals for NSLS-II Detector Development

• A pixel detector with multiple-tau time autocorrelation electronics on each pixel• Dynamics of systems on the atomic scale.• NSLS-II’s quasi-DC brightness will make it an optimal source for this

experiment.• Megapixel detector with on-pixel correlators can provide sufficient

sampling density to access the sub-microsecond domain.• 3D technology will provide the necessary integration density.

• A pixelated detector with on-pixel MCA• Simultaneous spectroscopy/diffraction detector.• Energy and spatial resolution.• X-ray microprobes with microdiffraction and fluorescence analysis on the

same sample position with the same detector.

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NSLS Detectors

• A series of detectors for selected SR applications has been developed over the past ~5 years

• Key technologies:• Silicon pad and strip detectors (Instrumentation)

• CMOS Application Specific ICs (Instrumentation)

• Advanced Data Acquisition hardware and software (NSLS)

• The highly parallel architectures enabled by these technologies lead to significant performance advantages

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Rapid XRF Elemental Mapping(BNL/CSIRO collaboration)

Pipelined, parallel processor and digitizer

Si padsensor(96 elements)

Low-noise preamp(32 x 3 chan.)

10

mm

Peak detector- multiplexer

size : 3.6 x 3.2 mm²technology: 0.35µm CMOS DP4M

Comparators

Cross-point switchand arbitration logic

PD/TAC array

MUX

Serial Programmable Interface

Bias

• Hardware: 32-element detector + 2 ASICs + digitizer/processor board.

• Dynamic Analysis real-time deconvolution demonstrated at 108 events/second.

• X-ray elemental images of Fiji pyrite collected at NSLS X27A beamline.

• 800 x 500 pixels of 10um x 10um, collected in 5 hr.

• 20X faster than conventional detector.

• Increase to 400 elements + NSLS-II brightness would give additional ×104 gain.

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Detector for Diffraction Applications

sensor640 strips125um pitch

20 ASICslow-noise preamp+ discr. + counter

Real-time growth / surface modification• Beamline X21 in-situ growth endstation

Reflectivity / truncation rods / GISAXS• Tests at Cornell• System under construction for X9 undulator/CFN

Inelastic scattering• System under construction for Argonne• Interest from SSRL

80 mm

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Limitations of Wirebonded Interconnection

pitch

throw

excess area(can’t tile)

NSLS-II detectors will require:

• larger area (100’s cm2)

• finer pixels (< 200m)

• more processing power/pixel (MCA, correlators)

• mosaic construction

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Monolithic Approaches for Sensor/ASIC Integration

• Common Technology• sensor in CMOS process (MAPS)• transistor in sensor process (DEPFET, XAMPS)

• Charge-Shifting• capture charge in a potential well and physically move

it to output port (CCD, CDD)

• Physical Connection• bump bonding (PbSn, In)• direct wafer-wafer bonding

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human hair for s

cale

8m

human hair for s

cale

8m

Bump-bonding: Examples

PX detectorSwiss Light Source1M, 200m2 pixels

large modules possible but:expensive, esp. for fine-pitchmany post-fab process stepsPb fluorescencedelamination

infrared imager(Raytheon)

ATLAS Vertex tracker85M pixels2 m2 silicon

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direct wafer-wafer bonding

• Ultimate goal is monolithic integration of

any technology

• Immediate push in industry is for reducing

wireload distribution in digital ICs

• Science applications being pursued in

optical/IR imaging, HEP tracking

• FNAL and KEK have active HEP designs

• Processes available at Lincoln Labs, JPL,

OKI Semiconductor, IBM

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3D CMOS/Photodiode Integration

1024 x 1024 imageroxide bonded 275°C SOI processthinned to 50m8m pixel pitch106 3D vias; yield 99.999%3.8x106 0.35m CMOS FETs2nA/cm2 dark current10 frames/secV. Sunthuralingam, Lincoln Labs (ISSCC2005)

bonded 2 wafer imager stack

Pixel readout chip for ILC15m pixel pitch106 3D vias; yield 99.999%104 0.18m CMOS FETs per pixel3 transistor levels11 metal layersIn fab (10/1/2006) at Lincoln LabsR. Yarama, Fermilab (FEE 2006)

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R&D Plan

FY 07-08• research the available 3D foundry services and the CAD tools

required to access them• acquire design capability• 1 foundry run (test vehicle)

FY 09-13• further technology experiments as needed• design of correlator and MCA chips• other detector hardware (vacuum, cooling, motion control)• design and production of DAQ hardware• control, acquisition, and user interface software

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Milestones: FY 07-08

Milestones

FY07Identify R&D partner with 3D capability.Acquire design tools compatible with R&D partner.Research correlator designs.Research ADC designs.

FY08Design a suitable test device to verify 3D capabilityFabricate test device with R&D partner.