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4-bit ALU

Yamei Li,Yuping Liang

Hua Qu,James Hsu

Advisor: Dave Parent12/6/2005

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Agenda• Introduction• Project (Experimental) Details

– ALU– Adder– DFF– MUX

• Summary– Project result– Lesson learned

• Acknowledgement

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Introduction

• The 4-bit ALU that our group designed can perform the following functions:– Adder, NOR, OR, and AND.

• The 4-bit ALU operates at 200 MHz and use 5.8mW of Power and occupied an area of 600m x 280m.

• The 4-bit ALU is made up of 4 identical 1-bit ALU, and 14 DFFs.

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Project Description and ALU schematic

• The 4-bit ALU is broken down into sub blocks consisting of:– 4 1-bit Adders– 4 4to1 MUXs– 4 AND, 4 NOR and 4 OR

gate– 10 input DFFs and 4 output

DFFs

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Logic Level

Gate Cg to Drive

#CDNs (N)

#CDP (M)

#LNs #LPs WN (H.C)

WP (H.C)

Cg of gate

DFFin（2）

NAND Master Mux Master

27 11

1 2

2 2

1 2

2 2

2.4 1.65

1.95 2.85

11 16

INV2 7 1 1 1 1 1.5 2.85 7 AOI2 7 2 2 3 3 2.7 4.8 20 AOI1 27 2 2 2 2 2.4 4.2 12

4 Adders (2+2+2+3=9)

INV1 12 1 1 1 1 2 3.3 10 MUX1 6.128 4 4 2 2 1.5 2.25 6.386 INV2 6.386 1 1 1 1 1.5 2.1 6.128 MUX3 8.43 4 4 2 2 1.5 2.25 6.386

MUX (4)

INV3 20 1 1 1 1 1.95 3 8.43 DFFout (2)

NAND Slave Mux Slave

27 20

1 1

2 3

1 2

2 2

4.05 2.85

3.45 4.95

20 27

nsns

PHL 294.17

5 Note: All widths are in microns

and capacitances in fF

Longest Path Calculations

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4-bit ALU Layout and LVS

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ALU Simulations and Power test

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DFF schematic & LVS report

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DFF layout

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DFF Hold Time Fall& Rise

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DFF Setup Time Rise & Fall

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1 Bit Adder Schematic,Layout & LVS

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1 Bit Adder Post Simulation

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4 Bit Adder Schematic and Simulation

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MUX schematics

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MUX layout and LVS

• Size of one MUX = 28m x 70m

• Size of 4 MUX = 5% of ALU area

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MUX Simulation Before Extraction

• Simulation results before extraction TPHL=1.0383 ns , TPLH=1.045 nsPropagation delay < 4 LL x 0.294ns=1.177ns

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MUX Post Simulation

• Results from Post Extraction Simulation

TPHL=0.758 ns , TPLH=0.755 ns

27% faster

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Summary• After this project, we became familiar with

Cadence tool and the fundamental concepts of IC design.

• Our project has 338 transistors and 18 terminals.

• The total area is =280m x 600m

• The power is=3.4W/cm2

• Lessons learned • how to fix the LVS error

• Learn how to work in a team

• Learn how to make trade offs

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Acknowledgements

• Thanks to Professor D. Parent guidance and unlimited patience.

• Thanks to Cadence Design Systems for the VLSI lab