07.flash memory technology

Flash Memory Technology

오 상 현 수석

연구소 , Flash 소자기술 그룹Hynix Semiconductor Inc.

| Memory Technology || Flash Device Technology |

Outline

Part 1 : Introduction to Flash Memory

Part 2 : Flash memory technology Floating gate technology Charge trap memory technology

Part 3 : Scaling limitation and Next generation Flash

Part 1:

Introduction to Flash Memory

[Note]• DRAM : Dynamic Random Access Memory• SRAM : Static Random Access Memory• ROM : Read Only Memory• EPROM : (UV) Erasable Programmable ROM • EEPROM : Electrically Erasable Programmable ROM• FLASH : Flash Erase EEPROM • FeRAM : Ferroelectric Memory


Inside iPhone4

Camera module

Main Board (Back)

http://blog.naver.com/PostView.nhn?blogId=psy2993&logNo=90089860159&viewDate=&currentPage=1&listtype=0

Microphone

Main Frame (Antenna)Main Board (Front)

Antenna & SpeakerFront Panel (LCD)Battery

NANDFlash


NAND & NOR application

• Low Cost and High Density• Page Mode Program

Code Memory

BIOS/Networking

Telecommunications

Mobile Phone (Code)

POS / PDA / PCA

• Fast Random Access• Fast Read Speed

Mass Storage

Memory Cards

Solid-State Disk

Mobile Phone (Storage)

NAND NOR

Tablet PC


Semiconductor memories

MOS MemoryMOS Memory

Random Access Memory ( RAM

)

Random Access Memory ( RAM

)

Read Only Memory

( ROM )

Read Only Memory

( ROM )

Dynamic RAM (DRAM)

Dynamic RAM (DRAM)

Static RAM (SRAM)

Static RAM (SRAM)

Programmable

ROM (PROM)

Programmable

ROM (PROM)Mask

ROMMask

ROM

EPROMEPROM EEPROM

EEPROM

Byte-alterableByte-alterable FlashFlash

Volatile Non-volatile

1970 intel 1970 intel

1971 intel

1970 intel

1979 intel 1984 Toshiba


Bi-stable status in memories

DRAM SRAM FeRAMMRAMFlashMemory

Data “1”“High”

Data “0”“Low”

V/2

0V/2

V

V

0

DielectricCapacitor

양단의 상대 전압이 Positive

또는 Negative

DielectricCapacitor

양단의 상대 전압이 Positive

또는 Negative

Vcc or Vss 공급TransistorGate 전압이High (On)

또는Low (Off)

[latch type]

Vcc or Vss 공급TransistorGate 전압이High (On)

또는Low (Off)

[latch type]

Transistor 를Turn-On 시키기 위한

문턱전압 (VT) 이높은 상태

또는낮은 상태

Transistor 를Turn-On 시키기 위한

문턱전압 (VT) 이높은 상태

또는낮은 상태

Resistor 의Resistance 가

작은 상태또는

큰 상태

Resistor 의Resistance 가

작은 상태또는

큰 상태

Capacitor 의Capacitance 가

큰 상태또는

작은 상태

Capacitor 의Capacitance 가

큰 상태또는

작은 상태

Bi-StableStatus

Description

Bi-StableStatus

Description


Memory performance

Flash EEPROM FeRAMSlow SRAM

DRAM

Nonvolatile Yes Yes Yes No No

Power

ConsumptionMedium Medium Medium Medium Large

Write Speed >10us <10ms <150ns <120ns <60ns

Write Voltage 10~20V 8~12V 2~5V 2~5V 2~5V

Write Endurance 105 cycles 105 cycles 1012 cycles 1015 cycles 1015 cycles


Inside NAND Flash

Bit

lin

e

Con

tact

WL

(Con

trol G

ate

)Flo

ati

ng

Gate

DS

L(D

rain

Sel.

Lin

e)

SS

L

(Sou

rce S

el.

Lin

e)

CS

L

(Cell S

ou

rce L

ine)

Bit

lin

e

1

2N

S/A

Row Decoder

12

M

Colu

mn

Decod

er

Mem

ory

Arr

ay

Lin

eB

it L

ine

1

2N

S/A

Row Decoder

12

M

Colu

mn

Decod

er

Mem

ory

Arr

ay

Word

BLo

BLe

BLs

Blo

ck 0

Blo

ck 1

Blo

ck N

- 1

BLo

BLe

BLs

Blo

ck 0

Blo

ck 1

Blo

ck N

- 1

WL0WL1WL2WL30WL31 SSLDSL

C-WELL

Dra

in C

on

tact

Bit Line

-C-WELL

Sou

rce L

ine

DSL SSL

Part 2 :

Flash memory Technology


Flash cell operation: Introduction

0 1 2 3 4 5 6 7 8 9 10

0.00

25.00µ

50.00µ

75.00µ

100.00µ

125.00µ

150.00µ

175.00µ

200.00µ

225.00µ

250.00µ

NMOS Transistor (0.45/0.25) ÀÇ Vg - Id Æ¯¼º curve

Dra

in C

urre

nt (

amp)

Gate Bias (volt)0 1 2 3 4 5 6 7 8 9 10

Flash Cell (0.45/0.25) Vg - Id curve의 특 성

Dra

in C

urre

nt (

amp)

Gate Bias (volt)

Gate

DrainSource

GND Vg Vd

DrainSource

GND Vd

Floating Gate

Vg

Control Gate

ID

VG

ID

VG

• Conventional NMOS Tr • Floating gate NMOS Tr

| Memory Technology || Flash Device Technology | Seaung Suk Lee

DrainSource

0V 1V3V

DrainSource

0V 1V3V

DrainSource

0V 1V3V

Erase Intrinsic (UV)

Program

-6 -4 -2 0 2 4

0

20

40

60

80

Cell C

urr

en

t (n

A)

Gate Bias (V)

Erased Cell Intrinsic Cell Programmed Cell

Flash cell operation: Read

90

100

120

6

| Memory Technology || Flash Device Technology | Seaung Suk Lee

Flash cell operation: Program & Erase

-4V -2V 0V 1V 3V

ON-Cell(Erase)

OFF-Cell(Program)

VWL


SSDSDBToxCGONOFG VVVVV

)()(

)()(0

SFGSDFGD

BFGToxCGFGONO

VVCVVC

VVCVVCQ

TJJ

SDToxONOT

CC

CCCCCwhere

/

From Gauss' Law

CONO

CTox

Coupling Ratio of Flash cell

ONO Coupling Ratio means Gate Controllability


F-N tunneling

Potential diagram of Si/SiO2 interface

with No Electric Field

Potential diagram of Si/SiO2 interface

with Strong Electric Field

야 ! 거기 둘 Oxide 모서리

잡아 당겨

J = AE² × Exp(-B/E)


NAND cell array architecture

ActiveBL

WL

FG

STI

STI

BL

WL

FG

n+n+

PWEL

PWEL

DSL

SSL

DSL

WL

SSL

On

e S

trin

g


NAND operation: Read

Cell Bias Condition Threshold Voltage DistributionB/L

DSL(4.5V)

Unsel. W/L(4.5V)

Sel. W/L(0V)

Unsel. W/L(4.5V)

SSL(4.5V)

Vsel.VREAD

-4V -2V 1V 3V

ON-Cell OFF-Cell

4.5V

Erase VerifyPGM Verify

Erase Program


NAND operation: Program & Program Inhibit

S D

18V

0V

DSL ( Vcc )

Vpass

Vpgm

Vpass

SSL ( 0V )

18V

0V

10V

0V

10V

0V

B/LVCC

B/L0V

CSL ( Vcc )

S D

18V

~ 8V

Program

Program Inhibit


Channel Boosting in Inhibited String

• Program Selected String

• Program Inhibited String

WL0 WL1 WL2 WL30 WL31SSL DSL

10V 18V 10V 10V 10V Vcc0V 0VVcc

WL0 WL1 WL2 WL30 WL31SSL DSL

10V 18V 10V 10V 10V Vcc0V VccVcc

OFF OFFChannel Self Boosting~8V

OFF ONChannel Ground


Increment Step Pulse Program (ISPP)

Intrinsic celldistribution

15V15.5V

16V 16.5V17V

DSL ( Vcc )

Vpass

Vpgm

Vpass

SSL ( 0V )

Vpgm

0V

10V

0V

10V

0V

B/L0VVCC

B/L0V

CSL ( Vcc )

Fast cell stop programming

Slow cell continuing program at higher bias

ISPP distribution (0.5V+α)

program verification


Erase operation

0V

Vcc

pass gate

erased cell CGs 0 V

P-wellbulk

0V20V

Selected Block

0V

0V

pass gate

erase inhibited cell (Floating)

0V20V

P-wellbulk

0V20V

Unselected Block

FN Tunneling Erase

FloatFloat

20V

Vg=0V

P-well

N-well

20V

P-sub

FloatFloat

20V

Vg~20V

P-well

N-well

20V

P-sub

Boosted by

coupling


Operation condition Summary

DSL

Pass W/L

Sel. W/L

Pass W/L

SSL

B/L_0 B/L_N

SL

Cell Vth -2 ~ -4V1 ~ 3V“ON”“OFF

”

Pass W/L

Read Program Erase

Select Word Line 0 15~20 0

Pass Word Line 4.5 10 0

DSL 4.5 Vcc Floating

SSL 4.5 0 Floating

SL 0 Vcc Floating

Select Bit Line 1 0 Floating

Unselect Bit Line 0 Vcc Floatin

g

Bulk 0 0 20


Unwanted Phenomena I : Disturbance

S D

18V

0V

Program

S D

18V

0V

Program

S D

18V

~ 8V

Pgm Disturb

S D

18V

~ 8V

Pgm Disturb

S D

10V

0V

Pass Disturb

S D

10V

0V

Pass Disturb

S D

10V

0V

Pass Disturb

DSL ( Vcc )

Vpass

Vpgm

Vpass

SSL ( 0V )

18V

0V

10V

0V

10V

0V

B/LVCC

B/L0V

CSL ( Vcc )

0

1

2

3

4

5

0 2 4 6 8 10 12 14

Vpgm Disturb

Vpass Disturb

Fail

Vth

Sh

ift

Vpass[V]

1E+00

1E+01

1E+02

1E+03

1E+04

1E+05

1E+06

7 8 9 10 11 12 13 14

Vpass (V)

No.

of

Fail B

its

PGM Disturb Pass Disturb

Disturb Window

Disturbance: Unwanted slight programming of erase cell

1. Program Disturbance2. Pass Disturbance3. Read Disturbance


Unwanted Phenomena II : Interference

ONO

STI

FGCG

Tunnel Ox

Si-Sub

Ctox

ConoCFGX

CFGXCFGY CFGXYCFGCGCG

CG

FG

0

0.05

0.1

0.15

0.2

0.25

1 2 3 4 5 6 7Adjacent Cell Vth Shift (V)

Cel

l Vth

Shi

ft (

V)

Oxide spacerNitride spacer

VFG = { CONOVCG+ CFGX(V1+V2) + CFGY(V3+V4) + CFGCG(V5+V6) } / CTOT

Where CTOT= Ctox + Cono + { 2CFGX + 2CFGY + 2CFGCG }

Cell Interference: Unwanted Vt shift by the P/E status of adjacent cells


Charge Trap Devices

M. White, "Characterization and modeling of scaled MANOS NVSM devices", IMEC lecture


TANOS Stack

Si-sub(P-type Si)

Oxide(SiO2)

Nitride(Si3N4)

High-K(Al2O3)

Metal Gate(TaN)

Tunnel OxideThin to enable FN tunneling (PGM & Erase)Thick to prevent direct tunneling (Retention)

Charge Trapping Material (Stoichiometric: deep trap, Si-rich: shallow trap)

High-K dielectric materialTo prevent electron back-tunneling (electric field)High CBO* necessary for retention

High Work function Metal GateTo prevent electron back-tunneling (barrier height)

* CBO (Conduction Band Offset)


TANOS Energy Band Diagram

EFEB

EC

4.1eVSi electron affinity

3.2eVOxide CBO

0.9eVOxide electron affinity

Vacuum Level (Evac)

EF

CBO: Conduction band offset (from Si CB edge)VBO: Valence band offset (from Si VB edge)

2.8eVAl2O3 CBO

2.0eVNitride CBO

4.7eVOxide VBO

2.7eVNitride VBO

1.1eVSilicon band-gap4.8eV

Al2O3 VBO

9.0eVOxide band-gap

5.8eVNitride band-gap

8.7eVAl2O3 band-gap

5.2eVMetal Gate Work function

- - -- - - --

1.1~1.8eVNitride active trap energy


Why TANOS?

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

10-6 10-5 10-4 10-3 10-2 10-1 100

Vt

shift

(V

)

Time (s)

Erase @-18V from fresh

workfunction

I 1

I 2

Substrate

Gate

BlockingOxide

TunnelOxide

Trapping Layer

1. Erase Saturation (back-tunneling)

2. In order to suppress electron back-tunneling

- Barrier height Metal Gate, P+ poly-Si gate- Electric field reduction High-K blocking oxide


High-K Blocking Oxide

I 1

I 2

Substrate

Gate

BlockingOxide

TunnelOxide

Trapping Layer

Al2O31. High-k material (k=9~12)2. Sufficient barrier height3. Compatible with poly-Si gate4. Thermally stable

22

3

3

2

2

1

12

2

2

3

3

2

211

2

3

3

2

2

1

13

2

2

1

1

3

3

3

2

2

1

11

2

2

3

3

1

)(

)2

(

)(

)(

)2

(

,)(

)2

(

d

xQddd

Qdd

VxdQ

E

xE

ddd

Qdd

V

Eddd

Qdd

V

E

g

gg


TANOS Key Issue: Erase/Retention

trade-off

Deep trap Nitride Shallow trap Nitride (Slow Erase & Good Retention) (Fast Erase & Poor Retention)

Faster Erase

Less Charge Loss

G. van den Bosch et al, "Nitride engineering for improved erase performance and retention of TANOS NAND Flash memory", NVSMW 2008

h

Trap

hh

eee

e

eee

Hole Tunneling

Back-Tunneling

Gate

Tunnel Oxide

Charge Trap Nitride

Block Oxide

Part 3 :

Scaling LimitationandNext Generation Flash


NAND Demand Driver

Performance

Performance

Density

DSC

UFD

MP3/PMP

Handset

SSD

• Embedded market (mobile phone, MID)

• HDD replacement (PC, Server)

• Optical media replacement (DTV, DVC)

2000 2001 2002 2003 2004 2005

256M~512MB

iPod Launch (2005)

2006 2007 2008 2009 2011 20122010

1/2/4GB

8/16/32GB

64/128GB

128MB

Replacing All Storage


In order to attain more bits in a wafer...

Bit Line (BL)

Upper Selection Gate (USG)

Control Gate (CG)

Lower Selection Gate (LSG)

Source Line (SL)

Shrinking cell sizeIncreasing wafer size

MLC (Multi-Level Cell) 3D Flash

4x ㎚

3x ㎚

2x ㎚

1x ㎚

2.25 times larger every 10years


Technology Roadmap


Scaling Limitation of Floating Gate

Floating Gate Limitation ~ 1xnm ▶ No further space for IPD to wrap-around P1

▶ Low cell current since active size becomes smaller


MLC (Multi-Level Cell)

Related to the Read Related to the Read Disturb (ECC Disturb (ECC

Compensation)Compensation)

1

R0

0

PV1 Vread

SLCSLC

11

R0

01

PV1

00

PV3

R2

PV2

10

R1

Vread

2b/2b/cellcell

Vread

0

1

1

1

1 2 3 4 5 6 7

PV1 PV2 PV3 PV4 PV5 PV6 PV7 PV8

0

1

1

0

0

1

1

0

1

1

0

1

0

0

0

0

1

0

1

1

03b/3b/cellcell

Higher

Upper

Lower

Vread

01

1

1

1

1 2 3 4 5 6 7

PV1PV2PV3PV4 PV5PV6PV7

8 9 10 11 12 13 14

PV8 PV9PV10PV11PV12PV13PV14PV15

150

1

1

1

0

0

1

1

1

0

1

1

1

0

0

1

0

0

0

1

0

1

0

1

1

1

0

1

1

1

0

0

0

1

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

1

1

0

1

1

1

0

4b/4b/cellcell

Top

Higher

Upper

Lower

Requires tight control of each cell distribution

More cell states in the limited voltage range

Performance and Reliability concerns


Scaling Limitation of Floating Gate

Floating Gate Limitation ~ 1xnm ▶ Interference and RTN Increase Cell distribution wider

▶ Fewer electrons are stored in FG Reliability concerns

Interference

Random Telegraph Noise

F5xF4y

F3x

F2x

F1x


Next candidates to Floating Gate

Vertical NAND is the best in cost-effectiveness

Simple Stacking Vertical NANDCross-point Memory

Less beneficial for bit-cost reduction(Critical Mask step increases as stacking)

Cost effective(Critical Mask step keeps

constant as stacking)


Vertical NAND Structures

BiCS P-BiCS TCAT DC-SF

Simple ProcessCleared ONO /

WL delay

Beneficial for Device

Operation

Best Performance

ONO / WL delayComplicated

ProcessComplicated

ProcessLarger Cell Size

No decisive winner as of today

BiCS : Bit-Cost ScalableP-BiCS : Pipe-shaped Bit-Cost ScalableTCAT : Tera-bit Cell Array TransistorDC-SF : Dual Control-gate with Surrounding Floating gate


Vertical NAND Flash using FG

Best 3D cell performance ever using FG instead of SONOS

10-5 10-4 10-3 10-2

-4

-2

0

2

4

6 8V 9V 10V 11V 12V 13V 14V 15V 16V

Vth (

V)

PGM Pulse Width (sec)

Programmed

cell

-6

-4

-2

0

2

4

6

10-3 10-2 10-1

Erase Pulse Width (sec)

-6V -7V -8V -9V -10V -11V -13V

Vth (

V)


Concept of Vertical String 3D NAND

Rotation

2D NAND Flash

3D Vertical String NAND Flash

BL

=

=

CHANNEL

BL

3D is simple rotation of 2D (Schematically the same)


3D Device Key Features

Poly-Si channel SONOS All-around gate Channel-last process 1 step litho (hole)

Single crystal Si channel Floating Gate (or TANOS) 1-side gate Channel-first process 2 step litho (ISO/Gate)

CG

channel

ONO

2D cell 3D cell (Vertical String)

Well

S D

FG

CG

channel S D


Gate-All-Around effect (GAA)

ControlGate

Channel

ONOD

S

Band Diagram

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

planehole 1000nmhole 250nmhole 120nmhole 90nmhole 70nmhole 60nmTunnel

Oxide

CT Nitride

BlockingOxide

Electric Field

2.0

4.0

6.0

8.0

10.0

planehole 1000nmhole 250nmhole 120nmhole 90nmhole 70nmhole 60nm

TunnelOxide

CT Nitride

BlockingOxide

Smaller hole size (or more curvature)

Higher Field at Tunnel Oxide (Inner)

Lower Field at Blocking Oxide (Outer)


3D Device Key Issues

Poly-Si channel SONOS Depletion mode Tr ▶ (Poly-Si channel) Low Cell Current, Wider distribution

▶ (SONOS) Slow Erase, Poor retention

No Source/Drain and Well structure ▶ Needs new Erase operation method (GIDL erase)

Higher WL resistance

DSLMemory Cell

SSL

Source

BL

2D Floating Gate Vertical-NAND

Source

Memory Cell

SSL

BL

PCG

DSLDSL SSL


P-BiCS Process Sequence(2) Channel hole etching : Cell size highly depends on the slope

(3) Slimming for WL pick-up : Thick PR and LER control

(1) Process Sequence : full dip-out of sacrificial layer & filling ONO and channel poly

R. Katsumata et al, "Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operationfor Ultra High Density Storage Devices", SOVT 2009


TCAT Process Sequence

Slit Patterning Nitride Pull-back ONO/MG Dep Gate Separation

silicon silicon silicon silicon

(1) Gate Replacement

(2) Slimming

J. Jang, "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory", SOVT 2009


What is a next paradigm shift?

T. Higashiki, 5th Annual SEMATECH/ISMI Symposium Japan


SummaryPart 1:

Among the various proposed memory concepts, only a few survived.

Flash is nonvolatile memory and the process is compatible to well established conventional Si-process.

Part 2:

Flash cell status ("0" or "1") is defined by the net charge captured inside trapping layer (poly-Si or nitride).

NAND flash programs and erases using FN-tunneling.

Part 3:

NAND scaling has been achieved down to 2xnm technology. However, we are facing limitation for further scaling at 1xnm.

3D flash is the most promising candidate to extend NAND bit growth.


Thank you for attention and ...


Homework#1아래와 같이 주어진 Floating Gate Cell 에서 (a) ONO coupling ratio 와 (b) Floating Gate Potential (Vfg) 를 계산하라 .

60pF

CTox10pF 10pF20pF

20V

0V 0V 0V


Homework#2TANOS stack 은 왼쪽 그림과 같이 Serial Capacitor 로 도식화할 수 있다 . Nitride 내부에는 전하 Q 가 균일하게 분포하고 있다고 가정하고 , Gauss' Law 를이용하여 Block Oxide, Nitride, Tunnel Oxide 에 걸리는 Electric Field 를 유도하라 . (ε1, ε2, ε3 은 각 Layer 의 유전율이며 , d1, d2, d3 는 각 Layer 의 두께이다 .)

Vg

Q

E3

E2

E1

++++

3, d3

2, d2

1, d1

++++

++ x

22

3

3

2

2

1

12

2

2

3

3

2

211

2

3

3

2

2

1

13

2

2

1

1

3

3

3

2

2

1

11

2

2

3

3

1

)(

)2

(

)(

)(

)2

(

,)(

)2

(

d

xQddd

Qdd

VxdQ

E

xE

ddd

Qdd

V

Eddd

Qdd

V

E

g

gg

Block Oxide

Nitride

Tunnel Oxide

07.flash memory technology

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