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Design of a 4-6GHz Wideband LNA in 0.13m

CMOS Technology

Sana Arshad

*

, Faiza Zafar and

Qamar-ul WahabDepartment of Electronic EngineeringNED University of Engineering & Technology

Karachi-75270, Pakistan*[email protected]

Abstract This paper presents the design of a single ended

wideband LNA utilizing reactive elements at the input and

output for impedance matching. It has been shown through

simulations that the LNA architecture utilizes components

similar to a narrowband design but achieves a much wider

bandwidth with high gain and low noise figure. The single ended

wideband LNA is based on 0.13-m CMOS technology from IBM

and simulated in Cadence SpectreRF. The LNA operates for

frequencies approximately between 4-6 GHz. The maximum gainof the LNA is 29.6 dB and average NF is 2.6 dB. The linearity

analysis shows the input referred P1dB and IIP3 of -25.07 dBm

and -13.47 dBm respectively. The two stage wideband LNA

consumes only 13.9 mA from a 1.5 V supply. It shows good

comparison with other LNAs designed for 4-6 GHz range with a

much higher gain and smaller NF.

I. INTRODUCTION

With the emergence of various communication standards,

the need for low cost and reconfigurable/wideband receiver

units is indispensable. The reconfigurable receivers usually

employ inductors for tuning to a specific frequency band and,

thus, occupy large area [1]-[3]. Wideband receivers havegained significant popularity during the past two decades since

they not only provide the flexibility of operation at various

frequencies simultaneously but can be made even without

inductors [4]-[5].

The low noise amplifier (LNA) is the main and first activeblock in any receiver. The performance metrics of a wideband

LNA are very critical compared to narrowband design.

Achieving high and flat gain with low noise figure (NF) is the

never-ending demand. This in conjunction with high linearity

and small power consumption makes the LNA design very

challenging. Several topologies for wideband LNAs have beenreported in literature, each trading off some parameter with the

other. The Distributed amplifiers are known for their largebandwidth but the gain is relatively small. The large area of

inductors limits their use in some applications, although NF

reduction techniques for distributed amplifiers have already

been proposed [6]. The Common Gate (CG) and resistivefeedback topologies are other ways of achieving wideband

behaviour but the former suffers from large NFmin and the

latter restricts the bandwidth to lower frequencies. The large

NF of CG LNA was worked out in [7] but NF could not go

below 2.5 dB. The resistive feedback topology suffers fromreduced bandwidth because the parasitic capacitances at the

input of the amplifier form low pass filter with the resistor and,

thus, degrade the response at high frequencies.

In this paper, we present the design of a wideband LNA

employing reactive elements similar to narrowband design to

achieve wideband input and output impedance matching. The

conventional cascode architecture has been used in

combination with reactive input network. Cascaded CS and

CG stages provide high gain and help in suppressing theMiller effect, thereby, rendering a better reverse isolation. Asecond cascode stage is also added to further increase the gain.

The conventional LNAs use a buffer for output impedance

matching (for measurement purpose) which degrades the gain

of the core LNA and increases power consumption. In our

design, the use of RLC combination at the output provides

wideband matching without trading-off the gain and power

consumption. A similar strategy has also been employed in [8]

for output impedance matching at the cost of gain.

The organisation of the paper is as follows. The wideband

LNA design theory is explained in Section II. Section III

discusses the layout of the LNA and post layout simulation

results are presented in Section IV. Finally the paper isconcluded in Section V.

II. THEORY AND ANALYSIS

In an LNA design, we need to optimize various

parameters such as gain, input and output impedances, NF,

linearity and power consumption. The source impedance for

good power match differs from the one at which noise figureis optimum [9]. Besides, there is an inverse relation between

gain and linearity of the LNA whereas power consumption

and linearity varies linearly with each other. It is apparent

from the above discussion that performance parameters of an

LNA are inter-related; therefore, optimizing one, degrades the

other. Hence, designing an LNA includes optimization of allof them or applying any technique to break the trade-off

between these quantities. It is almost impossible to achieve a

good LNA design just by altering the gate width and effective

gate voltages of the transistors [10].

Fig. 1 shows the schematic of our wideband LNA. Ingeneral, a common source (CS) amplifier with a degeneration

inductor offers a narrowband impedance matching inherently.

The generalized expression for the input impedance of a

degenerated CS transistor can be expressed as:

2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)

978-1-4673-2163-1/12/$31.00 2012 IEEE 125

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Figure 1. The 4-6 GHz Wideband LNA

(1)

In our design, a series combination of inductor (L1) and

capacitor (C2) is added before the degenerated cascode pair.As the input impedance of the LNA has a reactive part, the L1,

L2, C1 and C2 combination helps in resonating this reactive

part over multiple frequencies within the band of interest, thus,

providing larger bandwidth. The capacitor, C2, in parallel with

Cgs of M1 also helps to further increase the bandwidth. Anapproximate analysis for the input impedance of the LNA

gives Zinas

(2)

The biasing of the main transistor, M1, is carried out by

means of a current mirror, M3, whereas the cascoded

transistor M2 is biased directly through the Vdd supply. The

use of a cascode pair provides a high gain with good reverseisolation. To further increase the gain, a second cascode stage

is added. Additionally, this stage totally isolates the input and

output matching of the LNA. Inductors, L3 and L4, at the

drain are placed to provide exact supply voltage values to the

drain of the transistors, M2 and M5. The resistors, R3 and R4,

are added for stability and also help in achieving a high gain.

Besides, resistor R4 also helps in output impedance matching.

It is a very common practice to design an LNA with abuffer at output for output impedance matching during LNA

measurement. However, this buffer degrades the gain of core

LNA since the buffer gain is smaller than 1. In addition to gain

reduction, the buffer also consumes extra power. Taking this

fact into account we have utilized a series LC combination for

output matching as well. The desired wideband impedancematch is achieved through the combined impedance of C4, L4,

R4 and L5.

The high gain of the LNA is primarily because of the two

gain stages as shown in Fig. 1. However, the power

consumption is still comparable to single stage designs [11].

The overall voltage gain is obtained by evaluating the gain of

each stage of LNA individually and multiplying them together.

(3)

where Av1 and Av2 are the gains of first and second stage

respectively. The individual voltage gains are calculated bythe method presented in [12] as follows:

(4)

(5)

where Gm1, Rout1 and Gm2, Rout2are the transconductances and

output impedances of the first and second stage respectively.

Approximate analysis using the method mentioned above

renders (6)(9). It should be noted that Rout2is also the total

output impedance of our LNA.

The stability of LNA is estimated through Rollett's Stability

criteria (K factor and ) given by (10) and (11) [1 3]. In ourdesign, all critical resistors, inductors and capacitors are

adjusted for stability rendering an unconditionally stable

frequency response for the LNA.

(10)

Where

(11

(6)

(7)

(8)

(9)

M1

M3

M2

R1

VDD

M5

R2

biasV

OUTRF

INRF L1 C1C2

L2

L3

R3

C3

BIASR

M4

R4

L4C4 L5

Stage 1 Stage 2


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For achieving stability through the Rollett's Stability Criterion,

the K 1 shall be met incombination with 0 < B1 < 1 where

(12)The simulated K factor and B1f values for our LNA are

presented in section IV.

In our two staged wideband LNA, total NF is dominated bythe NF of first stage. Also, the higher the gain of the first stage,

the smaller will be the noise contribution of the next stage.

This is in accordance with the Friis formula for finding the NF

of the cascaded stages as in (13) [14].

(13)

Where F is the total noise factor, F1 and F2 are the noise

factors of first and second stage respectively and G1is the first

stage gain. The drain current noise, gate induced noise from

the cascode stage (M1 and M2) and thermal noise from the

resistor are the major noise contributors since the effect of

second stage noise factor will be smaller due to high gain of

the first stage. For input impedance matching at which both

NF and power match are optimum, we obtain a minimum NF

of 1.9 dB in the passband.

III. LAYOUT DESIGN

Cadence Virtuoso Layout XL is used for designing the

LNA layout. Physical verification checks including DRC,LVS, and QRC have been successfully performed using

Assura 1.8.0.1DM. The LNA is designed using standard 1.5 V

thin oxide transistors. On-chip MIM capacitors and parallel

spiral inductors are used for the design. The maximum and

minimum values of inductors used are 4.25 nH and 1.07 nHrespectively.

After complete layout design, post-layout simulations were

performed to check the effects of parasitics on LNA results.

The track widths were then adjusted to keep both, the parasitic

resistance and capacitance, optimum. This helped to obtain

better NF and bandwidth from the layout as well. Together

with this, large number of transistor fingers also contributed toa reduced NF. The total area of the chip is 1.26 mm

2whereas

the effective area of layout covers only 0.5 mm2

excluding

bond pads. Fig. 2 shows the layout of the LNA.

IV.SIMULATION RESULTS

All simulations of the LNA are performed in CadenceSpectre RF using IBM 0.13-m CMOS technology. The gatewidths of transistors M1, M2, M4 and M5 are all chosen to be

90-m through simulations. The diode connected transistor

M3 for biasing, is set for a gate width of 3-m. As a result,

bias voltage of 0.65 volts appears at the gate of M1. The gate

voltages of M2, M4 and M5 are 1.5, 0.6 and 1.5 voltsrespectively. The selected gate widths and biasing allow the

transistors to operate well in the saturation region, thereby,

obtaining maximum signal swing through the cascode pairs to

achieve maximum gain. With a power supply of 1.5 V, theLNA draws only 13.9 mA current.

For a bandwidth nearly equal to 2 GHz (~4-6 GHz), the

simulated input (S11) and output (S22) port reflection

coefficients achieve values better than -10 dB and -5 dB

respectively. The average forward gain (S21) and reverse

isolation (S12) are 25.5 dB and -74.5 dB respectively in thepassband. These parameters are plotted in Fig. 3.

The NF of the LNA is plotted in Fig. 4 which shows a

minimum NF of 1.9 dB at a frequency of 4.1 GHz. The

stability analysis of the LNA indicates both K >1 and B1f < 1

over a large frequency span. This clearly indicates the

unconditional stability of our LNA. Fig. 5 shows the combined

plot of both K and B1f. The linearity analysis is performed

using the two tone test. Since the LNA is wideband in nature,

two tones (5 GHz and 5.01 GHz) with spacing of 10 MHz are

selected. This is to ensure that any intermodulation product

does not oscillate the LNA under any condition. The resulting

third order intermodulation product frequency is identified andthe input power is swept from -40 dBm to 0 dBm. The IIP3

obtained is -13.47 dBm as plotted in Fig. 6. The input referred

P1dB is -25.07 dBm as shown in Fig. 7.

A comparison of our LNA with other state-of-the-art LNAs

of similar frequency range, bandwidth and technology nodes is

presented in Table I. It is apparent that the gain of our LNA is

substantially higher compared to other wideband LNAs with

slight degradation in linearity and power consumption. The

average gain of 25.5 dB is among the best values reported in

0.13-m CMOS technology for 4-6 GHz frequency range with

NF as small as 1.9 dB in the passband.

Figure 2. Layout of the LNA


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Figure 3. Simulated S-Parameters

Figure 4. Simulated NF (NF= 1.9 dB at 4.1GHz)

Figure 7. Input referred 1 dB Compression Point

(P1dB= -25.07 dBm)

TABLE I.COMPARSION OF SINGLE ENDED CMOSLNAS

Figure 5. Stability factors K and B1f

Figure 6. IIP3 of the LNA (IIP3= -13.47 dBm)

1Avg. in passband 2Min. in passband

V.CONCLUSION

A wideband LNA in the range 4-6 GHz has been designedin IBM 0.13-m CMOS technology. The wideband operationis achieved by using RLC networks both at the input andoutput. The two staged cascaded cascode topology provideshigh gain. The post layout simulation results depict forwardgain as high as 29.6 dB and NF as low as 1.9 dB in the

passband. The simulated input referred P1dB and IIP3 are -

25.07 dBm and -13.47 dBm respectively. The two staged LNAconsumes only 13.9 mA from a 1.5 V supply. Input and outputimpedances are matched to 50 with reverse isolation of -74.5 dB. The results show that our simulated LNA is similar in

performance to other wideband LNAs designed in this rangebut with a much higher gain and better NF. The summary ofthe results is presented in Table II.

2 3 4 5 6 7-30

-20

-10

0

10

20

30

40

Frequency (GHz)

S

-Parameters(dB)

S11

S21

S22

4 4.5 5 5.5 6

2

3

4

Frequency (GHz)

Noise

Figure(dB)

NF

-40 -35 -30 -25 -20 -15 -10 -5 0-15

-10

-5

0

5

10

Input Power (dBm)

OutputPower(dBm)

1dB/dB

Input referred P1dB

= -25.07 dBm

2 3 4 5 6 70

1000

2000

Kf

Frequency (GHz)

2 3 4 5 6 70.5

0.6

0.7

0.8

0.9

1

B1f

Kf

B1f

-40 -35 -30 -25 -20 -15 -10 -5 0-80

-60

-40

-20

0

20

Input Power (dBm)

OutputPow

er(dBm)

1dB/dB3dB/dB

IIP3= -13.47 dBm

Ref. No. [15] [16] [17] [18] This

work

Tech

(m)

0.18 0.18 0.18 0.18 0.13

S11

(dB)

< -10.5

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TABLE II. SUMMARY OF RESULTS

1Avg.

ACKNOWLEDGEMENT

The authors would like to thank High PerformanceComputing Centre, NED University of Engineering &

Technology, for the technical support and other facilities.

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