05 lc3 architecture

7/26/2019 05 LC3 Architecture

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CMPE12

5) LC-3 Architecture

(Textbooks Chapter 4-ish)

2CMPE12 Fall 2006 A. Di Blas (Orig. by C. Barzeghi)

The Stored-Program Computer

1943: ENIAC Hard-wired program -- settings of dials and switches.

1944: Beginnings of EDVAC -Electronic DiscreteVariable Automatic Computer

among other improvements, includes program stored in memory

1945: John von Neumann wrote a report on the stored-program computer,

known as the First Draft of a Report on EDVAC


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The basic structure proposed in the draftbecame known as the von Neumannmachine (or model).

This machine/model had five maincomponents:

1. the Central Arithmeticalpart, CA

2. the Central Controlpart, CC

3. the Memory, M, for both

instructions and data

4. the Input, I5. the Output, O

First Draft of a Report on EDVAC


Von Neumann Model*MEMORY

CONTROL UNIT

MAR MDR

IR

PROCESSING UNIT

ALU TEMP

PC

OUTPUT

MonitorPrinterLEDDisk

INPUT

KeyboardMouseScannerDisk

* A slightly modified version of Von Neumanns original diagram


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CISC vs. RISCCISC : Complex Instruction Set Computer

Lots of instructions of variable size, very memoryoptimal, typically less registers.

RISC : Reduced Instruction Set Computer Lessinstructions, all of a fixed size, more registers,optimized for speed. Usually called aLoad/Store architecture.


What is Modern

For embedded applications and forworkstations there exist a wide variety ofCISC and RISC and CISCy RISC and RISCyCISC.

Most current PCs use the best of bothworlds to achieve optimal performance.


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LC-3 Architecture

o RISC - only 15 instructions

o 16-bit data and address

o 8 general-purpose registers (GPR)

Plus 4 special-purpose registers:

o Program Counter (PC)

o Instruction Register (IR)

o Condition Code Register (CC)o Process Status Register (PSR)


Memory2kx marray of stored bits:

Address

unique (k-bit) identifier of location

LC-3: k = 16

Contents

m-bit value stored in location

LC-3: m = 16

Basic Operations:

LOAD

read a value from a memory location STORE

write a value to a memory location

0000000100100011010001010110

11011110

1111

00101101

10100010

address

contents


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Interface to Memory

How does the processing unit get data to/from memory?

MAR: Memory Address Register

MDR: Memory Data Register

To LOAD from a location (A):

1. Write the address (A) into the MAR.

2. Send a read signal to the memory.

3. Read the data from MDR.

To STORE a value (X) into a location (A):

1. Write the data (X) to the MDR.

2. Write the address (A) into the MAR.3. Send a write signal to the memory.

MEMORY

MAR MDR


Input and OutputDevices for getting data into andout of computer memory

Each device has its own interface,usually a set of registers like thememorys MAR and MDR

LC-3 supports keyboard (input) and monitor (output)

keyboard: data register (KBDR) and status register (KBSR) monitor: data register (DDR) and status register (DSR)

Some devices provide both input and output disk, network

The program that controls access to a device is usually called a driver.

INPUT

KeyboardMouseScannerDisk

OUTPUT

MonitorPrinterLEDDisk


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Instruction Fetch/Execute Cycle

In addition to input & output a program also:

Evaluates arithmetic & logical functions to determinevalues to assign to variable.

Determines the order of execution of the statements inthe program.

In assembly this distinction is captured in the notion of

arithmetic/logical, and control instructions.


Processing UnitFunctional Units ALU = Arithmetic/Logic Unit

could have many functional units.some of them special-purpose(multiply, square root, )

LC-3 performsADD, AND, NOT

Registers Small, temporary storage

Operands and results of functional units

LC-3 has eight registers (R0, , R7), each 16 bits wide

Word Size number of bits normally processed by ALU in one instruction

also width of registers

LC-3 is 16 bits

PROCESSING UNIT

ALU TEMP


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Control UnitControls the execution of the program

Instruction Register (IR) contains the current instruction.

Program Counter (PC) contains the addressof the next instruction to beexecuted.

Control unit: reads an instruction from memory

the instructions address is in the PC

interprets the instruction, generating signals that tell the othercomponents what to do

an instruction may take many machine cyclesto complete

CONTROL UNIT

IRPC


LC-3

Can youidentify the 5Von Neumanncomponents?


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Instructions

The instruction is the fundamental unit of work.

Specifies two things: opcode: operation to be performed

operands: data/locations to be used for operation

Three basic kinds of instructions: Computational instructions

Data-movement instructions

Flow-control instructions


Breaking down an instruction

ADD a, b, c

a b cADD

OpcodeDestination register

Source registers/immediate


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An instruction is encoded as a sequence of bits. (Likedata) Often, but not always, instructions have a fixed length, such

as 16 or 32 bits. Control unit interprets instruction:

generates sequence of control signals to carry out operation. Operation is either executed completely, or not at all.

A computers instructions and their formats is known asits Instruction Set Architecture (ISA).


Instruction encodingWhat meaning which bits have, depending on thesituation

Ex: in LC-3, the most-significant four bits containthe instructions OPCODE always.

The meaning of the other bits changes according to

the instruction.

Look up the textbook to find all 16 LC-3 instructionformat descriptions

15 14 13 12 0


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Ex: LC-3sADD Instruction

LC-3 has 16-bit instructions. Each instruction has a four-bit opcode, bits [15:12].

LC-3 has 8 registers(R0-R7) for temp. storage. Sources and destination ofADD are registers.

Add the contents of R2 to the contents of R6, and store theresult in R6.


Ex: LC-3s LDRInstructionLoad instruction read data from memory

Base + offset mode: add offset to base register - result is memory address

load from memory address into destination register

Add the value 6 to the contents of R3 to form a memoryaddress. Load the contents of that memory location to R2.


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Instruction Processing

Decode instruction

Evaluate address

Fetch operands from memory

Execute operation

Store result

Fetch instruction from memory


Six basicphasesof instruction processing:

F D EA OP EX S

NOTE:

Not all phases are needed by everyinstruction

All instructions will go through F and D atleast

Phases may take more than 1 machine cycle


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FETCH

Load next instruction (at address stored in PC)from memory into Instruction Register (IR).

Copy contents of PC intoMAR.

Send read signal to memory.

Copy contents ofMDRinto IR.

Then increment PC, so that it points to the nextinstruction in sequence.

PC becomes PC+1.

EA

OP

EX

S

F

D


DECODEFirst identify the opcode.

In LC-3, this is always the first four bits ofinstruction.

A 4-to-16 decoder asserts a control linecorresponding to the desired opcode.

Depending on opcode, identify other operandsfrom the remaining bits.

Example:

for LDR, last six bits is offset

forADD, last three bits is second sourceoperand

EA

OP

EX

S

F

D


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EVALUATE

ADDRESSFor instructions that require memory access,compute address used for access.

Examples: add offset to base register (as in LDR)

add offset to PC

add offset to zero

EA

OP

EX

S

F

D


FETCHOPERANDS

Obtain source operands needed toperform operation.

Examples: load data from memory (LDR)

read data from register file (ADD)

EA

OP

EX

S

F

D


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EXECUTE

Perform the operation, using the sourceoperands.

Examples: send operands to ALU and assertADD signal

do nothing (e.g., for loads and stores)

EA

OP

EX

S

F

D


STORE RESULT

Write results to destination.(register or memory)

Examples: result ofADD is placed in destination register

result of memory load is placed in destinationregister

for store instruction, data is stored to memory write address to MAR, data to MDR assert WRITE signal to memory

EA

OP

EX

S

F

D


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Changing the Sequence of

Instructions

In the FETCH phase, we increment the ProgramCounter by 1.

What if we dont want to always execute theinstruction that follows this one?

examples: loop, if-then, function call


We need special instructions that change thecontents of the PC.

These are the flow-control instructions:

jumps are unconditional -- they always changethe PC

branches are conditional -- they change the PConly if some condition is true (e.g., the result ofanADD is zero)

Flow-control instructions


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Ex: LC-3 JMP

Set the PC to the value contained in aregister. This becomes the address of thenext instruction to fetch.

Load the contents of R3 into the PC.


Recommended exercises:

Ex 4.5 (excluding point b3 for now)

Ex 4.7, 4.8, 4.10

Ex 4.13 and 4.16 (a little bit more advanced)

05 lc3 architecture

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