0.25 m m cmos electronics in cms

November, 2003 UK CMS Collaboration Meeting 1

0.25 m CMOS electronics in CMS

APV25 - readout chip for Si Trackerproduction wafer testing statusyield experiencesproduction QA results

MGPA - Multi-Gain Pre-Amplifier chip for ECALprototype design & performancecurrent status


APV25

8.1 mm

7.1m

m

pipeline

128x192

128

x pr

eam

p/sh

aper

AP

SP

+ 1

28:1

MU

X

pipe logicbias gen.

CAL FIFO

controllogic

digital header

128 analogue samples

APV O/P FramePeak Decon.

128 channel chip for analogue readout of AC coupled Si sensors

Main features 50 nsec. CR-RC amplifier 192 cell pipeline (up to 4sec latency + buffering) peak/deconvolution operating mode

peak mode -> normal CR-RC pulse shapedeconvolution -> single bunch crossing resolution

I2C slow control interface: bias registers, mode, latency ….bias registers, mode, latency …. On-chip CAL circuit: amplitude and delay programmableOn-chip CAL circuit: amplitude and delay programmable Rad-Hard: >10 MradsRad-Hard: >10 Mrads


Wafer TestingObjective

Identify faulty chips at wafer level with high level of fault coverage -> maximize yield of multi-chip hybrids

The task

360 viable sites/wafer

~ 73,000 chips required (+ spares) => ~ 300 wafers (yield dependent)

2 wafer/day throughput required to keep up with module production

generate wafer map for cutting co.

store all test information in database wafer id, chip#

8 inch APV wafer


Wafer Test HardwareMicromanipulator 8 inch semi–automatic probe station

VME based ADC (8 bits) RAL SeqSi 40 MHz CK/T1 CERN VI2C I/F

PC controls bothDAQ (VME)& probe-station (RS232)


Wafer Test Software

calibration pulseshapes – all chans

power supplycurrents

green lights =>all tests passed

channelpedestals

pipelinepedestals

(128 x 192)

calibrationgain

LabView based, aim for comprehensive fault coverage digital: chip addressing, stuck bits, pipeline control logic, ….. analogue: supply currents, all channels pulse shapes, all pipeline locations OK, noise, ……

channelnoise


Wafer Test Software (2)individual chip test subvi calledby supervisory vi

controls probe station movement

generates pass/fail wafer map

time to test 1 chip ~70s=> ~ 7 hrs/wafer=> 2 wafers/day

no.of good chipstotal available on wafer (360)

high yield wafer

= yield


Wafer Test – Yield Experiences

2001 0 9 81 Jan2002

1 24 ~302 21 ~10

March 3 25 79May 4 25 28

5 23 42Jan 6 25 ~ 0

7 23 37April 8 24 58

date lot # wafers yield [%]

2002

2003

Lot 1

Lot 3

(long story, cut short here)

problems seen as soon as production started

circular failure patterns => processingproblem (acknowledged by manufacturer)

other HEP designs also experiencing similarproblems

2002 actions to understand unsuccessful

major investigation launched February this year (following Jan deliveries)

- wafers from all problem lots sent for failure analysis (FA) - modified wafer test software – try to localize failures within chip - weekly phone conference set up involving manufacturer’s FA teams on 2 sites, IC & RAL, CERN coordinating team


Example Fault Diagnosis – Lot 4this wafer showed high power consumption failures – liquid crystal technique showed hotspots in pipeline control logic area

non-contacting vias found => transistors which should be off can float to on condition => high power consumption

separation between metal layers close to maximum allowed => points to possible problem with Inter-Level Dielectric (ILD) layer thickness control (etch time is fixed)

high ILD thickness and non-contacting vias also found on samples from other low-yield lots


FA Conclusions (mid 2003)

High ILD thickness appears to be common feature in low yield lots (APV25 and other designs)

High Q2 (capacitor metal) coverage, non-uniform metal layer coverage in some designs thought to becontributing factor (all metallization issues). Solution process has been tweaked (!!) to achieve lower ILD thickness for APV runs

Lessons learnt main one: good relationship with responsive manufacturer extremely valuable without we would still be in the dark – and still getting variable yields

debugging these kind of problems requires expert knowledge of process and special equipment (hot-spot analysis, de-layering, electron microscopy)


Wafer Test Yields Summary – to date

2001 0 9 81 engineering run

Jan 1 24 ~30 1st two production lots showed problems – manufacturerfound defects in silicide layer – these wafers replaced2 21 ~10

March 3 25 79 better yield

May 4 25 28 low yields again – major investigation launched involving manufacturer, CERN, other HEP teams with yield problems5 23 42

Jan 6 25 ~ 0 one-off: Failure Analysis showed lots of shorted tracks

7 23 37 on-going investigations show strong evidence that problemcaused by too thick dielectric between metal layersApril 8 24 58

June 9 19 90 1st production run with modified process

July 10 22 81

Aug. 11 12 76 experimental lot

Sept. 12 22 79

13 25 90

14 1 91

Oct. 15 24 91

16 25 90

very high yield sinceprocess modified to reduce inter-leveldielectric thickness

looks like problemsolved

date lot # wafers yield [%]

2002

2003

184 wafers (excluding lots 1, 2 & 4 - 8) , ~ 53,000 good chips


average pulse shapes for all pass chips (lots 1 – 5)normalised to max. pulse height (~ 13,000 chips) shows good pulse shape matching for all chips even without individual tuning (same set of bias parameters for every chip) not much wafer or lot dependence

Peak Mode DeconvolutionLot 1 Lot 1

Lot 4

Lot 5Lot 3

Lot 2

Lot 3 Lot 5

Lot 2 Lot 4

Wafer Test Results Analysis Example (1)


Wafer Test Results Analysis Example (2)

conclusions: close wafer:wafer and lot:lot matching

Supply Currents Channel Noise Channel Gain

~ small spread within a lot (~ 24 wafers)lot averages -> not much difference between lots


QA procedures (IC & Padova)Objective perform more detailed tests (including irradiation) on chips sampled from probed wafers after dicing. Cutting company picks 3 chips and returns them to us

(wafer test limited – time, electrical environment noisy, irradiation not feasible)

QA sample size initially 100% (chip from every wafer) decreasing to ~ 20% as confidence established

Procedure measure … irradiate (10 Mrads) … re-measure … … anneal (1 week @ 100oC) … re-measure

25 mm


QA Irradiation Setup

Identical facilities at Padova & IC

X-ray spectrum peak ~ 10 keV(Vtube=50 kV, Itube=10mA,150m Al filtration)

dose-rate calibration performed usingSi diodes, overall accuracy ~ 10% relative accuracy (Padova:IC) ~ 1%

10 Mrads takes ~ 14 hours


Chip QA measurement: Pre-rad


Chip QA measurement: 10 Mrads + Anneal


Example Chip QA measurement: Noise

decon (added C)

peak (added C)

decon baseline

peak baseline

conclusion: no QA problems observed so far


APV ConclusionsWafer probing production wafer probe test setup working well

throughput 2 wafers/day~ 53,000 good chips available for module production (~ 73,000 needed)

analysis of test data shows good matching between chips, wafers and lots yield problems observed on some lots now believed understood and solved

QA measurements automated measurement setup and protocol developed

measurements pre-rad, after 10 Mrads, after anneal good results from sampled lots so far, no surprises


The MGPA ECAL readout chipfor CMS

9th Workshop on Electronics for LHC Experiments, Amsterdam, 2003

Multi–Gain Pre-Amplifier - 0.25 m CMOS chip for CMS ECAL

MGPANew 0.25m VFE chip for ECAL

Prototype results as presentedat recent LECC conference

Minor modifications to prototype-> new version just submitted forengineering run


New ECAL VFE (Very Front End) Architecture

1

6

12

MGPA

12 bits

2 bits

LOGIC

Multi-channel ADCopto-electricbarrel: APDendcap: VPT

General approach use multiple gain ranges -> high resolution with only 12 bit ADC only transmit value for highest gain channel-in-range => have to take decision on front end

Previous architecture range decision taken in preamplifier (complex chip), followed by single channel commercial ADC

New architecture 3 parallel gain channels (MGPA), multi-channel ADC, range decision taken by logic in ADC chip use 0.25 m CMOS to take advantage of:

radiation hardnesssystem simplifications: single 2.5V supply, power savingsshort fabrication turnaround time, high yield, cheaper

Short timescale for development design begun mid 2002, submission early 2003, die received May 2003, packaged die since August

PbWO4

scint.


MGPA Target Specifications

Parameter Barrel End-Cap

fullscale signal 60 pC 16 pC

noise level 10,000e (1.6 fC) 3,500e (0.56 fC)

input capacitance ~ 200 pF ~ 50 pF

output signals(to match ADC)

differential 1.8 V, +/- 0.45 V around Vcm = (Vdd-Vss)/2 = 1.25 V

gain ranges 1, 6, 12

gain tolerance (each range)

+/- 10 %

linearity (each range)

+/- 0.1 % fullscale

pulse shaping 40 nsec CR-RC

pulse shape matching(Vpk-25)/Vpk

< +/- 1 % within and across gain ranges

Barrel/Endcap read out using APD/VPT different capacitance and photoelectric conversion factors

spec. review -> 3 gain ranges sufficient to deliver required performance -> MGPA design easier

Additional calibrate feature -> not precision but allows charge injection to each front end chip

Vpk-25 Vpk


MGPA Architecture

RF

charge amp.

RG1

diff. O/P stages

CF

VCM

CI

RI

gain stages

RI

DAC

I2C andoffset

generator

ext.trig.

1st stage RFCF = 40 nsec. (avoids pile-up) choose RFCF for barrel/endcap => 1 chip suits both RF dominant 1st stage noise source => independent of CIN

3 gain channels 1:6:12 set by resistors (on-chip) for linearity

differential current O/P stages external termination 2RICI = 40 nsec. => low pass filtering on all noise sources within chip

calibration facility prog. amplitude

I2C interface to programme: output pedestal levels enable calibration feature cal DAC setting

CCAL

RG2

RG3I/P

VCM

CI

RI

RI

VCM

CI

RI

RI

RFCF

i

i

i


Chip Layout

I2C

1st stage

highgainstage

diff. O/P stage

offset gen.

layout issues

gain channels segregated as much as poss. with separate power pads -> try to avoid inter-channel coupling

lots of multiple power pads

die size ~ 4mm x 4mm

packaged in 100 pin TQFP (14mm x 14mm)midgainstage

lowgainstage

diff. O/P stage

diff. O/P stage


Test Setup

PulseGen.

MGPA test board

ProgrammableAttenuator

True rmsmilli-voltmeter

Scope

diff. probe

priority given to measurements for barrel gain(60 pC fullscale)


Pulse Shape MeasurementsV

olts

time [nsec]

low gain range mid gain range high gain rangedifferential O/P signals (diff. probe)

0 – 60 pC, 33 steps

saturation in mid and high gain ranges

but no obvious signs of distortion in lower gain ranges => effective gain channel segregation in layout

gain ratios 1 : 5.6 : 11.3 (c.f. 1 : 6 : 12)

linea

r ran

ge


Linearity: High Gain Channel

spec.

linea

rity

[% fu

llsca

le]

Linearity [% fullscale] = peak pulse ht. – fit (to pk pulse ht) X100 fullscale signal

relative signal size

linearity within (or close to) specfor a range of gain stage bias currents

=> not v. sensitive to bias conditions

5.4 pC

similar results for mid and low gain channels


Pulse Shape Matching

normalise

to max pulse ht.

pulse shape matching important within and across gain ranges

to quantify use pulse shape matching factor, PSMF = Vpk-25 Vpk

VpkVpk-25pulse shapes for all 3 gain ranges (11 steps / range)

all 33 pulse shapes overlaid

puls

e he

ight

[Vol

ts]

time [nsec.]


Pulse Shape Matching

spec.

Pulse shape matching [%] = (PSMF – Average PSMF) x 100Average PSMF

(Average PSMF = average over all pulse shapes and all 3 gain ranges)

relative signal size [1=fullscale]

puls

e sh

a pe

mat

c hin

g [%

]

pulse shape matching close tospec. (+/- 1%)


Noise

Barrel (33 pF // 1.2k)

measured simulation

(~20pF) +180pF 200 pF

high 7,000 7,850 6,200

mid 8,250 9,100 8,200

low ~ 28,000 ~ 28,000 35,400

weak dependence on input capacitance as expected

higher electronic noise not significant for low gain range gain stage noise dominates for this range

estimated errors:

~ 10% high and mid-gain ranges, ~20% low gain range

Endcap (8.2 pF // 4k7)

measured simulation

(~20 pF) + 56 pF 50 pF

2,900 3,050 2,700

3,300 3,450 3,073

~ 8,500 ~ 8,500 9,800

within spec. < 10,000 (barrel) < 3,500 (endcap)


Radiation Tests

~ 3% reduction in gain after 5 Mrads (2 x worst case)

no measurable effect on noise

(10 keV X-rays (spectrum peak) , dosimetry accurate to ~ 10%, doserate ~ 1 Mrad/hour, no anneal)

low mid high

pre-rad5 Mrads


On-chip Calibration Feature

ext.10pF

MGPA I/P

Vol

ts

nsec.

simple DAC allows programmable (I2C)amplitude charge injection -> range of signal sizes for each gain range

external trigger required

allows functional verificationduring chip screening and in-system

I2C

externaledgetrigger


MGPA ConclusionsFirst iteration successfulAnalogue performance good

gain, linearity, pulse shape matching, noise all within or v.close to spec.

rad-hard as expected

System testsmultiple chips mounted on VFE cards, with multi-channel ADCsused with APDs/crystals in beam test -> encouraging performance

Next iterationminor design changes

pinout (requested to assist VFE card layout)I2C register default values (chip biases up close to nominal operating point on switch-on)current reference to bias generator included on-chip

Already submitted (17th Nov.) for engineering runexpect wafers early in New Year-> enough chips for Supermodule calibration in 2004


Deep Sub-Micron Future*0.25 m CMOS turned up just in time (~1998) – where would we be without it? in CMS everything (I think) from HCAL in now 0.25m - Pixel, Tracker, ECAL readout and control ASICs

0.25m technology will not be around forever (maybe until 2007?) 0.13m next logical step (have to follow industry – skip 0.18m)

need special relationship with (and goodwill of) technology supplier prototypes -> production NOT a smooth ride (e.g. APV yield experiences) understanding yield issues requires close collaboration with foundry HEP projects need relatively few wafers c.f. foundry capacity

0.13m offers possible improvements in: power reduction: most of tracker material budget electronics related (power cabling, cooling) higher speed and circuit density, more rad-hard, ….

also challenges -> R&D required circuit techniques to cope with reduced supply headroom (1.3V) radiation effects (ionizing and SEE) generating and characterising digital circuit libraries (and analogue?) modelling more complicated (more metal layers -> complex parasitic couplings)

undisputable statement: LHC (and future HEP) experiments not possible without ASICs

*see Sandro Marchioro’s talk at LECC’03 LHC electronics workshop

0.25 m m cmos electronics in cms

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