01-08 dip switches on rnc components

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8DIP Switches on RNC ComponentsAbout This Chapter

This part describes the DIP switches on the RNC subracks and RNC boards.

8.1 DIP Switches on RNC Subracks

The DIP switch on the RSS subrack is the same as that on the RBS subrack. The DIP switches

are used to set the subrack number.

8.2 DIP Switches on the AEUa Board

The AEUa board has ten DIP switches. The ten DIPswitches are S1, S2, S3, S4, S5, S6, S7, S8,

S9, and S10.

8.3 DIP Switches on the AOUa Board

The AOUa board has two DIP switches which are both SW1. The two DIP switches controls

the mode setting of the two STM-1/OC-3 optical ports.

8.4 DIP Switches on the PEUa Board

The PEUa board has ten DIP switches. The ten DIP switches are S1, S2, S3, S4, S5, S6, S7, S8,

S9, and S10.

8.5 DIP Switch on the MDMC Board

The MDMCboard provides one DIP switch. The DIP switch is S2.

8.6 DIP Switches on the PFCU Board

The PFCU board has one DIP switch. The DIP switch is SW1 and consists of four bits. The DIPswitch is used to set the address of the PFCU board.

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Hardware Description 8 DIP Switches on RNC Components

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8.1 DIP Switches on RNC Subracks

The DIP switch on the RSS subrack is the same as that on the RBS subrack. The DIP switchesare used to set the subrack number.

Location of the DIP switches

The DIP switches are located on the back of the RSS subrack and the RBS subrack, as shown

in 3.1 Components of the RNC Subrack.

Appearance of DIP Switch

Figure 8-1shows the area of the DIP switch.

Figure 8-1DIP switch

Description of DIP Switches

The DIP switch on the RNC subrack has eight bits. The higher the bit is, the more significant it

is. If the bit is set to ON, it indicates 0. If the bit is set to OFF, it indicates 1. Table 8-1provides

the definitions of the bits.

Table 8-1Bits of the DIP switch

Bit Meaning

1, the least significantbit

Subrack number setting bit

2 Subrack number setting bit




6 Parity check bit

7 Not used in the RNC and is usually set to 0

8 DIP Switches on RNC Components

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Hardware Description

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Bit Meaning

8, the most significant

bit

l If bit 8 is set to 0, the SCUa board can be started only by the

loading on the OMUa board.

l If bit 8 is set to 1, a loading request is sent to the OMUa boardbefore the SCUa board is started. If the OMUa board responds

within 30 s, the SCUa board is started by the loading on the OMUa

board. If the OMUa board fails to respond within 30 s, the SCUa

board is started by the loading on Flash.

For RNC, bit 8 is usually set to 1.

Setting of DIP switches

Table 8-2shows the setting of the DIP switches for the RNC subracks. Subrack 0 is an RSS

subrack. Subracks 15 are RBS subracks.

Table 8-2Setting of DIPswitches for RNC subracks

SubrackNumber

Bit

1 2 3 4 5 6 7 8

Subrack 0 ON ON ON ON ON ON ON OFF

Subrack 1 OFF ON ON ON ON OFF ON OFF

Subrack 2 ON OFF ON ON ON OFF ON OFF

Subrack 3 OFF OFF ON ON ON ON ON OFF

Subrack 4 ON ON OFF ON ON OFF ON OFF

Subrack 5 OFF ON OFF ON ON ON ON OFF

8.2 DIP Switches on the AEUa Board

The AEUa board has ten DIP switches. The ten DIP switches are S1, S2, S3, S4, S5, S6, S7, S8,

S9, and S10.

Allocation of DIP Switches on PEUa BoardFigure 8-2shows the DIP switches on the AEUa board.

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Figure 8-2DIP switches on the AEUa board

(1) Sub-board (2) Bottom plate

CAUTION

As shown in Figure 8-2, the DIP switches are located on the obverse side of the sub-board which

faces the bottom plate and is installed on the bottom plate. Therefore, the DIP switches must be

set before the sub-board is installed on the bottom plate. The part which is marked with dotted

lines in Figure 8-2cannot be seen directly.


DIP switches S1S8 are used to set the TX end and the RX end of the E1/T1/J1 cables 031 to

be grounded or not grounded. DIP switch S9 is used to set the FPGA loading mode. DIP switch

S10 is used to set the work modes such as E1 balanced mode, E1 unbalanced mode, T1 mode,and J1 mode. For details, refer to Table 8-3.


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Table 8-3DIP switches on the AEUa board

DIPSwitch

Bit Description Status Meaning

S1 18 RX ground switch of E1s/T1s/J1s

2431

ON Setting

work mode

to E1

unbalanced

mode

OFF Setting

work mode

to other

modes

S2 18 TX ground switch of E1s/T1s/J1s 24

31

ON Setting

work mode

to E1

unbalanced

mode

OFF Setting

work mode

to other

modes

S3 18 RX ground switch of E1s/T1s/J1s

1623

ON Setting

work mode

to E1unbalanced

mode

OFF Setting

work mode

to other

modes


23

ON Setting

work mode

to E1

unbalancedmode

OFF Setting

work mode

to other

modes

S5 18 RX ground switch of E1s/T1s/J1s 0

7

ON Setting

work mode

to E1

unbalanced

mode

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DIPSwitch


OFF Setting

work mode

to other

modes


7

ON Setting

work mode

to E1

unbalanced

mode

OFF Setting

work mode

to othermodes

S7 18 RX ground switch of E1s/T1s/J1s 8

15

ON Setting

work mode

to E1

unbalanced

mode

OFF Setting

work mode

to other

modes


15

ON Setting

work mode

to E1

unbalanced

mode

OFF Setting

work mode

to other

modes

S9 12 DIP switch for setting FPGA loadingmode. It consists of two bits.

(ON, ON) Settingloading

mode to

JTAG

configurati

on

(OFF, OFF) Setting

loading

mode to

CPU slave

parallel


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DIPSwitch


configurati

on

S10 12 DIP switch for setting work mode. It

consists of two bits.

(ON, ON) Setting

work mode

to E1

unbalanced

mode

(OFF, ON) Setting

work mode

to E1

balanced

mode

(ON, OFF) Setting

work mode

to T1 mode

(OFF, OFF) Setting

work mode

to J1 mode

NOTE

l If signals are transmitted in E1 unbalanced mode, the signals are transmitted through the 75-ohm coaxialcable and the RX end of the cable is grounded, that is, the corresponding DIP switch is set to ON. If

signals are transmitted in other modes, the signals are transmitted through the 120-ohm twisted pair

cable and the RX end of the cable is not grounded, that is, the corresponding DIP switch is set to OFF.

l By default, all the DIP switches are set for the transmission in E1 balanced mode and the loading mode

of CPU slave parallel configuration. That is, all bits of S1S9 are set to OFF. Bit 1 of S10 is set to OFF

and bit 2 of S10 is set to ON.

l Ensure that the matching between the different types of DIP switches is correct.

8.3 DIP Switches on the AOUa Board

The AOUa board has two DIP switches which are both SW1. The two DIP switches controlsthe mode setting of the two STM-1/OC-3 optical ports.

Allocation of DIP Switches on PEUa Board

Figure 8-3shows the DIP switches on the AOUa board.

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Figure 8-3DIP switches on the AOUa board


Table 8-4describes the switches on the AOUa board.

Table 8-4DIP switches on the AOUa board

DIP Switch Bit Status Meaning

S1 12 (ON, ON) Setting loading mode

to JTAG

configuration

(OFF, OFF) Setting loading mode

to CPU slave parallel

configuration


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3 ON Setting work mode to

T1 mode

OFF Setting work mode toE1 mode

4 ON Setting the mapped

path to AU3.

OFF Setting the mapped

path to AU4.

5 ON Setting the

information structure

to TU11.

OFF Setting theinformation structure

to TU12.

6 ON SONET

OFF SDH

7 Reserved

8 Reserved

NOTE

All the bits are set to OFF by default.

8.4 DIP Switches on the PEUa Board

The PEUa board has ten DIP switches. The ten DIP switches are S1, S2, S3, S4, S5, S6, S7, S8,

S9, and S10.

Allocation of DIP Switches on PEUa Board

Figure 8-4shows the DIP switches on the PEUa board.

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Figure 8-4DIP switches on the PEUa board

(1) Sub-board (2) Bottom plate

CAUTION

As shown in Figure 8-4, the DIP switches are located on the obverse side of the sub-board which

faces the bottom plate and is installed on the bottom plate. Therefore, the DIP switches must be

set before the sub-board is installed on the bottom plate. The part which is marked with dotted

lines in Figure 8-4cannot be seen directly.


DIP switches S1S8 are used to set the TX end and the RX end of the E1/T1/J1 cables 031 to

be grounded or not grounded. DIP switch S9 is used to set the FPGA loading mode. DIP switch

S10 is used to set the work modes such as E1 balanced mode, E1 unbalanced mode, T1 mode,and J1 mode. For details, refer to Table 8-5.


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Table 8-5DIP switches on the PEUa board

DIPSwitch


S1 18 RX ground switch of

E1s/T1s/J1s 2431

ON Setting work

mode to E1

unbalanced

mode

OFF Setting work

mode to other

modes

S2 18 TX ground switch of

E1s/T1s/J1s 2431

ON Setting work

mode to E1

unbalanced

mode

OFF Setting work

mode to other

modes


E1s/T1s/J1s 1623

ON Setting work

mode to E1

unbalanced

mode

OFF Setting work

mode to othermodes


E1s/T1s/J1s 1623

ON Setting work

mode to E1

unbalanced

mode

OFF Setting work

mode to other

modes


E1s/T1s/J1s 07

ON Setting work

mode to E1unbalanced

mode

OFF Setting work

mode to other

modes


E1s/T1s/J1s 07

ON Setting work

mode to E1

unbalanced

mode

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DIPSwitch


OFF Setting work

mode to other

modes


E1s/T1s/J1s 815

ON Setting work

mode to E1

unbalanced

mode

OFF Setting work

mode to other

modes


ON Setting work mode to E1

unbalanced

mode

OFF Setting work

mode to other

modes

S9 12 DIP switch for setting

FPGA loading mode. It

consists of two bits.

(ON, ON) Setting loading

mode to JTAG

configuration

(OFF, OFF) Setting loadingmode to CPU

slave parallel

configuration

S10 12 DIP switch for setting

work mode. It consists of

two bits.

(ON, ON) Setting work

mode to E1

unbalanced

mode

(OFF, ON) Setting work

mode to E1

balanced mode

(ON, OFF) Setting work

mode to T1 mode

(OFF, OFF) Setting work

mode to J1 mode


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NOTE

l If signals are transmitted in E1 unbalanced mode, the signals are transmitted through the 75-ohm coaxial

cable and the RX end of the cable is grounded, that is, the corresponding DIP switch is set to ON. If

signals are transmitted in other modes, the signals are transmitted through the 120-ohm twisted pair

cable and the RX end of the cable is not grounded, that is, the corresponding DIP switch is set to OFF.l By default, all the DIP switches are set for the transmission in E1 balanced mode and the loading mode

of CPU slave parallel configuration. That is, all bits of S1S9 are set to OFF. Bit 1 of S10 is set to OFF

and bit 2 of S10 is set to ON.

l Ensure that the matching between the different types of DIP switches is correct.

8.5 DIP Switch on the MDMC Board

The MDMC board provides one DIP switch. The DIP switch is S2.

Figure 8-5shows the DIP switch on the MDMC board.

Figure 8-5DIP switch on the MDMC board

With four bits, the DIP switch S2 is used to set the address of the WDMB.

To set the address, pull out the WDMB as described in the Replacing an MDMC Board. Then,

set S2 as listed in Table 8-6.

Table 8-6DIP switch on the WDMB


S2 1, the most

significant bit

ON 0

2 ON 0

3 ON 0

4, the least

significant bit

ON 0

CAUTION

In the RNC, the address of the MDMC board is 0 by default. Therefore, the DIP switch on the

MDMC board must be set as described in Table 8-6.

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8.6 DIP Switches on the PFCU Board

The PFCU board has one DIP switch. The DIP switch is SW1 and consists of four bits. The DIP

switch is used to set the address of the PFCU board.

Figure 8-6shows the DIP switch on the PFCU board.

Figure 8-6DIP switch on the PFCU board

To set the address, pull out the fan box. Then, set the DIP switch as described in Table 8-7. For

how to pull out the fan box, refer to Replacing an RNC Fan Box. After the setting, the address

of the PFCU board is 1.

Table 8-7DIP switch on the PFCU board


SW1 1, the least significant bit OFF 1

2 ON 0

3 ON 0

4, the most significant bit ON 0


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01-08 dip switches on rnc components

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