0 spi-3 physical layer v5

IntroductionThe SPI-3 Physical (PHY) Layer LogiCORE™ IP provides acomplete, pre-engineered solution that is fully compatiblewith the OIF-SPI3-01.0 System Packet Interface Level-3implementation agreement. This fully verified solutionimplements the SPI-3 PHY Layer interface, which inter-connects with SPI-3 Link Layer devices.

Features• Configurable interface data widths: 8-bit, 16-bit,

and 32-bit

• Byte-level and Packet-level transmit flow control configuration options

• Supports 1 to 256 addressable channels

• Fully parameterizable internal FIFO: Depth ranges from 16 to 4096 entries implemented in user- selectable block RAM or distributed memory

• LocalLink user interface allows easy interconnection to other LocalLink-compliant interfaces

• Programmable RX pause value of 0 or 2 cycles

• Greater than 125MHz packet interface supported in Virtex® families; greater than 104MHz packet interface supported in Spartan® families

0

SPI-3 Physical Layer v5.2

DS339 April 24, 2009 0 0 Product Specification

LogiCORE™ IP Facts

Core Specifics

Supported Device Family

Virtex-5, Virtex-4, Spartan-3E,Spartan-3,Spartan-3A/3AN

Resources Used1 I/O LUTs FFsBlock RAMs

Slices2

Tx Core (8-bit) 24 211 234 1 182

Tx Core (32-bit) 50 222 313 2 230

Rx Core (8-bit) 16 273 272 1 220

Rx Core (32-bit) 42 363 404 2 345

Provided with Core

DocumentationProduct Specification

Getting Started Guide

Design File Formats

VHDL and Verilog

Constraints File User Constraints File (UCF)

Verification VHDL and Verilog Test Bench

Instantiation Template

VHDL and Verilog Wrapper

Design Tool Requirements

Xilinx Implementation Tools

ISE® v11.1

SimulationMentor Graphics® ModelSim® v6.4b

Cadence® IUS v8.1-s009

Synthesis XST, Synplify®

Support

Provided by Xilinx, Inc. @ www.xilinx.com/support

1. Resources statistics are for a core configured withPacket-level transfer control and a 512-deep blockRAM FIFO.

2. Slice counts obtained with area groups placed oneach core.

- DISCONTINUED PRODUCT -

DS339 April 24, 2009 www.xilinx.com 1Product Specification

© 2005-2009 Xilinx, Inc., XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

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ApplicationsThe SPI-3 PHY Layer interface enables the interconnection of physical layer devices to link layerdevices. Figure 1 illustrates the SPI-3 PHY Layer cores in a typical physical layer application.

Feature SummaryThe SPI-3 PHY Layer Receive (Rx) and Transmit (Tx) core features are defined in the sections that fol-low.

Receive Core Features• Data Bus Width. The data bus width supported by the SPI-3 PHY Layer core includes an 8-bit and

32-bit data path implementation for OIF-SPI3-01.0 compliance. An additional 16-bit data path implementation is provided for additional compatibility beyond the OF-SPI-301.0 standard.

• Maximum Burst Size. The Receive core implements a maximum burst size of 256 bytes in a manner that is transparent to the User Interface. The Receive core breaks up transfers larger than 256 bytes by asserting the start of transfer signal and reasserting the address.

• Programmable Pause. The Receive core supports a programmable minimum pause of 0 or 2 clock cycles between transfers. A pause of 0 clock cycles maximizes the throughput of the interface. A pause of 2 clock cycles allows the Link Layer device processing time between transfers.

• Optionally Independent Clock Domains. The Receive core is provided with the option of using independent clock domains used on the SPI-3 Packet Interface and the User Interface.

Transmit Core Features• Data Bus Width. The data bus width supported by the SPI-3 PHY Layer core includes an 8-bit and

32-bit data path implementation for OIF-SPI3-01.0 compliance. An additional 16-bit data path implementation is provided for additional compatibility beyond the OF-SPI3-01.0 standard.

Figure Top x-ref 1

Figure 1: SPI-3 PHY Layer Block Diagram

SPI-3 PHY Core

PHY Rx

SPI-3 Link LayerSPI-3

Interface

PHY Tx

Data

Data

PHYDevice

PHYDevice

PHYDevice

.

.

.

PHYDevice

UserInterface

Flow Control

Data

Data

Flow Control

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DS339 ApriProduct Sp


• Byte-Level and Packet-Level Transmit Flow Control Modes. A common transfer control interface is provided on the User Interface, allowing the user to design with a common interface and choose the flow control mode without altering the design. Byte-level mode lets the Link Layer device have direct access to the transmit packet available status of all supported port addresses. In Packet-level mode, the transmit packet available status is transmitted over a single signal, reducing the connection count between the Physical and Link Layer devices.

• 1 to 256 Supported Port Addresses. 1 to 256 port addresses are supported through the CORE Generator™ GUI, allowing for a wide range of flow control information to be reported. Based on the number of addresses required, a core with optimal architecture is generated.

• Parity Error Checking. A parity check is performed independently on the address and the data received on the SPI-3 Packet Interface. Any parity mismatches are detected and flagged on an error bus on the User Interface.

• Optionally Independent Clock Domains. The Transmit core is provided with the option of using independent clock domains on the SPI-3 Packet Interface and the User Interface.

Functional OverviewThe SPI-3 PHY Layer solution consists of two modules—the Receive core and the Transmit core. TheSPI-3 PHY Layer Receive core implements the SPI-3 Packet Interface and is responsible for generatingdata provided on the RDAT signal; the SPI-3 PHY Layer Transmit core implements the SPI-3 PacketInterface and is responsible for processing incoming data on the TDAT signal.

Receive Core

The Receive (Rx) core transmits 8-bit, 16-bit, or 32-bit data on the SPI-3 Packet Interface by processingand formatting 8-bit, 16-bit, or 32-bit data words from the User Interface. In addition to data processingand formatting, the Receive core is responsible for error detection as well as ensuring adherence to theSPI-3 protocol.

The Receive core has two primary interfaces: the SPI-3 Packet Interface and the User Interface. Figure 2shows the Receive core input and output signals, both described in the Core Interfaces section.

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Transmit Core

The Transmit (Tx) core receives 8-bit, 16-bit, or 32-bit data on the SPI-3 Packet Interface and transmits8-bit, 16-bit, or 32-bit data words on the User Interface. In addition to data processing and formatting,the Transmit core is responsible for generating flow control as well as status and error detection.

The Transmit core has two primary interfaces: the SPI-3 Packet Interface and the User Interface. In addi-tion to data processing interfaces, the Transmit core has an additional Transmit Packet Available Inter-face on the SPI-3 Transmit Interface, and a FIFO Status Interface on the User Interface. Figure 3 showsthe Transmit core input and output signals, both described in the Core Interfaces section.

Figure Top x-ref 2

Figure 2: SPI-3 PHY Layer Receive Core

D = Data WidthM = Mod Width

SPI-3 PHY Rx Core

RST

PHY RxFIFO

PHY RxSPI-3 Transmit

RX_CLK

RX_SRC_RDY

RX_DST_RDY

RX_SOF

RX_EOF

RX_ADDR[7:0]

RX_DATA[D-1:0]

RX_REM[M-1:0]

RX_ERR

RFCLK

RENB

RDAT[D-1:0]

RPRTY

RVAL

RSOP

REOP

RERR

RMOD[M-1:0]

RSX

PHY RxSPI-3 Transmit


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Core InterfacesThis section describes the SPI-3 architecture and defines the interface signals on the Receive and Trans-mit cores.

• User Interface. On both the Receive and Transmit cores, the User Interface implements the Xilinx LocalLink standard, providing a simple, flexible way to transmit and receive packets. The User Interface consists of a unidirectional data bus with control signals that allow the user application to stall data transfer.

• SPI-3 Packet Interface. On the Receive core, the SPI-3 Packet Interface connects to the reciprocal SPI-3 Packet Interface on the PHY Layer device; on the Transmit core, the SPI-3 Packet Interface connects to reciprocal SPI-3 Packet Interface on the PHY Layer device.

Figure Top x-ref 3

Figure 3: SPI-3 PHY Layer Transmit Core

D = Data WidthM = Mod Width

T = Threshold WidthC = Number of Channels

SPI-3 PHY Tx Core

RST

PHY TxFIFO

PHY TxSPI-3 Recieve

TX_CLK

TX_SRC_RDY

TX_DST_RDY

TX_SOF

TX_EOF

TX_ADDR[7:0]

TX_DATA[D-1:0]

TX_REM[M-1:0]

TX_ERR

TFCLK

TENB

TDAT[D-1:0]

TPRTY

TSOP

TEOP

TERR

TMOD[M-1:0]

TSXTX_ERRBUS[7:0]

TX_AF[C-1:0] PTPA

TADR[7:0]

STPA

DTPA[C-1:0]

TX_SOB

TX_AF_WE

TX_AF_MASK[C-1:0]

TX_FIFO_AF

Static Configuration Signals

FIFO StatusPHY Tx

SPI-3 FlowControl


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Receive Core Interfaces

The Receive core receives data from the User Interface and processes the data for transmission on theSPI-3 Packet Interface. The User Interface and the SPI-3 Packet Interface operate on optionally indepen-dent clock domains.

SPI-3 Packet Interface

Table 1 defines the SPI-3 Packet Interface signals of the Receive core. The SPI-3 Packet Interface con-nects to the reciprocal SPI-3 Packet Interface on the Link Layer device.

Table 1: SPI-3 Packet Interface: Receive Core

Signal Name Direction Description

RFCLK INReceive Clock: Used to synchronize data transfer transactions between the Link Layer device and the PHY Layer device. All SPI-3 Packet Interface signals are synchronous to the rising edge of this clock.

RVAL OUT

Receive Data Valid: Indicates the validity of the receive data signals. RVAL is low between transfers and when RSX is asserted; it is also low when the PHY pauses a transfer. When a transfer is paused by holding RENB high, RVAL will hold its value unchanged, although no new data will be present on RDAT until the transfer resumes.When RVAL is high, the RDAT, RMOD, RSOP, REOP, and RERR signals are valid. When RVAL is low, RDAT, RMOD, RSOP, REOP, and RERR signals are invalid and must be disregarded. The RSX signal is valid when RVAL is low.

RENB IN

Receive Read Enable: Used to control the flow of data from the Receive core. The RENB signal may be deasserted at anytime if the Link Layer device is unable to accept data from the Receive core.When RENB is sampled low by the Receive core, the RDAT, RPRTY, RMOD, RSOP, REOP, RERR, RSX, and RVAL are updated on the following rising edge of RFCLK.When RENB is sampled high by the Receive core, the RDAT, RPRTY, RMOD, RSOP, REOP, RERR, RSX, and RVAL signals will remain unchanged on the following rising edge of RFCLK.

RDAT[D-1:0] OUT

Receive Packet Data Bus: The RDAT bus carries the packet data that has been written to the User Interface, as well as the in-band port address of the packet data. Data is transmitted in big endian order on RDAT; for example, when the width of the data bus is 32-bits, bit 31 is transmitted first and bit 0 is transmitted last.

RPRTY OUTReceive Parity: Indicates the parity calculated over the RDAT bus. The Receive core expects odd parity.

RMOD[M-1:0] OUT

Receive Word Modulo: Indicates the number of valid bytes of data presented on RDAT. The RMOD bus should always be all zero, except during the last transfer of a packet on RDAT. When REOP is asserted, the number of valid packet data bytes on RDAT is specified by RMOD. When an 8-bit interface is used, the RMOD signal is not present.

RSOP OUTReceive Start of Packet: Used to delineate the packet boundaries on the RDAT bus. When RSOP is high, the start of the packet is present on the RDAT bus.


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Figure 4 illustrates a sample operation of the SPI-3 Packet Interface transmitting two complete packets.The first packet is initiated after the rising edge of the first RFCLK, when RENB is sampled low. TheReceive core drives RVAL low on the second clock cycle, and asserts RSX while providing the in-bandport address of the current packet, A0, on RDAT[7:0]. For the following three clock cycles packet datais transmitted by the Receive core asserting RVAL and driving RDAT with valid packet data, D0, D1, andD2.

After the fifth clock cycle, the Receive core asserts REOP and signals RMOD appropriately to indicate theremaining valid data, D3, for packet in progress. The following cycle, a transfer to a new port addressis initiated with the Receive core providing an in-band address of A1 and completing seven valid cyclesof data transfer.

REOP OUT

Receive End of Packet: Used to delineate the packet boundaries on the RDAT bus. When REOP is high, the end of the packet is present on the RDAT bus. When a 32-bit or 16-bit interface is used, RMOD indicates then number of valid packet bytes on RDAT when REOP is asserted.

RERR OUTReceive Error Indicator: Indicates that the current packet is in error. RERR shall only be asserted when REOP is asserted.

RSX OUT

Receive Start of Transfer: Indicates when the in-band port address is present on the TDAT bus. When TSX is asserted, the value of TDAT[7:0] is the address of the packet data. Subsequent data transfers on the TDAT bus will be from the port specified by this in-band address. If the address changes, TSX will be asserted at the beginning of the transfer. TSX will also interrupt a transfer and assert if the 256 byte maximum is reached, and it will then resume the transfer. TSX is considered valid only when TENB is deasserted.

Figure Top x-ref 4

Figure 4: SPI-3 Packet Interface: Transmit Two Full Packets

Table 1: SPI-3 Packet Interface: Receive Core (Continued)


A1 B0 B1 B2

REOP

RSOP

RERR

RVAL

RFCLK

RMOD

RENB

RDAT

RPRTY

RSX

D0

MM

A0 D1 D2 D3 B3 B4 B5 B6


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Figure 5 illustrates a sample operation of the SPI-3 Packet Interface transmitting a complete packetusing flow control signals. After the RENB signal has been sampled low, the Receive core transmits 3valid cycles on the SPI-3 Packet Interface. After transmitting data word D1, the Receive core stalls theSPI-3 Packet Interface for one cycle by deasserting the RVAL signal. The following clock cycle, RVAL isreasserted, and the Receive core continues transmitting data. Following the successful transmission ofD3, the Link Layer device has deasserted the RENB signal, halting the Receive core from transmittingadditional data. Two clock cycles later, the Link Layer device reasserts RENB, and data transmissioncontinues until the end of the packet is transmitted.

Figure 6 illustrates a sample operation similar to that shown in Figure 4; however, the system shown inFigure 6 is configured with a programmable pause value of 2 clock cycles, allowing the Link Layerdevice time to process the transaction further after a REOP is received. In this example, the Link Layerdevice does not deassert RENB on reception of the REOP, allowing the Receive core to continue trans-mission.

Figure Top x-ref 5

Figure 5: SPI-3 Packet Interface: Transmit Packet with Flow Control

Figure Top x-ref 6

Figure 6: SPI-3 Packet Interface: Programmable Pause of Two Clock Cycles

D4

REOP

RSOP

RERR

RVAL

RFCLK

RMOD

RENB

RDAT

RPRTY

RSX

D0

M

A0 D1 D2 D3 D5 D6 D7 D8

REOP

RSOP

RERR

RVAL

RFCLK

RMOD

RENB

RDAT

RPRTY

RSX

MM

A1 B0 B1 B2D0A0 D1 D2 D3 B3 B4


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User Interface

Table 2 defines the User Interface signals on the Receive core. The Receive User Interface connects tothe physical side of the system and implements the Xilinx LocalLink standard, providing a simple, flex-ible way to receive packets.

Figure 7 illustrates a sample operation of the Receive User Interface transmitting two complete packets.The first packet begins on the second rising edge of RX_CLK on RX_SRC_RDY and RX_DST_RDY bothasserted high. The user logic drives RX_SOF, RX_EOF, RX_ADDR, RX_DATA, and RX_REM appro-priately during the 5 clock cycle transfer. RX_DST_RDY is never deasserted, allowing the user logic torun at full rate. The packet begins with RX_SOF being asserted, which will assert RSOP on the SPI-3Packet Interface. On the sixth clock cycle, RX_EOF is asserted, which will assert REOP on the SPI-3Packet Interface. RX_REM is also asserted on the last clock cycle. The value of RX_REM is then translatedappropriately for the RMOD signal on the SPI-3 Packet Interface. An additional 8-clock cycle transfertakes place on completion of the previous packet. The Receive core detects the port address change andautomatically creates an in-band port address cycle on the SPI-3 Packet Interface. At the tenth and elev-enth rising clock edge RX_DST_RDY is asserted low, halting the user logic from providing additionaldata.

Table 2: User Interface: Receive Core


RX_CLK INReceive FIFO Write Clock: Used to synchronize data transfer transactions between the Link Layer device and the PHY Layer device. All User Interface signals are synchronous to the rising edge of this clock.

RX_SRC_RDY INReceive Source Ready: Indicates a word presented by the user is valid (not accepted until RX_DST_RDY is also asserted).

RX_DST_RDY OUTReceive Destination Ready: Indicates a word presented by the user will be accepted (if RX_SRC_RDY is also asserted).

RX_SOF INReceive Start of Frame: Indicates that the data on RX_DATA represents the beginning of a frame. A RX_SOF indication is passed through as RSOP to the SPI-3 Packet Interface.

RX_EOF INReceive End of Frame: Indicates that the data on RX_DATA represents the end of a frame. A RX_EOF indication is passed through as REOP to the SPI-3 Packet Interface.

RX_ADDR[7:0] INReceive Address: Indicates the port address associated with the packet. A change in RX_ADDR induces an in-band port address to be transmitted on the SPI-3 Packet Interface.

RX_DATA[D-1:0] IN Receive Data: Packet data to be written to the SPI-3 Packet Interface.

RX_REM[M-1:0] IN

Receive Remainder: Binary-encoded count of valid bytes in RX_DATA when RX_EOF is asserted; valid only when RX_EOF is asserted. Valid bytes begin with the most-significant byte of RX_DATA. The actual number of valid bytes is (RX_REM+1). When an 8-bit interface is used, the RX_REM bus is not present.

RX_ERR INReceive Error: When asserted, indicates that the packet contained an error. Valid only when RX_EOF is asserted.


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Figure 8 illustrates a sample operation of the Receive User Interface transmitting two interwoven pack-ets. The first packet having port address 0x00 begins and transmits for three clock cycles. The user logicthen switches to port address 0x01, and begins transmission for four cycles. The user logic thenswitches back to port address 0x00 and finishes the packet in two clock cycles. The user logic thenswitches back to port address 0x01 and transmits for an additional four clock cycles, finishing up thepacket that was started earlier. This signaling method allows for the user logic to break up packets ondifferent port addresses into different lengths for transmission across the SPI-3 Packet Interface.

Transmit Core Interfaces

The Transmit core receives data from the SPI-3 Packet Interface and processes the data for reading onthe User Interface. The User Interface and the SPI-3 Packet Interface operate on optionally independentclock domains.

Figure Top x-ref 7

Figure 7: Receive User Interface: Transmitting Two Packets

Figure Top x-ref 8

Figure 8: Receive User Interface: Transmitting Two Interwoven Packets

_ _

RX_DST_RDY

RX_DATA

RX_ADDR

RX_REM

RX_EOF

RX_SOF

RX_ERR

RR

0x00 0x01

B0 B1 B2 B3D1D0 D2 D3 D4 B4 B5

RX_SOB

RX_ERRBUS

B0 B1 B2 B3RX_DATA

RX_ADDR

RX_REM

RX_EOF

RX_CLK

RX_SRC_RDY

RX_DST_RDY

RX_SOF

D1

0x00 0x00

RR

D0

0x01

D2 D3 D4

0x01

B4 B5 B6 B7

RX_ERR


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SPI-3 Packet Interface

Table 3 defines the SPI-3 Packet Interface signals on the Transmit core. The SPI-3 Packet Interface con-nects to the reciprocal SPI-3 Packet Interface on the Link Layer device.

Table 3: SPI-3 Packet Interface: Transmit Core


TFCLK INTransmit FIFO Write Clock: Used to synchronize data transfer transactions between the Link Layer device and the PHY Layer device. All SPI-3 Packet Interface signals are synchronous to the rising edge of this clock.

TENB IN

Transmit Write Enable: Used to control the flow of data to the Transmit core. When TENB is high, the TDAT, TMOD, TSOP, TEOP and TERR signals are invalid and are ignored by the Transmit Core. The TSX signal is valid and processed by the Transmit core when TENB is high.When TENB is low, TDAT, TMOD, TSOP, TEOP and TERR signals are valid and are processed by the Transmit Core. The TSX signal is ignored by the Transmit core when TENB is low.

TDAT[D-1:0] IN

Transmit Packet Data Bus: The TDAT bus carries the packet data that was presented to the User Interface, as well as carries the in-band port address of the packet data.Data must be received in big endian order on TDAT. For example, when the width of the data bus is 32-bits, bit 31 is received first and bit 0 is received last.

TPRTY INTransmit Parity: Indicates the parity calculated over the TDAT bus. TPRTY is considered valid only when TENB or TSX is asserted. The Transmit core supports odd parity. Parity errors are reported on the User Interface.

TMOD[M-1:0] IN

Transmit Word Modulo: Indicates the number of valid bytes of data presented on TDAT. The TMOD bus should always be all zero, except during the last transfer of a packet on TDAT. When TEOP is asserted, the number of valid packet data bytes on TDAT is specified by TMOD. When an 8-bit interface is used, the TMOD signal in not present.

TSOP INTransmit Start of Packet: Used to delineate the packet boundaries on the TDAT bus. When TSOP is high, the start of the packet is present on the TDAT bus.

TEOP IN

Transmit End of Packet: Used to delineate the packet boundaries on the TDAT bus. When TEOP is high, the end of the packet is present on the TDAT bus. When a 32-bit or 16-bit interface is used, TMOD indicates then number of valid packet bytes on TDAT when TEOP is asserted.

TERR INTransmit Error Indicator: Indicates that the current packet is in error. TERR shall only be asserted when TEOP is asserted.

TSX IN

Transmit Start of Transfer: Indicates when the in-band port address is present on the TDAT bus. When TSX is high, the value of TDAT[7:0] is the address of the packet data. Subsequent data transfers on the TDAT bus will be from the port specified by this in-band address. TSX will be asserted at the beginning of each transfer. When TSX is considered valid only when TENB is not asserted.


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Figure 9 illustrates a sample operation of the SPI-3 Packet Interface receiving two complete packets.The first rising clock edge the TENB signal is sampled high, halting the Transmit core from receivingdata. The next clock cycle TENB and TSX are both sampled high, and the value of TDAT[7:0] is thevalue of the in-band port address of A0. In the following four clock cycles a complete packet is received,and demarcated with a TSOP and TEOP. On the seventh clock cycle a new packet is received with anin-band port address of A1. The following 7 clock cycles illustrate an additional data packet beingreceived.

Figure 10 illustrates a sample operation of the SPI-3 Packet Interface receiving a complete packet utiliz-ing the flow control signals. A packet is written into the Transmit core similar to the sample operationshown in Figure 9. The TENB signal is sampled high during the eighth and ninth rising clock edges,stalling the data transfer. On the tenth clock cycle, the TENB signal asserts low and the packet continuestransmission until the end of the packet is received.

Figure Top x-ref 9

Figure 9: SPI-3 Packet Interface Receiving Two Complete Packets

Figure Top x-ref 10

Figure 10: SPI-3 Packet Interface Receiving Complete Packetwith Flow Control

A1 B0 B1 B2

TEOP

TSOP

TERR

TFCLK

TMOD

TENB

TDAT

TPRTY

TSX

D0

MM

A0 D1 D2 D3 B3 B4 B5 B6

D5

TEOP

TSOP

TERR

TFCLK

TMOD

TENB

TDAT

TPRTY

TSX

D0

M

A0 D1 D4 D6 D7 D8 D9D2 D3


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User Interface

Table 4 defines the User Interface signals on the Transmit core. The User Interface connects to the phys-ical side of the system and implements the Xilinx LocalLink standard, providing a simple flexible wayto transmit packets.

Table 4: User Interface: Transmit Core


TX_CLK INTransmit Clock: All User Interface signals are synchronous to the rising edge of this clock.

TX_SRC_RDY OUTTransmit Source Ready: Indicates a word presented by the Transmit core is valid (not accepted until TX_DST_RDY is also asserted).

TX_DST_RDY INTransmit Destination Ready: Indicates a word presented by the Transmit core will be accepted (if TX_SRC_RDY is also asserted).

TX_SOB OUTTransmit Start of Burst: Indicates that the data on TX_DATA represented a new burst of data, determined by a change of the in-band address.

TX_SOF OUTTransmit Start of Frame: Indicates that the data on TX_DATA represents the beginning of a frame. A TX_SOF indication is a pass-through of TSOP from the SPI-3 Packet Interface.

TX_EOF OUTTransmit End of Frame: Indicates that the data on TX_DATA represents the end of a frame. A TX_EOF indication is a pass-through of TEOP from the SPI-3 Packet Interface.

TX_ADDR[7:0] OUT Transmit Address: Indicates the port address associated with the packet.

TX_DATA[D-1:0] OUTTransmit Data: Carries the packet data associated with the transmit address.

TX_REM[M-1:0] OUT

Transmit Remainder: Binary-encoded count of valid bytes in TX_DATA when TX_EOF is asserted; valid only when TX_EOF is asserted. Valid bytes begin with the most-significant byte of TX_DATA. The actual number of valid bytes is (TX_REM+1). When an 8-bit interface is used, the TX_REM bus is not present.

TX_ERR OUT

Transmit Error: When asserted, indicates that the packet contained an error. The type of error will be asserted on TX_ERRBUS. Errors are held until the in-band address is changed, or a TEOP was received on the SPI-3 Packet Interface.

TX_ERRBUS[7:0] OUT

Transmit Error Bus: Provides real-time error notification. Errors are held until the in-band address is changed, or a TEOP was received on the SPI-3 Packet Interface. TX_ERRBUS[0] can only be flagged on valid cycles when TX_EOF is asserted.[7:3] = reserved (tied to 0)[2] = in-band address parity error[1] = data parity error[0] = TERR was indicated


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Figure 11 illustrates a sample operation of the Transmit User Interface presenting two complete packetsto the user logic. Following the first rising clock edge, the Transmit User Interface asserts TX_SOB inresponse to the port address changing. This signal can be used as an indicator to the user logic to switchFIFOs external to the Transmit core. We also see TX_SOF, TX_ADDR, and TX_DATA being driven tothe appropriate values received on the SPI-3 Packet Interface. Following the fifth rising clock edge, thepacket is ended, TX_EOF is asserted and a remainder is presented on TX_REM. The following clockcycle, TX_SOB is asserted, and TX_ADDR changes port addresses. For rising clock edges ten and eleven,TX_SRC_RDY is deasserted by the Transmit core, possibly due to a stall on the SPI-3 Packet Interface.Data transfer resumes on the twelfth rising clock edge.

Figure Top x-ref 11

Figure 11: Transmit User Interface Presenting Two Complete Packets

TX_DATA

TX_ADDR

TX_REM

TX_EOF

TX_CLK

TX_SOB

TX_DST_RDY

TX_SRC_RDY

TX_SOF

RR

TX_ERRBUS

TX_ERR

B0 B1 B2D1D0 D2 D3 D4 B3 B4 B5

0x00 0x01 0x01


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Figure 12 illustrates a sample operation of the Transmit User Interface presenting two interwovenpackets. On the second rising clock edge, TX_SOB indicates an address change and TX_ADDR indicatesport address 0x00. Three clock cycles later, TX_SOB is again asserted indicating an address change, thistime TX_ADDR indicates port address 0x01. On the ninth rising clock edge, TX_SOB is asserted andTX_ADDR indicates that the Transmit core has returned to port address 0x00. The remainder of thisframe is transmitted on the next clock cycle. The eleventh rising clock edge TX_SOB again indicates achannel change and TX_ADDR indicates port address 0x01. The remainder of this frame is transmittedby the Transmit core in the following three clock cycles.

Figure 13 illustrates a sample operation of the Transmit User Interface presenting two complete pack-ets. The first packet indicates that TERR was flagged on the SPI-3 Packet Interface. The TX_ERRBUS isdriven to 0x01 to indicate that the current packet received a TERR indication. TX_ERR is also assertedindicating that TX_ERRBUS contained an error. When a channel change or a TX_EOF occurs, the valueof TX_ERRBUS and TX_ERR are reset to 0x00 and low, respectively.

Figure Top x-ref 12

Figure 12: Transmit User Interface Presenting Two Interwoven Packets

B0 B1 B2 B3TX_DATA

TX_ADDR

TX_REM

TX_EOF

TX_CLK

TX_SOB

TX_SRC_RDY

TX_DST_RDY

TX_SOF

TX_ERRBUS

D1

0x00 0x00

RR

D0

0x01

D2 D3 D4

0x01

B4 B5 B6 B7

TX_ERR


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Figure 14 illustrates a sample operation of the Transmit User Interface presenting two complete pack-ets. The first packet indicates that the packet had a data parity error. This error is indicated on theTX_ERRBUS as 0x02 and can be asserted at any point in time in a packet. After the parity error isdetected, the error is held until TX_EOF or the in-band port address has changed. The second packetfurther illustrates that the data parity error is held until TX_EOF.

Figure Top x-ref 13

Figure 13: Transmit User Interface Presenting Two Complete Packets

Figure Top x-ref 14

Figure 14: Transmit User Interface Presenting Two Complete Packets with Parity Error

B0 B1 B2 B3TX_DATA

TX_ADDR

TX_REM

TX_EOF

TX_CLK

TX_SOB

TX_SRC_RDY

TX_DST_RDY

TX_SOF

D1

0x00

RR

D0 D2 D3 D4

0x01

B4 B5 B6 B7

TX_ERRBUS 0x00

TX_ERR

0x01 0x00Hex

B0 B1 B2 B3TX_DATA

TX_ADDR

TX_REM

TX_EOF

TX_CLK

TX_SOB

TX_SRC_RDY

TX_DST_RDY

TX_SOF

D1

0x00

RR

D0 D2 D3 D4

0x01

B4 B5 B6 B7

TX_ERRBUS 0x02

TX_ERR

0x00Hex 0x02


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Figure 15 illustrates a sample operation of the Transmit User Interface presenting two complete pack-ets. The first packet indicates that the packet had an in-band port address parity error. This error is indi-cated on the TX_ERRBUS as 0x4 and is asserted for the length of the packet until TX_EOF or the portaddress has changed.

Transmit FIFO Status Interface

Table 5 defines the Transmit FIFO Status Interface signals. The Transmit FIFO Status Interface providesstatus for the internal FIFO as well as status for the user’s port addressable FIFOs for transmissionthrough the Transmit Packet Available Interface.

Figure Top x-ref 15

Figure 15: Transmit Interface Presenting Two Complete Packets with In-bandPort Address Parity Error

Table 5: Transmit FIFO Status Interface


TX_FIFO_AF OUT

Transmit Internal FIFO Almost Full: Used to indicate the fill status of the internal FIFO. When the TX_FIFO_AF signal is asserted, the internal FIFO is almost full. The user is responsible for asserting the appropriate TX_AF signal to ensure that the internal FIFO does not overflow.

TX_AF[C-1:0] INTransmit Almost Full: Used to indicate which PHY FIFOs are almost full as indexed by the port address.

TX_AF_WE IN

Transmit Almost Full Write Enable: Used to validate the TX_AF signal. When TX_AF_WE is low, any changes to the TX_AF signal are not reflected on the Transmit Packet Available Interface. When high, the values on TX_AF are used to generate the appropriate signals on the Transmit Packet Available Interface.

TX_AF_MASK[C-1:0] IN

Transmit Almost Full Mask: Used to indicate which portions of the TX_AF bus are valid. When low, the corresponding port address status remains unchanged. When high, the corresponding port address status is updated.

B0 B1 B2 B3TX_DATA

TX_ADDR

TX_REM

TX_EOF

TX_CLK

TX_SOB

TX_SRC_RDY

TX_DST_RDY

TX_SOF

D1

0x00

RR

D0 D2 D3 D4

0x01

B4 B5 B6 B7

TX_ERRBUS 0x04

TX_ERR

0x00Hex


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Figure 16 (shown in the next section) illustrates a sample operation on the Transmit FIFO Status Inter-face. Only the operation of the Transmit FIFO Status Interface will be described here; the next sectionwill describe how the Transmit Packet Available Interface is affected. During the first rising clock edge,the TX_AF_WE signal is sampled low, indicating that the values present on the TX_AF bus are invalidand should be ignored, and the previous valid values should be used instead. On the second risingclock edge, TX_AF_WE is sampled high. TX_AF was driven to 0x5 and TX_AF_MASK was 0xF, indicatingchannels "2" and "0" are almost full. On the seventh rising clock edge TX_AF_WE is again sampled to behigh, so the Transmit core updates its current FIFO status values. TX_AF was driven to 0x0, howeverTX_AF_MASK was driven to 0x1. Only channel "0" is updated because the TX_AF_MASK mask signalindicates that this is the only channel to be updated. Channel "2" remains almost full, and channel "0"becomes ready for a packet again.

The Transmit FIFO Status Interface is consistent between Byte-level mode and Packet-level mode, sothe behavior of the Transmit FIFO Status Interface is the same in Figures 16 and 17. Note that the rela-tionship between the Transmit FIFO Status Interface and the Transmit Packet Available Interface (dis-cussed below) is that when a given port address is indicated as not full (available) by driving theappropriate bit of TX_AF low, the following condition occurs:

• In Byte-level mode, the corresponding bit in the DTPA bus is driven high shortly afterward, and the STPA signal is driven high as well if a packet is sent to the same given port address.

• In Packet-level mode, the PTPA signal is driven high if the TADR bus accesses that given port address.

• If TX_AF is driven high (not available) for a given port address, the Transmit Packet Available Interface signals are affected in the same way, but are driven low instead.


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Transmit Packet Available Interface

Table 6 defines the Transmit Packet Available Interface signals. The Transmit Packet Available Interfaceconnects to the corresponding Transmit Packet Available Interface on the Link Layer device.

Figure 16 illustrates a sample operation of the Transmit Packet Available Interface in Byte-level mode.The current status of the Transmit FIFOs are sent using the Transmit FIFO Status Interface, as describedpreviously. About 4 clock cycles later, the DTPA and STPA signals are updated to reflect the latest statusinformation. For the duration of this illustration, assume that the Transmit core is currently receiving anin-band port address of 0x00. Because of this, the STPA signal will reflect the current status of the portaddress 0x00. The DTPA signal reflects the status of all available channels.

Table 6: Transmit Packet Available Interface

Signal Name Direction Mode Description

TADR[C-1:0] IN Packet

Transmit Address: Used with the PTPA signal to poll the transmit FIFO’s packet available status.When TADR is sampled on the rising edge of the TFCLK by the Transmit core, the polled packet available indication PTPA signal is updated with the status of the port specified by the TADR address on the following rising edge of TFCLK.

PTPA OUT Packet

Polled-PHY Transmit Packet Available: PTPA transitions high when a predefined minimum number of bytes are available in the polled transmit FIFO. Once high, PTPA indicates that the transmit FIFO is not full. When PTPA transitions low, it indicates that the transmit FIFO is full or near full.PTPA allows the polling of the PHY selected by the TADR address bus. The port which PTPA reports is updated on the following rising edge of TFCLK after the PHY address on TADR is sampled by the PHY device.

DTPA[C-1:0] OUT Byte

Direct Transmit Packet Available: Provides direct status indication for the corresponding ports in the PHY device.DTPA transitions high when a predefined minimum number of bytes are available in the corresponding transmit FIFO. Once high, the DTPA signal indicates that the corresponding transmit FIFO is not full. When DTPA transitions low, it indicates that its transmit FIFO is full or near full.

STPA OUT Byte

Selected-PHY Transmit Packet Available: STPA transitions high when a predefined minimum number of bytes is available in the transmit FIFO specified by the in-band address on TDAT. Once high, the STPA signal indicates that the corresponding transmit FIFO is not full. When STPA transitions low, it indicates that its transmit FIFO is full or near full.STPA always provides status indication for the selected port of the PHY device in order to avoid FIFO overflows while polling is performed. The port which STPA reports is updated on the following rising edge of TFCLK after the PHY address on TDAT is sampled by the PHY device.


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Because the FIFO Status Interface and the Transmit Packet Available Interface are on different clockdomains, synchronization logic is used to cross clock domains. The true latency between the TransmitFIFO Status Interface and the Transmit Packet Available Interface depends on the clock frequency of theclocks used in the design.

Figure 17 illustrates a sample operation of the Transmit Packet Available Interface in Packet-levelmode. The current status of the Transmit FIFOs are sent using the Transmit FIFO Status Interface, asdescribed previously. The Link Layer device provides a port address on the TADR signal. The Transmitcore generates the appropriate status for transmission on the PTPA signal. When the port address A0 issampled on the second clock cycle, the Transmit core responds by driving PTPA to the value indicatedby the Transmit FIFO Status Interface on the next rising clock edge. This process continues for eachaddress on TADR.

Because the Transmit FIFO Status Interface and Transmit Packet Available Interface are on differentclock domains, synchronization logic is used to cross clock domains. The true latency between theTransmit FIFO Status Interface and the Transmit Packet Available Interface depends on the clock fre-quency of the clocks used in the design.

Figure Top x-ref 16

Figure 16: Transmit Packet Available Interface in Byte-level Mode

Figure Top x-ref 17

Figure 17: Transmit Packet Available Interface in Packet-level Mode

TX_CLK

TX_FIFO_AF

TX_AF_MASK 0x1Hex 0xF

TX_AF_WE

TX_AF 0x0Hex 0x5

DTPA

STPA

TFCLK

1010 1011

TX_CLK

TX_FIFO_AF

TX_AF_MASK 0x1Hex 0xF

TX_AF_WE

TX_AF 0x0Hex 0x5

TADR

PTPA

TFCLK

A1A0 A2 A3 A1A0 A2 A3 A1A0 A2 A3


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Transmit Static Configuration Signals

Table 7 defines the Transmit Static Configuration signals. These signals are inputs to the core that arestatically driven by setting them to a constant value in the top-level wrapper file. The SPI-3 PHY Layerrelease includes a wrapper file with the static configuration signals connected to the values selected inthe CORE Generator GUI.

Signal Widths

The Receive and Transmit cores can transmit and receive data on 8-bit, 16-bit, or 32-bit interface widths,depending on the core configuration. Consequently the remainder/modulo widths are related to thedata path width. Additionally, the flow control interfaces are dependent on the number of supportedport addresses in the selected configuration. The static configuration almost-full-threshold widths arealso dependent on the depth of the internal FIFO.

Table 8 defines the relationship between the data bus width and the LocalLink remainder (TX_REM,RX_REM) and SPI-3 modulo (TMOD, RMOD) signals. When the core is configured in 8-bit mode, theremainder and modulo signals are not present.

The number of supported port addresses is used to determine the width of the signals DTPA, TX_AF,and TX_AF_MASK buses. The number of supported port addresses is configured through the COREGenerator GUI.

Table 9 defines the relationship between the internal FIFO depth and the width of theTX_AF_THRESH_ASSERT and TX_AF_THRESH_NEGATE static configuration signals.

Table 7: Transmit Static Configuration Signals


TX_AF_ASSERT_THRESH[T-1:0] STATICTransmit Almost Full Assert Threshold: Allows the user to control when the TX_FIFO_AF (almost full flag for the internal FIFO) is asserted.

TX_AF_NEGATE_THRESH[T-1:0] STATICTransmit Almost Full Negate Threshold: Allows the user to control when the TX_FIFO_AF (almost full flag for the internal FIFO) is negated.

Table 8: Data Bus Width Dependencies

Data Bus Width (D) Remainder/Modulo Width (M)

8 N/A

16 1

32 2

Table 9: Threshold Bus Width Dependencies

Internal FIFO Depth Threshold Width (T)

16 4

32 5

64 6

128 7

256 8


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Remainder and Modulo Signaling

When an 8-bit interface is used, the REM signal on the User Interface and MOD signal on the PacketInterface are not present. The User Interfaces on the Receive and Transmit cores implement the XilinxLocalLink standard. The Xilinx LocalLink standard specifies that the remainder signal indicate thenumber of valid bytes on the data bus as REM + 1, with the valid bytes MSB justified. This signal is onlyvalid when an EOF is asserted. Table 10 shows the possible REM signaling and the valid bits on theDATA signal.

The SPI-3 Packet Interfaces on the Receive and Transmit cores implement the OIF SPI3-01.0 standard.The SPI-3 standard uses a Modulo signal to indicate valid bytes on the last transfer. Table 11 shows thepossible MOD signaling and the valid bits on the DAT signal.

VerificationXilinx has verified the SPI-3 PHY Layer core in a proprietary test environment using an internallydeveloped bus functional model (BFM). Thousands of test vectors have been generated and verified,including both correct and errored frames.

512 9

1024 10

2048 11

4096 12

Table 10: Example REM Signaling

32-bit 16-bit

REM[1:0] DATA valid REM[0] DATA valid

"00" [31:24] "0" [15:8]

"01" [31:16] "1" [15:0]

"10" [31:8]

"11" [31:0]

Table 11: Example MOD Signaling

32-bit 16-bit

MOD[1:0] DAT valid MOD[0] DAT valid

"00" [31:0] "0" [15:0]

"01" [31:8] "1" [15:8]

"10" [31:16]

"11" [31:24]

Table 9: Threshold Bus Width Dependencies (Continued)

Internal FIFO Depth Threshold Width (T)


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