) reference guide · 2020. 6. 12. · 1105-00 23 november 2018 non-confidential update for v11.5....

Fast ModelsVersion 11.11

Fixed Virtual Platforms (FVP) Reference Guide

Copyright © 2014–2020 Arm Limited or its affiliates. All rights reserved.100966_1111_00_en

Fast ModelsFixed Virtual Platforms (FVP) Reference GuideCopyright © 2014–2020 Arm Limited or its affiliates. All rights reserved.

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ContentsFast Models Fixed Virtual Platforms (FVP)Reference Guide

PrefaceAbout this book ...................................................... ...................................................... 9

Chapter 1 Introduction1.1 About FVPs ...................................................... ...................................................... 1-121.2 Data collection in FVPs ............................................. ............................................. 1-13

Chapter 2 Getting Started with Fixed Virtual Platforms2.1 FVP command-line options .......................................... .......................................... 2-162.2 Loading and running an application on an FVP ........................... ........................... 2-212.3 Configuring the model .............................................. .............................................. 2-222.4 FVP debug ....................................................... ....................................................... 2-232.5 Using the CLCD window .......................................................................................... 2-242.6 Ethernet with VE FVPs ............................................................................................ 2-272.7 Using a terminal with a system model .................................. .................................. 2-292.8 Virtio P9 device component .......................................... .......................................... 2-31

Chapter 3 Base Platform FVPs3.1 FVP_Base_AEMv8A ............................................... ............................................... 3-353.2 FVP_Base_AEMv8A-AEMv8A ........................................ ........................................ 3-433.3 FVP_Base_AEMvA ................................................ ................................................ 3-543.4 FVP_Base_Cortex-A32x1 ........................................... ........................................... 3-62


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3.5 FVP_Base_Cortex-A32x2 ........................................... ........................................... 3-703.6 FVP_Base_Cortex-A32x4 ........................................... ........................................... 3-783.7 FVP_Base_Cortex-A35x1 ........................................... ........................................... 3-873.8 FVP_Base_Cortex-A35x2 ........................................... ........................................... 3-953.9 FVP_Base_Cortex-A35x4 .......................................... .......................................... 3-1033.10 FVP_Base_Cortex-A53x1 ...................................................................................... 3-1123.11 FVP_Base_Cortex-A53x2 .......................................... .......................................... 3-1203.12 FVP_Base_Cortex-A53x4 .......................................... .......................................... 3-1283.13 FVP_Base_Cortex-A55 ............................................ ............................................ 3-1373.14 FVP_Base_Cortex-A55+Cortex-A76 .................................. .................................. 3-1463.15 FVP_Base_Cortex-A55x1 .......................................... .......................................... 3-1553.16 FVP_Base_Cortex-A55x1+Cortex-A75x1 .............................. .............................. 3-1633.17 FVP_Base_Cortex-A55x2 .......................................... .......................................... 3-1723.18 FVP_Base_Cortex-A55x2+Cortex-A75x2 .............................. .............................. 3-1803.19 FVP_Base_Cortex-A55x4 .......................................... .......................................... 3-1893.20 FVP_Base_Cortex-A55x4+Cortex-A75x1 .............................. .............................. 3-1983.21 FVP_Base_Cortex-A55x4+Cortex-A75x2 .............................. .............................. 3-2073.22 FVP_Base_Cortex-A55x4+Cortex-A75x4 .............................. .............................. 3-2163.23 FVP_Base_Cortex-A55x4+Cortex-A76x2 .............................. .............................. 3-2253.24 FVP_Base_Cortex-A57x1 .......................................... .......................................... 3-2343.25 FVP_Base_Cortex-A57x1-A35x1 .......................................................................... 3-2423.26 FVP_Base_Cortex-A57x1-A53x1 .......................................................................... 3-2523.27 FVP_Base_Cortex-A57x2 .......................................... .......................................... 3-2623.28 FVP_Base_Cortex-A57x2-A35x4 .......................................................................... 3-2703.29 FVP_Base_Cortex-A57x2-A53x4 .......................................................................... 3-2803.30 FVP_Base_Cortex-A57x4 .......................................... .......................................... 3-2903.31 FVP_Base_Cortex-A57x4-A35x4 .......................................................................... 3-2993.32 FVP_Base_Cortex-A57x4-A53x4 .......................................................................... 3-3103.33 FVP_Base_Cortex-A65AEx2 ........................................ ........................................ 3-3213.34 FVP_Base_Cortex-A65AEx2+Cortex-A76AEx2 .................................................... 3-3303.35 FVP_Base_Cortex-A65AEx4 ........................................ ........................................ 3-3393.36 FVP_Base_Cortex-A65AEx4+Cortex-A76AEx4 .................................................... 3-3493.37 FVP_Base_Cortex-A65AEx8 ........................................ ........................................ 3-3593.38 FVP_Base_Cortex-A65x1 .......................................... .......................................... 3-3703.39 FVP_Base_Cortex-A65x2 .......................................... .......................................... 3-3783.40 FVP_Base_Cortex-A65x4 .......................................... .......................................... 3-3863.41 FVP_Base_Cortex-A72x1 .......................................... .......................................... 3-3953.42 FVP_Base_Cortex-A72x1-A53x1 .......................................................................... 3-4033.43 FVP_Base_Cortex-A72x2 .......................................... .......................................... 3-4133.44 FVP_Base_Cortex-A72x2-A53x4 .......................................................................... 3-4213.45 FVP_Base_Cortex-A72x4 .......................................... .......................................... 3-4313.46 FVP_Base_Cortex-A72x4-A53x4 .......................................................................... 3-4403.47 FVP_Base_Cortex-A73x1 .......................................... .......................................... 3-4513.48 FVP_Base_Cortex-A73x1-A53x1 .......................................................................... 3-4593.49 FVP_Base_Cortex-A73x2 .......................................... .......................................... 3-4693.50 FVP_Base_Cortex-A73x2-A53x4 .......................................................................... 3-4773.51 FVP_Base_Cortex-A73x4 .......................................... .......................................... 3-4873.52 FVP_Base_Cortex-A73x4-A53x4 .......................................................................... 3-4963.53 FVP_Base_Cortex-A75 ............................................ ............................................ 3-5073.54 FVP_Base_Cortex-A75x1 .......................................... .......................................... 3-515


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3.55 FVP_Base_Cortex-A75x2 .......................................... .......................................... 3-5233.56 FVP_Base_Cortex-A75x4 .......................................... .......................................... 3-5313.57 FVP_Base_Cortex-A76 ............................................ ............................................ 3-5403.58 FVP_Base_Cortex-A76AEx2 ........................................ ........................................ 3-5483.59 FVP_Base_Cortex-A76AEx4 ........................................ ........................................ 3-5573.60 FVP_Base_Cortex-A76x1 .......................................... .......................................... 3-5673.61 FVP_Base_Cortex-A76x2 .......................................... .......................................... 3-5753.62 FVP_Base_Cortex-A76x4 .......................................... .......................................... 3-5833.63 FVP_Base_Cortex-A77x1 .......................................... .......................................... 3-5923.64 FVP_Base_Cortex-A77x2 .......................................... .......................................... 3-6003.65 FVP_Base_Cortex-A77x4 .......................................... .......................................... 3-6083.66 FVP_Base_Cortex-A78x1 .......................................... .......................................... 3-6173.67 FVP_Base_Cortex-A78x2 .......................................... .......................................... 3-6253.68 FVP_Base_Cortex-A78x4 .......................................... .......................................... 3-6333.69 FVP_Base_Cortex-X1x1 ........................................... ........................................... 3-6423.70 FVP_Base_Cortex-X1x2 ........................................... ........................................... 3-6503.71 FVP_Base_Cortex-X1x4 ........................................... ........................................... 3-6583.72 FVP_Base_Neoverse-E1x1 ......................................... ......................................... 3-6673.73 FVP_Base_Neoverse-E1x2 ......................................... ......................................... 3-6753.74 FVP_Base_Neoverse-E1x4 ......................................... ......................................... 3-6833.75 FVP_Base_Neoverse-N1 ........................................... ........................................... 3-6923.76 FVP_Base_Neoverse-N1x1 ......................................... ......................................... 3-7013.77 FVP_Base_Neoverse-N1x2 ......................................... ......................................... 3-7093.78 FVP_Base_Neoverse-N1x4 ......................................... ......................................... 3-7173.79 FVP_Base_RevC-2xAEMv8A ....................................... ....................................... 3-7263.80 FVP_Base_RevC-2xAEMvA ........................................ ........................................ 3-739

Chapter 4 BaseR Platform FVPs4.1 FVP_BaseR_Cortex-R52x1 ......................................... ......................................... 4-7534.2 FVP_BaseR_Cortex-R52x2 ......................................... ......................................... 4-7614.3 FVP_BaseR_Cortex-R52x4 ......................................... ......................................... 4-769

Chapter 5 VE Platform FVPs5.1 FVP_VE_Cortex-A15x1 ............................................ ............................................ 5-7805.2 FVP_VE_Cortex-A15x1-A7x1 ....................................... ....................................... 5-7885.3 FVP_VE_Cortex-A15x2 ............................................ ............................................ 5-7975.4 FVP_VE_Cortex-A15x2-A7x2 ....................................... ....................................... 5-8055.5 FVP_VE_Cortex-A15x4 ............................................ ............................................ 5-8155.6 FVP_VE_Cortex-A15x4-A7x4 ....................................... ....................................... 5-8245.7 FVP_VE_Cortex-A17x1 ............................................ ............................................ 5-8355.8 FVP_VE_Cortex-A17x1-A7x1 ....................................... ....................................... 5-8435.9 FVP_VE_Cortex-A17x2 ............................................ ............................................ 5-8525.10 FVP_VE_Cortex-A17x4 ............................................ ............................................ 5-8605.11 FVP_VE_Cortex-A17x4-A7x4 ....................................... ....................................... 5-8695.12 FVP_VE_Cortex-A5x1 ............................................. ............................................. 5-8805.13 FVP_VE_Cortex-A5x2 ............................................. ............................................. 5-8885.14 FVP_VE_Cortex-A5x4 ............................................. ............................................. 5-8965.15 FVP_VE_Cortex-A7x1 ............................................. ............................................. 5-9055.16 FVP_VE_Cortex-A7x2 ............................................. ............................................. 5-9135.17 FVP_VE_Cortex-A7x4 ............................................. ............................................. 5-921


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5.18 FVP_VE_Cortex-A9x1 ............................................. ............................................. 5-9305.19 FVP_VE_Cortex-A9x2 ............................................. ............................................. 5-9385.20 FVP_VE_Cortex-A9x4 ............................................. ............................................. 5-9465.21 FVP_VE_Cortex-R4 ............................................... ............................................... 5-9555.22 FVP_VE_Cortex-R5x1 ............................................. ............................................. 5-9635.23 FVP_VE_Cortex-R5x2 ............................................. ............................................. 5-9715.24 FVP_VE_Cortex-R7x1 ............................................. ............................................. 5-9795.25 FVP_VE_Cortex-R7x2 ............................................. ............................................. 5-9865.26 FVP_VE_Cortex-R8x1 ............................................. ............................................. 5-9935.27 FVP_VE_Cortex-R8x2 ............................................ ............................................ 5-10005.28 FVP_VE_Cortex-R8x4 ............................................ ............................................ 5-1007

Chapter 6 MPS2 Platform FVPs6.1 FVP_MPS2_AEMv8M ............................................ ............................................ 6-10166.2 FVP_MPS2_Cortex-M0 ........................................... ........................................... 6-10306.3 FVP_MPS2_Cortex-M0plus ........................................ ........................................ 6-10446.4 FVP_MPS2_Cortex-M23 .......................................... .......................................... 6-10596.5 FVP_MPS2_Cortex-M3 ........................................... ........................................... 6-10746.6 FVP_MPS2_Cortex-M33 .......................................... .......................................... 6-10886.7 FVP_MPS2_Cortex-M35P ......................................... ......................................... 6-11036.8 FVP_MPS2_Cortex-M4 ........................................................................................ 6-11186.9 FVP_MPS2_Cortex-M55 .......................................... .......................................... 6-11326.10 FVP_MPS2_Cortex-M7 ........................................... ........................................... 6-11476.11 FVP_MPS2_SSE-200_AEMv8M_pipeline ............................. ............................. 6-11616.12 FVP_MPS2_SSE-200_Cortex-M33 .................................. .................................. 6-11746.13 FVP_MPS2_SSE-200_Cortex-M55 .................................. .................................. 6-11896.14 FVP_MPS2_SecurCore-SC000 ..................................... ..................................... 6-12046.15 FVP_MPS2_SecurCore-SC300 ..................................... ..................................... 6-1219

Chapter 7 Arm® Neoverse™ reference design FVPs7.1 About the FVPs ................................................. ................................................. 7-12357.2 Block diagrams for RD-N1-E1-edge .................................................................... 7-12367.3 FVP peripherals ................................................. ................................................. 7-1237


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Preface

This preface introduces the Fast Models Fixed Virtual Platforms (FVP) Reference Guide.

It contains the following:• About this book on page 9.


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About this bookArm® Fixed Virtual Platform Reference. This manual introduces the Fixed Virtual Platforms, anddescribes how you can use them with other tools.

Using this book

This book is organized into the following chapters:

Chapter 1 IntroductionThis chapter introduces the document.

Chapter 2 Getting Started with Fixed Virtual PlatformsThis chapter describes how to use FVPs.

Chapter 3 Base Platform FVPsThis chapter lists the Base Platform FVPs and the instances in them.

Chapter 4 BaseR Platform FVPsThis chapter lists the BaseR Platform FVPs and the instances in them.

Chapter 5 VE Platform FVPsThis chapter lists the VE Platform FVPs and the instances in them.

Chapter 6 MPS2 Platform FVPsThis chapter lists the MPS2 Platform FVPs and the instances in them.

Chapter 7 Arm® Neoverse™ reference design FVPsThis chapter describes the Arm Neoverse™ N1 edge and Arm Neoverse E1 edge reference designFVPs. These FVPs are collectively referred to as RD-N1-E1-edge FVPs.

Glossary

The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for thoseterms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaningdiffers from the generally accepted meaning.

See the Arm® Glossary for more information.

Typographic conventions

italicIntroduces special terminology, denotes cross-references, and citations.

boldHighlights interface elements, such as menu names. Denotes signal names. Also used for termsin descriptive lists, where appropriate.

monospaceDenotes text that you can enter at the keyboard, such as commands, file and program names,and source code.

monospaceDenotes a permitted abbreviation for a command or option. You can enter the underlined textinstead of the full command or option name.

monospace italicDenotes arguments to monospace text where the argument is to be replaced by a specific value.

monospace boldDenotes language keywords when used outside example code.

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https://developer.arm.com/support/arm-glossary

Encloses replaceable terms for assembler syntax where they appear in code or code fragments.For example:

MRC p15, 0, , , ,

SMALL CAPITALS

Used in body text for a few terms that have specific technical meanings, that are defined in theArm® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, andUNPREDICTABLE.

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Chapter 1Introduction

This chapter introduces the document.

It contains the following sections:• 1.1 About FVPs on page 1-12.• 1.2 Data collection in FVPs on page 1-13.


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1.1 About FVPsFixed Virtual Platforms (FVPs) enable software development without the need for real hardware.

FVPs are available for Linux and Windows hosts, either:

• As pre-built executables. Their composition is fixed, although you can configure their behavior usingparameters.

• As source code in the Fast Models product, with the tools required to customize and build them.

Arm provides different types of FVP, based on the following platforms:

• Armv8‑A Base Platform.• Armv8‑R BaseR Platform.• Arm Versatile™ Express development boards.• Arm MPS2 or Arm MPS2+ platforms, for Cortex®‑M series processors.

FVPs are available for all Cortex‑A, Cortex‑R, and Cortex‑M processors, and they support the CADI,MTI, and Iris interfaces, so can be used for debugging and for trace output.

There are several freely available, pre-built FVPs for download from Arm Developer which can be usedwithout a license:• Foundation Platform. This is a basic FVP with a minimal peripheral set which is suitable for running

on Linux hosts only. It includes a single cluster which can be configured with between 1-4 AEMv8-Acores. It is suitable for running bare-metal applications and for booting Linux. It supports the CADIdebug interface, but does not support MTI or Iris interfaces.

• AEMv8-A Base Platform RevC FVP. This is a platform model with a more extended peripheral setthan the Foundation Platform. It has two AEMv8-A clusters, each of which can be configured with1-4 AEMv8-A cores. It supports Armv8‑A architecture versions up to v8.5 and supports CADI, MTI,and Iris debug and trace interfaces.

• Validation platform for A-profile architectures. This FVP is optimized for validating CPUimplementations and can be used with the A-profile Architecture Compliance Kit (ACK).

Arm provides validated Linux and Android deliverables for the Armv8‑A AEM Base Platform FVP andfor the Foundation Platform. These are available on the Arm Community website at Arm DevelopmentPlatforms. To get started with Linux on Armv8‑A FVPs, see Armv8-A FVPs also on Arm Community.

Related informationBase PlatformMicrocontroller Prototyping System 2Versatile Express Model

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https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platformshttps://community.arm.com/dev-platforms/https://community.arm.com/dev-platforms/https://community.arm.com/dev-platforms/w/docs/228/armv8-a-fvpshttps://developer.arm.com/docs/100964/1111/base-platformhttps://developer.arm.com/docs/100964/1111/microcontroller-prototyping-system-2https://developer.arm.com/docs/100964/1111/versatile-express-model

1.2 Data collection in FVPsArm periodically collects anonymous information about the usage of our products to understand andanalyze what components or features you are using, with the goal of improving our products and yourexperience with them. Product usage analytics contain information such as system information, settings,and usage of specific features of the product. They do not include any personal information.

Host information includes:• Operating system name, version, and locale.• Number of CPUs.• Amount of physical memory.• Screen resolution.• Processor and GPU type.

Feature tracking information includes:

Table 1-1 Fast Models analytics data points

Name Description Since

Platform name • Tracked:— Name of the platform model being run— Fast Models version and build number that was used to build the platform model.— Whether the platform model is a standalone product or was supplied as part of the

Fast Models product. a

• Reported: Percentage of users using the different platforms.• Data type: Text.• Send policy: Every invocation.• Trigger points: On starting the simulation.

v11.8

Session length • Tracked: Length of time the platform was used.• Reported: Average time the different platforms are used.• Data type: Text.• Send policy: Every invocation.• Trigger points: On exiting the simulation.

v11.9

Debug server • Tracked: Whether a CADI or Iris debugger was connected.• Reported: Type of debug server that was started, either CADI or Iris.• Data type: Text.• Send policy: Every invocation.• Trigger points: Debug server startup.

v11.10

Arm IP • Tracked: Names of Fast Models core, System IP, and GPU components that are includedin the simulation.

• Reported: Component names, for example DP500 or SMMUv3AEM. These are nothierarchical names.

• Data type: Text.• Send policy: Every invocation.• Trigger points: Component instantiation.

v11.10

a This feature is tracked since v11.10.

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Note

• Analytics gathering is enabled by default. Use the --disable-analytics command-line option todisable it for the current invocation, or set the ARM_DISABLE_ANALYTICS environment variable to anon-zero value to disable it for all invocations.

• Querying the list of parameters with --list-params or the available options using --help does nottrigger reporting.

• The names of non-Arm platforms or components are obfuscated.

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Chapter 2Getting Started with Fixed Virtual Platforms

This chapter describes how to use FVPs.

It contains the following sections:• 2.1 FVP command-line options on page 2-16.• 2.2 Loading and running an application on an FVP on page 2-21.• 2.3 Configuring the model on page 2-22.• 2.4 FVP debug on page 2-23.• 2.5 Using the CLCD window on page 2-24.• 2.6 Ethernet with VE FVPs on page 2-27.• 2.7 Using a terminal with a system model on page 2-29.• 2.8 Virtio P9 device component on page 2-31.


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2.1 FVP command-line optionsSpecify these options when you launch an FVP from the command line. You can specify these options inany order.

Table 2-1 CADI or Iris-related options

Shortform

Long form Description

-S --cadi-server

Start a CADI server. This option allows a CADI-enabled debugger to connect to targets in thesimulation.

-I --iris-server

Start an Iris server. This option allows an Iris-enabled debugger to connect to targets in the simulation.

-R --run Run the simulation immediately after a CADI or Iris server is started.

Use this option with --cadi-server or --iris-server.

If you do not specify this option, the simulation waits until the debugger has connected to it before itruns.

-L --cadi-log Log all CADI function calls made during the simulation into XML files.

One log file is created for each CADI target. The log files are created in the current working directory.

The filename format is:

CADIlog--.xml

-i --iris-log Log to stdout all Iris function calls that were made during the simulation.

There are 5 possible log levels. To set a level greater than 1, specify the option multiple times, forexample -ii for level 2.

The log levels have the following meanings:

0 Logging is disabled. This is the default value.

1 Log messages use a compact single-line format.

2 Log messages use a single-line pseudo-JSON format.

3 Log messages use a more readable, multi-line pseudo-JSON format.

4 As 3 but also prints the U64JSON hex value of the message.

Note

To set the Iris log level for all FVP invocations, use the IRIS_GLOBAL_INSTANCE_LOG_MESSAGESenvironment variable.

-A --iris-allow-remote

Start an Iris server and allow remote connections from another machine to it.

The default is disallowed.

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Table 2-1 CADI or Iris-related options (continued)

Shortform


-p --print-port-number

Print the port number that the Iris or CADI server is listening to.

Use this option with --cadi-server or --iris-server. Tip

This option is useful if you need to specify the port number when you connect a client to thedebug server.

--iris-portn

Set a port to use for the Iris server.

Use this option with --iris-server.

The default is 7100.

--iris-port-rangemin:max

Set the range of ports to scan when starting an Iris server. The server uses the first available port in therange.

Use this option with --iris-server.

Table 2-2 Output options

Shortform


--list-instances Print a list of model instances to standard output, then exit the simulation.

-l --list-params Print a list of model parameters to standard output, then exit the simulation. Tip

If you are loading a plug-in, this option also lists the plug-in parameters.

--list-regs Print model register information to standard output, then exit the simulation.

--check-regs Same as --list-regs but with extra consistency checks on the CADI register API.

-o --output filename Redirect lists of instances, parameters, memory, or registers to an output file.

--log filename Log all SystemC reports into filename.



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Table 2-2 Output options (continued)

Shortform


--stat Print the following performance statistics on simulation exit:

Simulated timeAn estimate of the time that the workload would have taken on the modeled hardware.

User timeTime in wall clock seconds that the host CPU spent running in user mode.

System timeTime in wall clock seconds that the host CPU spent running in system mode.

Wall timeTime in wall clock seconds between the simulation starting and stopping.

Performance indexAn estimate of the accuracy of the simulation performance. This value is Simulatedtime divided by Wall time.

-P --prefix Prefix each line of semihosting output with the target instance name.

-h --help Print the help message and exit.

--version Print version information for the FVP.

-q --quiet Suppress informational output.

-K --keep-console Keep the console window open after completion. This option applies to Windows only.

Table 2-3 Run control options

Shortform


--cpulimit n Maximum number of wall-clock seconds for the simulation process to be active. This valueexcludes simulation startup and shutdown.

This option is ignored if a debug server is started.

The default is unlimited.

--cyclelimit n Maximum number of cycles to run.



-T --timelimit n Maximum number of wall-clock seconds for the simulation to run, excluding startup and shutdown.



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Table 2-3 Run control options (continued)

Shortform


--simlimit n Maximum number of seconds to simulate.



Like the Simulated time value output by --stat, this value is measured in simulation seconds,not wall-clock seconds.

-b --break[instance=]address

Set a breakpoint on the address of an instruction.

This option can be specified multiple times.

If the FVP has multiple cores you must specify an instance, for example:

-b FVP_Base_AEMv8A.cluster0.cpu0=0x800010eC

Table 2-4 Timing and performance options

Short form Long form Description

--cpi-file filename Use filename to set the Cycle Per Instruction (CPI) class.

For information about CPI files, see Timing Annotation.

-Q --quantum n Number of ticks to simulate for each quantum. The default is 10000.

-M --min-sync-latency n Number of ticks to simulate before synchronizing. Events that occur at a higher frequencythan this value are missed. The default is 100.

Table 2-5 Memory options

Shortform


--dumpfile@address,size

Dump a section of memory into a file. This option can be specified multiple times. The syntaxis:

--dump [instance=]file@[memspace:]address,size

Note

To see a list of instances and memory space information, use the --list-memory option.

--data file@address Load raw data from file to the specified address. This option can be specified multiple times.The syntax is:

--data [instance=]file@[memspace:]address



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Table 2-5 Memory options (continued)

Shortform


--list-memory Print model memory information to standard output, then exit the simulation.

--start [instance=]address

Set the initial PC value to the start address of the application. Note

• Use this option if you do not want the CPU to start executing at the default reset address.You do not normally need to do this if you are loading an ELF file using--application.

• This option might be used with --data to load binary data that is not in an ELF file.

Table 2-6 Configuration options


-C --parameter instance.parameter=value Set a parameter. This option can be specified multiple times.

This option is also used to set plug-in parameters.

-f --config-file filename Load the parameters from a configuration file.

Table 2-7 Options for loading a plug-in or application

Shortform


-a --application[instance=] filename

Load an application.

Use this format if the FVP has multiple cores:

-a instance*=file

--plugin filename Load the plug-in filename. This option can be specified multiple times. Forinformation about plug-ins, see Plug-ins for Fast Models.

--trace-plugin filename Load a trace plug-in. Note

This option is deprecated. Use --plugin instead.

Table 2-8 Analytics options


--disable-analytics Disable product analytics gathering for the current run.

For persistent disabling, set the ARM_DISABLE_ANALYTICS environment variable.



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2.2 Loading and running an application on an FVPThere are different ways to launch an FVP, for example from the command prompt, or from ModelDebugger or Arm Development Studio.

To run an FVP from the command prompt, enter the model name followed by the model options. To seeall available options, use the --help option. This is a list of some of the commonly used options forFVPs:

-a [instance=]filename.axfSpecifies an application to load, and optionally, the instance to load it on. The file can be in oneof the following formats, or in a gzip-compressed version of it:• ELF.• Motorola S-Record.• Intel-Hex.• Verilog-Hex, in the format:

@

If the FVP contains multiple CPU instances, you can specify the instance to load the image on.The instance name can include a wildcard (*), for example:

FVP_Base_AEMv8A-AEMv8A -a cluster0.cpu*=__image.axf

Omitting the instance name loads the application on all cores in the first cluster. If the FVP hasmultiple cores but no clusters, you must specify the instance name.

--data filename.bin@addressLoads binary data into memory at the address specified.

-C instance.parameter=valueSets a single model parameter. Parameters are specified using a path that separates the instancenames and the parameter using dots. For example, -C bp.flashloader0.fname=fip.bin.Here, bp and flashloader0 are instance names and fname is the parameter. To set multipleparameters using a configuration file, use the -f option instead. To list all the availableparameters, with their type, default value, and description, invoke the model with the --list-params, or -l option.

-f config_file.txtSpecifies the name of a plain text configuration file. Configuration files simplify managingmultiple model parameters. You can set the same parameters using this option as with the -Coption.

-SStarts a CADI debug server. This option allows a CADI-enabled debugger, such as ModelDebugger or Arm Development Studio Debugger, to connect to the running model. The modelwaits for the debugger to connect before starting.

Related informationArm Development Studio User GuideModel Debugger for Fast Models User Guide

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2.3 Configuring the modelWhen you start the model from the command line, you can configure it using either:

• One or more -C command-line arguments.• A configuration file and the -f command-line argument.

Each -C command-line argument or line in the configuration file must contain:

• The name of the component instance.• The parameter to modify.• Its value.

Use the following format:

instance.parameter=value

The instance can be a hierarchical path, with each level separated by a dot “.” character. Note

• Comment lines in the configuration file begin with a # character.• You can set Boolean values using either true or false, or 1 or 0.

You can generate a configuration file with all parameters set to default values by redirecting the outputfrom the --list-params option into a new file, for example:

FVP_Base_AEMv8A.exe --list-params > params.txt

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2.4 FVP debugThis section describes how to debug an FVP.

FVP debug optionsTo debug an FVP, you can either:• Run the FVP from within a CADI-enabled debugger.• Start the FVP with the -S command-line argument and then connect a CADI-enabled debugger to it.

For information about using your debugger in these ways, see your debugger documentation.

Semihosting support

Semihosting enables code running on a platform model to directly access the I/O facilities on a hostcomputer. Examples of these facilities include console I/O and file I/O.

The simulator handles semihosting by intercepting HLT 0xF000, SVC 0x123456, or SVC 0xAB, dependingon whether the processor is in A64, A32 or T32 state. It handles all other HLTs and SVCs as normal.

If the operating system does not use HLT 0xF000, SVC 0x123456, or SVC 0xAB for its own purposes, it isnot necessary to disable semihosting support to boot an operating system.

To temporarily or permanently disable semihosting support for a current debug connection, see yourdebugger documentation.

Related informationSemihosting for AArch32 and AArch64Using semihosting to access resources on the host computer

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2.5 Using the CLCD windowWhen a Base Platform or VE FVP starts, the CLCD window opens, representing the contents of thesimulated color LCD frame buffer. It automatically resizes to match the horizontal and vertical resolutionthat is set in the CLCD peripheral registers.

Figure 2-1 CLCD window in its default state at startup

The top section of the CLCD window displays the status information.

USERSW

Eight white boxes show the state of the User DIP switches.

These represent switch S6 on the VE hardware, USERSW[8:1], which is mapped to bits [7:0] ofthe SYS_SW register at address 0x1C010004.

The switches are in the off position by default. To change its state, click in the area above orbelow a white box.

BOOTSW

Eight white boxes show the state of the VE Boot DIP switches.

These represent switch S8 on the VE hardware, BOOTSEL[8:1], which is mapped to bits [15:8]of the SYS_SW register at address 0x1C010004.

The switches are in the off position by default. Note

Changing Boot DIP switch positions while the model is running can result in unpredictablebehavior.

S6LED

Eight colored boxes indicate the state of the VE User LEDs.

These represent the red/yellow/green LEDs on the VE hardware, which are mapped to bits [7:0]of the SYS_LED register at address 0x1C010008.

Daughter

Eight white boxes show the state of the daughterboard DIP switches and eight colored boxesshow the state of the daughterboard LEDs.

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Total Instr

A counter showing the total number of instructions executed.

Because the FVP models provide a Programmer’s View (PV) of the system, the CLCD displaystotal instructions rather than total processor cycles. Timing might differ substantially from thehardware because:• Bus fabric is simplified.• Memory latencies are minimized.• Cycle approximate processor and peripheral models are used.

In general, bus transaction timing is consistent with the hardware, but the timing of operationswithin the model is not accurate.

Total Time

A counter showing the total elapsed time, in seconds.

This time is wall clock time, not simulated time.

Rate Limit

A feature that disables or enables fast simulation.

Because the system model is highly optimized, your code might run faster than it would on realhardware. This effect might cause timing issues.

Rate Limit is enabled by default. Simulation time is restricted so that it more closely matchesreal time.

To disable or enable Rate Limit, click the square button. You can configure this option wheninstantiating the model with the rate_limit-enable visualization component parameter.

When you click the Total Instr item in the CLCD, the display toggles to show the following:

Instr/sec

The number of instructions that execute per second of wall clock time.

Perf IndexThe ratio of real time to simulation time. The larger the ratio, the faster the simulation runs. Ifyou enable the Rate Limit feature, the Perf Index approaches unity.

You can reset the simulation counters by resetting the model.

The FVP CLCD displays the core run state for each core on each cluster using a colored icon. The iconsare to the left of the Total Instr (or Inst/sec) item.

Figure 2-2 Core run state icons for a dual-cluster, quad-core model



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Table 2-9 Core run state icon descriptions

Icon State label Description

UNKNOWN Run status unknown, that is, simulation has not started.

RUNNING Core running, is not idle, and is executing instructions.

HALTED External halt signal asserted.

STANDBY_WFE Last instruction executed was WFE and standby mode has been entered.

STANDBY_WFI Last instruction executed was WFI and standby mode has been entered.

IN_RESET External reset signal asserted.

DORMANT Partial core power down.

SHUTDOWN Complete core power down.

If the CLCD window has focus:• Any keyboard input is translated to PS/2 keyboard data.• Any mouse activity over the window is translated into PS/2 relative mouse motion data. The data is

then streamed to the KMI peripheral model FIFOs.

Note

The simulator only sends relative mouse motion events to the model. As a result, the host mouse pointerdoes not necessarily align with the target OS mouse pointer.

You can hide the host mouse pointer by pressing the left Ctrl+left Alt keys. Press the keys again toredisplay the host mouse pointer. Only the left Ctrl key is operational. The right Ctrl key does not havethe same effect.

If you prefer to use a different key, configure it with the trap_key visualization component parameter.

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2.6 Ethernet with VE FVPsThis section describes how to use Ethernet with VE FVPs.

Using Ethernet with VE FVPs

The VE FVPs have a virtual Ethernet component. This component is a model of the SMSC 91C111Ethernet controller, and uses a TAP device to communicate with the network. By default, the Ethernetcomponent is disabled.

Host requirements

Before you can use the Ethernet capability of VE FVPs, set up your host computer.

Target requirements

This section describes the target requirements.

Target requirements - about

The VE FVPs include a software implementation of the SMSC 91C111 Ethernet controller. Yourtarget OS must therefore include a driver for this specific device. To use the SMSC chip,configure the kernel. Linux supports the SMSC 91C111.

The configurable SMSC 91C111 component parameters are:• enabled.• mac_address.• promiscuous.

enabled

When the device is disabled, the kernel cannot detect the device.

Target OS

Drivers

SMSC91C111

TAP device

Virtual Machine

TCP/IP

Operating System

Figure 2-3 Model networking structure block diagram

To perform read and write operations on the TAP device, configure a HostBridge component.The HostBridge component is a virtual Programmer’s View (PV) model. It acts as a networkinggateway to exchange Ethernet packets with the TAP device on the host, and to forward packetsto NIC models.

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mac_address

There are two options for the mac_address parameter.

If a MAC address is not specified, when the simulator is run it takes the default MAC address,which is randomly generated. This random generation provides some degree of MAC addressuniqueness when running models on multiple hosts on a local network.

promiscuous

The Ethernet component starts in promiscuous mode by default. In this mode, it receives allnetwork traffic, even any not addressed to the device. Use this mode if you are using a singlenetwork device for multiple MAC addresses. Use this mode if, for example, you share thenetwork card between your host OS and the VE FVP Ethernet component.

By default, the Ethernet device on the VE FVP has a randomly generated MAC address andstarts in promiscuous mode.

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2.7 Using a terminal with a system modelThe Terminal component is a virtual component that enables UART data to be transferred between aTCP/IP socket on the host and a serial port on the target.

Note

To use the Terminal component with a Microsoft Windows 7 client, you must first install Telnet. TheTelnet application is not installed on Microsoft Windows 7 by default.

Download the application by following the instructions on the Microsoft web site. Search for “Windows7 Telnet” to find the Telnet FAQ page. To install Telnet:1. Select Start > Control Panel > Programs and Features to open a window that enables you to

uninstall or change programs.2. Select Turn Windows features on or off on the left side of the bar. This opens the Microsoft

Windows Features dialog. Select the Telnet Client check box.3. Click OK. The installation of Telnet might take several minutes to complete.

The following figure shows a block diagram of one possible relationship between the target and hostthrough the Terminal component. The TelnetTerminal block is what you configure when you defineTerminal component parameters. The Virtual Machine is your FVP.

Console

Driver

UART

TelnetTerminal

Telnet

TCP/IP

Serial

Virtual Machine

Target OS

Kernel

Figure 2-4 Terminal block diagram

On the target side, the console process that is invoked by your target OS relies on a suitable driver beingpresent. Such drivers are normally part of the OS kernel. The driver passes serial data through a UART.The data is forwarded to the TelnetTerminal component, which exposes a TCP/IP port to the worldoutside of the FVP. This port can be connected to by, for example, a Telnet process on the host.

By default, the FVP starts four telnet Terminals when the model is initialized. You can change the startupbehavior for each of the four Terminals by modifying the corresponding component parameters.

If the Terminal connection is broken, for example by closing a client telnet session, the port is re-openedon the host. This might have a different port number if the original one is no longer available. Before thefirst data access, you can connect a client of your choice to the network socket. If there is no existing

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connection when the first data access is made, and the start_telnet parameter is true, a host telnetsession is started automatically.

The port number of a particular Terminal instance can be defined when the FVP starts. The actual valueof the port that is used by each Terminal is declared when it starts or restarts, and might not be the valuethat you specified if the port is already in use. If you are using Model Shell, the port numbers aredisplayed in the host window in which you started the model.

You can start the Terminal component in either telnet mode or raw mode.

Telnet mode

In telnet mode, the Terminal component supports a subset of the RFC 854 protocol. This means that theTerminal participates in negotiations between the host and client concerning what is and is not supported,but flow control is not implemented.

Raw mode

Raw mode enables the byte stream to pass unmodified between the host and the target. This means thatthe Terminal component does not participate in initial capability negotiations between the host and client.It acts as a TCP/IP port. You can use this feature to directly connect to your target through the Terminalcomponent.

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2.8 Virtio P9 device componentThe VirtioP9Device component is included in Base, BaseR, and A-profile VE platforms. It implements asubset of the Plan 9 file protocol over a virtio transport. It enables accessing a directory on the host'sfilesystem within Linux, or another operating system that implements the protocol, running on a platformmodel.

Take the following steps to set up this component:• Use a version of Linux that supports v9fs over virtio and virtio-mmio devices.• Update the device tree to include the VirtioP9Device component, or specify it on the kernel

command-line, as shown below. The address range for both VE and Base platforms is0x1C140000-0x1C14FFFF.

The interrupt number is 43, or IRQ 75, for both VE and Base platforms.• Set the following parameter to the directory on the host that you want to mount in the model:

VE:motherboard.virtiop9device.root_path

Base:bp.virtiop9device.root_path

• On Linux, mount the host directory by using the following command in the model:

$ mount -t 9p -o trans=virtio,version=9p2000.L FM

Example kernel command-line argument:

virtio_mmio.device=0x10000@0x1c140000:75

Example entry for DTS files, to add next to the corresponding virtio_block entry:

virtio_p9@0140000 { compatible = "virtio,mmio"; reg = ; interrupts = ; };

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Chapter 3Base Platform FVPs

This chapter lists the Base Platform FVPs and the instances in them.

For the Base Platform memory map, see Base - memory map in the Fast Models Reference Manual.

It contains the following sections:• 3.1 FVP_Base_AEMv8A on page 3-35.• 3.2 FVP_Base_AEMv8A-AEMv8A on page 3-43.• 3.3 FVP_Base_AEMvA on page 3-54.• 3.4 FVP_Base_Cortex-A32x1 on page 3-62.• 3.5 FVP_Base_Cortex-A32x2 on page 3-70.• 3.6 FVP_Base_Cortex-A32x4 on page 3-78.• 3.7 FVP_Base_Cortex-A35x1 on page 3-87.• 3.8 FVP_Base_Cortex-A35x2 on page 3-95.• 3.9 FVP_Base_Cortex-A35x4 on page 3-103.• 3.10 FVP_Base_Cortex-A53x1 on page 3-112.• 3.11 FVP_Base_Cortex-A53x2 on page 3-120.• 3.12 FVP_Base_Cortex-A53x4 on page 3-128.• 3.13 FVP_Base_Cortex-A55 on page 3-137.• 3.14 FVP_Base_Cortex-A55+Cortex-A76 on page 3-146.• 3.15 FVP_Base_Cortex-A55x1 on page 3-155.• 3.16 FVP_Base_Cortex-A55x1+Cortex-A75x1 on page 3-163.• 3.17 FVP_Base_Cortex-A55x2 on page 3-172.• 3.18 FVP_Base_Cortex-A55x2+Cortex-A75x2 on page 3-180.• 3.19 FVP_Base_Cortex-A55x4 on page 3-189.• 3.20 FVP_Base_Cortex-A55x4+Cortex-A75x1 on page 3-198.• 3.21 FVP_Base_Cortex-A55x4+Cortex-A75x2 on page 3-207.• 3.22 FVP_Base_Cortex-A55x4+Cortex-A75x4 on page 3-216.


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• 3.23 FVP_Base_Cortex-A55x4+Cortex-A76x2 on page 3-225.• 3.24 FVP_Base_Cortex-A57x1 on page 3-234.• 3.25 FVP_Base_Cortex-A57x1-A35x1 on page 3-242.• 3.26 FVP_Base_Cortex-A57x1-A53x1 on page 3-252.• 3.27 FVP_Base_Cortex-A57x2 on page 3-262.• 3.28 FVP_Base_Cortex-A57x2-A35x4 on page 3-270.• 3.29 FVP_Base_Cortex-A57x2-A53x4 on page 3-280.• 3.30 FVP_Base_Cortex-A57x4 on page 3-290.• 3.31 FVP_Base_Cortex-A57x4-A35x4 on page 3-299.• 3.32 FVP_Base_Cortex-A57x4-A53x4 on page 3-310.• 3.33 FVP_Base_Cortex-A65AEx2 on page 3-321.• 3.34 FVP_Base_Cortex-A65AEx2+Cortex-A76AEx2 on page 3-330.• 3.35 FVP_Base_Cortex-A65AEx4 on page 3-339.• 3.36 FVP_Base_Cortex-A65AEx4+Cortex-A76AEx4 on page 3-349.• 3.37 FVP_Base_Cortex-A65AEx8 on page 3-359.• 3.38 FVP_Base_Cortex-A65x1 on page 3-370.• 3.39 FVP_Base_Cortex-A65x2 on page 3-378.• 3.40 FVP_Base_Cortex-A65x4 on page 3-386.• 3.41 FVP_Base_Cortex-A72x1 on page 3-395.• 3.42 FVP_Base_Cortex-A72x1-A53x1 on page 3-403.• 3.43 FVP_Base_Cortex-A72x2 on page 3-413.• 3.44 FVP_Base_Cortex-A72x2-A53x4 on page 3-421.• 3.45 FVP_Base_Cortex-A72x4 on page 3-431.• 3.46 FVP_Base_Cortex-A72x4-A53x4 on page 3-440.• 3.47 FVP_Base_Cortex-A73x1 on page 3-451.• 3.48 FVP_Base_Cortex-A73x1-A53x1 on page 3-459.• 3.49 FVP_Base_Cortex-A73x2 on page 3-469.• 3.50 FVP_Base_Cortex-A73x2-A53x4 on page 3-477.• 3.51 FVP_Base_Cortex-A73x4 on page 3-487.• 3.52 FVP_Base_Cortex-A73x4-A53x4 on page 3-496.• 3.53 FVP_Base_Cortex-A75 on page 3-507.• 3.54 FVP_Base_Cortex-A75x1 on page 3-515.• 3.55 FVP_Base_Cortex-A75x2 on page 3-523.• 3.56 FVP_Base_Cortex-A75x4 on page 3-531.• 3.57 FVP_Base_Cortex-A76 on page 3-540.• 3.58 FVP_Base_Cortex-A76AEx2 on page 3-548.• 3.59 FVP_Base_Cortex-A76AEx4 on page 3-557.• 3.60 FVP_Base_Cortex-A76x1 on page 3-567.• 3.61 FVP_Base_Cortex-A76x2 on page 3-575.• 3.62 FVP_Base_Cortex-A76x4 on page 3-583.• 3.63 FVP_Base_Cortex-A77x1 on page 3-592.• 3.64 FVP_Base_Cortex-A77x2 on page 3-600.• 3.65 FVP_Base_Cortex-A77x4 on page 3-608.• 3.66 FVP_Base_Cortex-A78x1 on page 3-617.• 3.67 FVP_Base_Cortex-A78x2 on page 3-625.• 3.68 FVP_Base_Cortex-A78x4 on page 3-633.• 3.69 FVP_Base_Cortex-X1x1 on page 3-642.• 3.70 FVP_Base_Cortex-X1x2 on page 3-650.• 3.71 FVP_Base_Cortex-X1x4 on page 3-658.• 3.72 FVP_Base_Neoverse-E1x1 on page 3-667.• 3.73 FVP_Base_Neoverse-E1x2 on page 3-675.• 3.74 FVP_Base_Neoverse-E1x4 on page 3-683.• 3.75 FVP_Base_Neoverse-N1 on page 3-692.• 3.76 FVP_Base_Neoverse-N1x1 on page 3-701.• 3.77 FVP_Base_Neoverse-N1x2 on page 3-709.• 3.78 FVP_Base_Neoverse-N1x4 on page 3-717.

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• 3.79 FVP_Base_RevC-2xAEMv8A on page 3-726.• 3.80 FVP_Base_RevC-2xAEMvA on page 3-739.

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3.1 FVP_Base_AEMv8AFVP_Base_AEMv8A contains the following instances:

Table 3-1 FVP_Base_AEMv8A instances

Name Type Description

FVP_Base_AEMv8A FVP_Base_AEMv8A

Base Platform Compute Subsystem for ARMAEMv8AMPCT.

FVP_Base_AEMv8A.bp BasePlatformPeripherals

Peripherals and address map for the Base Platform.

FVP_Base_AEMv8A.bp.Timer_0_1 SP804_Timer ARM Dual-Timer Module(SP804).

FVP_Base_AEMv8A.bp.Timer_0_1.clk_div0

ClockDivider A ClockDivider is a library component that takes a ClockSignalon its input port (which could come from the output of aMasterClock, or from another ClockDivider), and generates a newClockSignal on its output port, representing a clock frequency thatis related to the input clock by the ratio of the multiply and divideparameters.



FVP_Base_AEMv8A.bp.Timer_0_1.counter0

CounterModule Internal component used by SP804 Timer module.



FVP_Base_AEMv8A.bp.Timer_2_3 SP804_Timer ARM Dual-Timer Module(SP804).









FVP_Base_AEMv8A.bp.ap_refclk MemoryMappedGenericTimer

ARM Generic Timer.

FVP_Base_AEMv8A.bp.audioout AudioOut_SDL SDL based Audio Output for PL041_AACI.

3 Base Platform FVPs3.1 FVP_Base_AEMv8A


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https://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/SP804_Timerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Other-components/CounterModulehttps://developer.arm.com/docs/100964/latest/fast-models-components/Other-components/CounterModulehttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/SP804_Timerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Other-components/CounterModulehttps://developer.arm.com/docs/100964/latest/fast-models-components/Other-components/CounterModulehttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/MemoryMappedGenericTimerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/MemoryMappedGenericTimerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/AudioOut_SDL

Table 3-1 FVP_Base_AEMv8A instances (continued)


FVP_Base_AEMv8A.bp.clock100Hz ClockDivider A ClockDivider is a library component that takes a ClockSignalon its input port (which could come from the output of aMasterClock, or from another ClockDivider), and generates a newClockSignal on its output port, representing a clock frequency thatis related to the input clock by the ratio of the multiply and divideparameters.

FVP_Base_AEMv8A.bp.clock24MHz ClockDivider A ClockDivider is a library component that takes a ClockSignalon its input port (which could come from the output of aMasterClock, or from another ClockDivider), and generates a newClockSignal on its output port, representing a clock frequency thatis related to the input clock by the ratio of the multiply and divideparameters.


FVP_Base_AEMv8A.bp.clock32KHz ClockDivider A ClockDivider is a library component that takes a ClockSignalon its input port (which could come from the output of aMasterClock, or from another ClockDivider), and generates a newClockSignal on its output port, representing a clock frequency thatis related to the input clock by the ratio of the multiply and divideparameters.


FVP_Base_AEMv8A.bp.clock50Hz ClockDivider A ClockDivider is a library component that takes a ClockSignalon its input port (which could come from the output of aMasterClock, or from another ClockDivider), and generates a newClockSignal on its output port, representing a clock frequency thatis related to the input clock by the ratio of the multiply and divideparameters.

FVP_Base_AEMv8A.bp.clockCLCD ClockDivider A ClockDivider is a library component that takes a ClockSignalon its input port (which could come from the output of aMasterClock, or from another ClockDivider), and generates a newClockSignal on its output port, representing a clock frequency thatis related to the input clock by the ratio of the multiply and divideparameters.

FVP_Base_AEMv8A.bp.clockdivider ClockDivider A ClockDivider is a library component that takes a ClockSignalon its input port (which could come from the output of aMasterClock, or from another ClockDivider), and generates a newClockSignal on its output port, representing a clock frequency thatis related to the input clock by the ratio of the multiply and divideparameters.



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https://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDivider



FVP_Base_AEMv8A.bp.dmc RAMDevice RAM device, can be dynamic or static ram.

FVP_Base_AEMv8A.bp.dmc_phy RAMDevice RAM device, can be dynamic or static ram.

FVP_Base_AEMv8A.bp.dram RAMDevice RAM device, can be dynamic or static ram.

FVP_Base_AEMv8A.bp.dram_alias_warning

WarningMemory Memory that prints warnings, and RAZ/WIs or aborts.

FVP_Base_AEMv8A.bp.dummy_CF WarningMemory Memory that prints warnings, and RAZ/WIs or aborts.

FVP_Base_AEMv8A.bp.dummy_local_dap_rom

RAMDevice RAM device, can be dynamic or static ram.

FVP_Base_AEMv8A.bp.dummy_ram RAMDevice RAM device, can be dynamic or static ram.

FVP_Base_AEMv8A.bp.dummy_usb RAMDevice RAM device, can be dynamic or static ram.

FVP_Base_AEMv8A.bp.exclusive_monitor

PVBusExclusiveMonitor

Global exclusive monitor.

FVP_Base_AEMv8A.bp.flash0 IntelStrataFlashJ3 Intel Strata Flash J3 LISA+ model.

FVP_Base_AEMv8A.bp.flash1 IntelStrataFlashJ3 Intel Strata Flash J3 LISA+ model.

FVP_Base_AEMv8A.bp.flashloader0 FlashLoader A device that can preload a gzipped image into flash at startup.

FVP_Base_AEMv8A.bp.flashloader1 FlashLoader A device that can preload a gzipped image into flash at startup.

FVP_Base_AEMv8A.bp.generic_watchdog

MemoryMappedGenericWatchdog

ARM Generic Watchdog.

FVP_Base_AEMv8A.bp.hdlcd0 PL370_HDLCD ARM PrimeCell HD Color LCD Controller (Nominal DesignationPL370).

FVP_Base_AEMv8A.bp.hdlcd0.timer ClockTimerThread A ClockTimerThread(64) is a drop-in replacement for aClockTimer(64) component. The main difference to theClockTimer component is that the ClockTimerThread runs thesignal() callback from a proper scheduler thread. This mean thatthe signal() function may directly or indirectly invoke wait()functions to wait for time or events. This is not allowed for theClockTimer component which does not use a thread. Componentswhich issue bus transactions from within the timer signal()callback must use ClockTimerThread(64) rather thanClockTimer(64).

FVP_Base_AEMv8A.bp.hdlcd0.timer.timer

ClockTimerThread64

A ClockTimerThread64 is a drop-in replacement forClockTimer64. The main difference to the ClockTimer componentis that the ClockTimerThread runs the signal() callback from aproper scheduler thread. This mean that the signal() function maydirectly or indirectly invoke wait() functions to wait for time orevents. This is not allowed for the ClockTimer component whichdoes not use a thread. Components which issue bus transactionsfrom within the timer signal() callback must useClockTimerThread(64) rather than ClockTimer(64).

FVP_Base_AEMv8A.bp.hdlcd0.timer.timer.thread

SchedulerThread A SchedulerThread instance represents a co-routine thread in thesimulation.

FVP_Base_AEMv8A.bp.hdlcd0.timer.timer.thread_event

SchedulerThreadEvent

A SchedulerThreadEvent instance is an auto-reset booleancondition variable other threads can wait on.



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https://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/RAMDevicehttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/RAMDevicehttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/RAMDevicehttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/WarningMemoryhttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/WarningMemoryhttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/RAMDevicehttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/RAMDevicehttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/RAMDevicehttps://developer.arm.com/docs/100964/latest/fast-models-components/Bus-components/PVBusExclusiveMonitorhttps://developer.arm.com/docs/100964/latest/fast-models-components/Bus-components/PVBusExclusiveMonitorhttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/IntelStrataFlashJ3https://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/IntelStrataFlashJ3https://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/FlashLoaderhttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/FlashLoaderhttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/MemoryMappedGenericWatchdoghttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/MemoryMappedGenericWatchdoghttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/PL370_HDLCDhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockTimerThreadhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockTimerThread64https://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockTimerThread64https://developer.arm.com/docs/100964/latest/fast-models-components/Other-components/SchedulerThreadhttps://developer.arm.com/docs/100964/latest/fast-models-components/Other-components/SchedulerThreadEventhttps://developer.arm.com/docs/100964/latest/fast-models-components/Other-components/SchedulerThreadEvent



FVP_Base_AEMv8A.bp.hdlcd0_labeller Labeller -

FVP_Base_AEMv8A.bp.hostbridge HostBridge Host Socket Interface Component.

FVP_Base_AEMv8A.bp.mmc MMC Generic Multimedia Card.

FVP_Base_AEMv8A.bp.nontrustedrom IntelStrataFlashJ3 Intel Strata Flash J3 LISA+ model.

FVP_Base_AEMv8A.bp.nontrustedromloader

FlashLoader A device that can preload a gzipped image into flash at startup.

FVP_Base_AEMv8A.bp.pl011_uart0 PL011_Uart ARM PrimeCell UART(PL011).

FVP_Base_AEMv8A.bp.pl011_uart0.clk_divider











FVP_Base_AEMv8A.bp.pl031_rtc PL031_RTC ARM PrimeCell Real Time Clock(PL031).

FVP_Base_AEMv8A.bp.pl041_aaci PL041_AACI ARM PrimeCell Advanced Audio CODEC Interface(PL041).

FVP_Base_AEMv8A.bp.pl050_kmi0 PL050_KMI ARM PrimeCell PS2 Keyboard/Mouse Interface(PL050).

FVP_Base_AEMv8A.bp.pl050_kmi0.clk_divider




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https://developer.arm.com/docs/100964/latest/fast-models-components/Bus-components/Labellerhttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/HostBridgehttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/MMChttps://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/IntelStrataFlashJ3https://developer.arm.com/docs/100964/latest/fast-models-components/Peripheral-components/FlashLoaderhttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/PL011_Uarthttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/PL011_Uarthttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/PL011_Uarthttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/PL011_Uarthttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDividerhttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/PL031_RTChttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/PL041_AACIhttps://developer.arm.com/docs/100964/latest/fast-models-components/SystemIP-components/PL050_KMIhttps://developer.arm.com/docs/100964/latest/fast-models-components/Clocking-components/ClockDivider



FVP_Base_AEMv8A.bp.pl050_kmi1 PL050_KMI ARM PrimeCell PS2 Keyboard/Mouse Interface(PL050).

FVP_Base_AEMv8A.bp.pl050_kmi1.clk_divider


FVP_Base_AEMv8A.bp.pl111_clcd PL111_CLCD ARM PrimeCell Color LCD Controller(PL111).

FVP_Base_AEMv8A.bp.pl111_clcd.pl11x_clcd

PL11x_CLCD Internal component used by PL110 and PL111 CLCD controllers.

FVP_Base_AEMv8A.bp.pl111_clcd.pl11x_clcd.timer

ClockTimerThread A ClockTimerThread(64) is a drop-in replacement for aClockTimer(64) component. The main difference to theClockTimer component is that the ClockTimerThread runs thesignal() callback from a proper scheduler thread. This mean thatthe signal() function may directly or indirectly invoke wait()functions to wait for time or events. This is not allowed for theClockTimer component which does not use a thread. Componentswhich issue bus transactions from within the timer signal()callback must use ClockTimerThread(64) rather thanClockTimer(64).

FVP_Base_AEMv8A.bp.pl111_clcd.pl11x_clcd.timer.timer

ClockTimerThread64

A ClockTimerThread64 is a drop-in replacement forClockTimer64. The main difference to the ClockTimer componentis that the ClockTimerThread runs the signal() callback from aproper scheduler thread. This mean that the signal() function maydirectly or indirectly invoke wait() functions to wait for time orevents. This is not allowed for the ClockTimer component whichdoes not use a thread. Components which issue bus transactionsfrom within the timer signal() callback must useClockTimerThread(64) rather than ClockTimer(64).

FVP_Base_AEMv8A.bp.pl111_clcd.pl11x_clcd.timer.timer.thread

SchedulerThread A SchedulerThread instance represents a co-routine thread in thesimulation.

FVP_Base_AEMv8A.bp.pl111_clcd.pl1

) reference guide · 2020. 6. 12. · 1105-00 23 november 2018 non-confidential update for v11.5....

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