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© 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Sagitrón Jornadas MMIVJornadas MMIV / 2-INSTR / / 2-INSTR / 11
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PICmicro PICmicro de 28de 28
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• 12-bit core
• 14-bit core
• 16-bit core
• 16-bit enh. core
33 instructions33 instructions
Easy to learnEasy to learn High compactionHigh compaction Very powerful single-word instructions Very powerful single-word instructions All single- cycle except program branchesAll single- cycle except program branches Upward compatibility of instructionsUpward compatibility of instructions
35 instructions35 instructions
58 instructions58 instructions 72+4 instructions72+4 instructions
R I S C R I S C
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Byte-Oriented Operations
Decrement f, skip if zero
No OperationMove W to fClear WClear fSubtract W from fDecrement fInclusive OR W and fAND W and fExclusive OR W and fAdd W and fMove fComplement fIncrement f
Rotate right fRotate left fSwap halves fIncrement f, skip if zero
NOP -MOVWF fCLRW -CLRF fSUBWF f,dDECF f,dIORWF f,dANDWF f,dXORWF f,dADDWF f,dMOVF f,dCOMF f,dINCF f,dDECFSZf,dRRF f,dRLF f,dSWAPF f,dINCFSZ f,d
Bit-Oriented Operations
Bit clear fBit set fBit test f, skip if clearBit test f, skip if set
BCF f,bBSF f,bBTFSC f,bBTFSS f,b
Literal and Control Operations
Go into standby modeClear Watchdog TimerReturn, place Literal WOption Tris PortCall SubroutineGo to addressMove Literal to W
SLEEPCLRWDTRETLWOPTIONTRISFCALLGOTOMOVLW
--k-faak
AND Literal WInclusive OR Literal WExclusive OR Literal W
ANDLWIORLWXORLW
kkk
f = file register address d = destination selecta = program addressb = bit k = literal
Instrucciones PIC16C5X (33): Instrucciones PIC16C5X (33):
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OP CODEOP CODE
Codificación instrucciones 12-bit Codificación instrucciones 12-bit
Byte Oriented OperationsByte Oriented Operations
OP CODEOP CODE dd ff ff ff ff ff
Bit Oriented OperationsBit Oriented Operations
OP CODEOP CODE bb ff ff ff ff ffbb bb
kk
Literal OperationsLiteral Operations
kk kk kk kk kk kk kk
OP CODEOP CODE xx aa aa aa
PC call and gotoPC call and goto
aa aa aa aa aa
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Indirect addr* TMR0 PCL STATUS FSR PORT A PORT B PORT C X X
X X
X X X X X X X X
X X X X X X X X Bank 0 Bank 1 Bank 2 Bank 3
* Not a physical register
00
0F
10
1F
Mapa de Registros PIC16C5X Mapa de Registros PIC16C5X
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• 5-bit direct address from the instruction
• 2-bit from FSR register
Effective 7-bit Register AddressEffective 7-bit Register Address
RA1RA1RA0RA0 OP CODEOP CODE
FSR RegisterFSR Register 12-bit Instruction12-bit Instruction
ff ff ff ff ff
RA1RA1 RA0RA0 ff ff ff ff ff
5-bits From Instruction Word5-bits From Instruction Word
2-bits From2-bits FromFSR FSR
RegisterRegister
Direccionamiento Directo PIC16C5X Direccionamiento Directo PIC16C5X
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• 5-bit indirect address from the FSR (File Select Register).
• 2-bit from FSR register
Effective 7-bit Register AddressEffective 7-bit Register Address
RA1RA1RA0RA0
FSR RegisterFSR Register File Select RegisterFile Select Register
ff ff ff ff ff
RA1RA1 RA0RA0 ff ff ff ff ff
5-bits From FSR5-bits From FSR
2-bits From2-bits FromFSR FSR
RegisterRegister
Direccionamiento Indirecto PIC16C5X Direccionamiento Indirecto PIC16C5X
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Clear all RAM locations from 0x10 to 0x1F. Indirect address is loaded into FSR. Every time INDF is used as operand, register pointed to by FSR is actually used.
Clear all RAM locations from 0x10 to 0x1F. Indirect address is loaded into FSR. Every time INDF is used as operand, register pointed to by FSR is actually used.
movlwmovlw 0x100x10movwfmovwf FSRFSR
LOOPLOOP clrfclrf INDFINDFincfincf FSR,FFSR,Fbtfscbtfsc FSR,4FSR,4gotogoto LOOPLOOP<next instruction><next instruction>
XXXX XXXXXXXX XXXX
0000 00000000 0000
FSR = 10hFSR = 10h
INDFINDF00h00h
04h04h
10h10h
1Fh1Fh
Data MemoryData Memory
Direccionamiento Indirecto PIC16C5X Direccionamiento Indirecto PIC16C5X
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• GOTO: 9-bit destination address is loaded into PC <8:0>. The upper 2-bit PC <10:9> are loaded from STATUS <6:5> allowing 4x512 (2K) addressing range. GOTO
1 0 1 a a a a a a a a a
PCL
STATUS
x p p x x x x x
p p a a a a a a a a a
GOTO: Salto Incondicional PIC16C5X GOTO: Salto Incondicional PIC16C5X
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• CALL: 8-bit destination address is loaded into PC <7:0>. PC <8> is forced to “0”. The upper 2-bit PC <10:9> are loaded from STATUS <6:5> allowing lower half of 4x512 (1K) addressing range. It means that all subrutine entry must be located in the lower half of any page. • RETLW: PC <10:0> is loaded from the top of the stack.
1 0 0 1 a a a a a a a a
PCL
STATUS
x p p x x x x x
p p 0 a a a a a a a a
CALL
CALL: Llamada a Rutina PIC16C5X CALL: Llamada a Rutina PIC16C5X
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• WRITE to PC: When the PC is the destination of any instruction, the computed 8-bit value will be loaded into PC <7:0>. PC <8> is forced to “0”. The upper 2-bit PC <10:9> are loaded from STATUS <6:5> allowing lower half of 4x512 (1K) addressing range. It means that any computed jump must be located in the lower half of any page.
WRITE to PC
d d d d d d d d
PCL
STATUS
x p p x x x x x
p p 0 a a a a a a a a
Escritura en el PC: PIC16C5X Escritura en el PC: PIC16C5X
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Byte-Oriented Operations
Decrement f, skip if zero
No OperationMove W to fClear WClear fSubtract W from fDecrement fInclusive OR W and fAND W and fExclusive OR W and fAdd W and fMove fComplement fIncrement f
Rotate right fRotate left fSwap halves fIncrement f, skip if zero
NOPMOVWFCLRWCLRFSUBWFDECFIORWFANDWFXORWFADDWFMOVFCOMFINCFDECFSZRRFRLFSWAPFINCFSZ
-f-
ff,df,df,df,df,df,df,df,df,df,df,df,df,df,d
Bit-Oriented Operations
Bit clear fBit set fBit test f, skip if clearBit test f, skip if set
BCF f,bBSF f,bBTFSC f,bBTFSS f,b
Literal and Control Operations
Go into standby modeClear Watchdog TimerReturn, place Literal WReturn from interruptReturnCall SubroutineGo to addressMove Literal to WAdd Literal to WSubtract Literal from WAND Literal WInclusive OR Literal WExclusive OR Literal W
SLEEPCLRWDTRETLWRETFIERETURNCALLGOTOMOVLWADDLWSUBLWANDLWIORLWXORLW
--k--aakkkkkkf = file register address
d = destination selecta = program addressb = bit k = literal
Instrucciones PIC16FXXX (35): Instrucciones PIC16FXXX (35):
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Codificación instrucciones 14-bit Codificación instrucciones 14-bit
Byte Oriented OperationsByte Oriented Operations
OP CODEOP CODE dd ff ff ff ff ff ff ff
Bit Oriented OperationsBit Oriented Operations
OP CODEOP CODE bb ff ff ff ff ff ff ffbb bb
kk
Literal OperationsLiteral Operations
OP CODEOP CODE kk kk kk kk kk kk kk
OP CODEOP CODE aa aa aa aa
PC call and gotoPC call and goto
aa aa aa aa aa aa aa
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* Not a physical register
8000
Bank 2 Bank 3
FF7F
Indirect addr*OPTION
PCLSTATUS
FSRTRIS ATRIS B
XXX
PCLATHINTCON
XXX
Bank 1
Indirect addr*TMR0PCL
STATUSFSR
PORT APORT B
XXX
PCLATHINTCON
XXX
Bank 0
Mapa de Registros PIC16FXXX Mapa de Registros PIC16FXXX
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• 7-bit direct address from the instruction
• 2-bit from STATUS register
Effective 9-bit Register AddressEffective 9-bit Register Address
IRPIRP RP1RP1 RP0RP0 OP CODEOP CODETOTO PDPD ZZ DCDC CC
STATUS RegisterSTATUS Register 14-bit Instruction14-bit Instruction
ff ff ff ff ff ff ff
RP1RP1 RP0RP0 ff ff ff ff ff ff ff
7-bits From Instruction Word7-bits From Instruction Word
2-bits From2-bits FromSTATUS STATUS RegisterRegister
Direccionamiento Directo PIC16FXXX Direccionamiento Directo PIC16FXXX
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IRPIRP ff ff ff ff ff ff ff ff
ff
• 8-bit indirect address from the FSR (File Select Register).
• 1-bit from STATUS register.
• 8-bit indirect address from the FSR (File Select Register).
• 1-bit from STATUS register.
IRPIRP RP1RP1 RP0RP0 TOTO PDPD ZZ DCDC CC ff ff ff ff ff ff ff
STATUS RegisterSTATUS Register 8-bit FSR Register8-bit FSR Register
Effective 9-bit Register AddressEffective 9-bit Register Address
8-bits From FSR8-bits From FSR
1-bit From1-bit FromSTATUS STATUS RegisterRegister
Direccionamiento Indirecto PIC16FXXX Direccionamiento Indirecto PIC16FXXX
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Clear all RAM locations from 0x20 to 0x7F. Indirect address is loaded into FSR. Every time INDF is used as operand, register pointed to by FSR is actually used.
Clear all RAM locations from 0x20 to 0x7F. Indirect address is loaded into FSR. Every time INDF is used as operand, register pointed to by FSR is actually used.
movlwmovlw 0x200x20movwfmovwf FSRFSR
LOOPLOOP clrfclrf INDFINDFincfincf FSR,FFSR,Fbtfssbtfss FSR,7FSR,7gotogoto LOOPLOOP<next instruction><next instruction>
0000 00000000 0000
0000 00000000 0000
FSR = 20hFSR = 20h
INDFINDF00h00h
04h04h
20h20h
7Fh7Fh
Data MemoryData Memory
Direccionamiento Indirecto PIC16FXXX Direccionamiento Indirecto PIC16FXXX
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8-bit constant (literal) value included in instruction word.
Used by literal instructions such as movlw, addlw, retlw, etc.
8-bit constant (literal) value included in instruction word.
Used by literal instructions such as movlw, addlw, retlw, etc.
OP CODEOP CODE kk
14-bit Instruction for Literal Instructions14-bit Instruction for Literal Instructions
kk kk kk kk kk kk kk
Direccionamiento Inmediato PIC16FXXX Direccionamiento Inmediato PIC16FXXX
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xx xx xx pp pp xx xx xx
pp pp aa aa aa aa aa aa aa aa aa aa aa
• GOTO: 11-bit destination address is loaded into PC <10:0>. The upper 2-bit PC <12:11> are loaded from PCLATH <4:3> allowing 4x2K (8K) addressing range.
PCLATH
GOTO: Salto Incondicional PIC16FXXX GOTO: Salto Incondicional PIC16FXXX
OP CODEOP CODE aa aa aa aa aa aa aa aa aa aa aa
Program Counter
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xx xx xx pp pp xx xx xx
pp pp aa aa aa aa aa aa aa aa aa aa aa
• CALL: 11-bit destination address is loaded into PC <10:0>. The upper 2-bit PC <12:11> are loaded from PCLATH <4:3> allowing 4x2K (8K) addressing range.
PCLATH
CALL: Llamada a Rutina PIC16FXXX CALL: Llamada a Rutina PIC16FXXX
OP CODEOP CODE aa aa aa aa aa aa aa aa aa aa aa
Program Counter
• RETLW, RETURN and RETFIE: PC <12:0> is loaded from the top of the stack. PCLATH is unchanged.
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PCH <5>PCH <5> PCL <8>PCL <8>
13-Bit Program Counter13-Bit Program Counter
PCLATH <5>PCLATH <5>
Internal Data Bus <8>Internal Data Bus <8>
55
55
88
First write high byte to First write high byte to PCLATH.PCLATH.
Next write low byte to Next write low byte to PCL, this loads the entire PCL, this loads the entire 13-bit value to PC.13-bit value to PC.
Reading the PC Reading the PC Read low byte Read low byte from PCLfrom PCL PCLATH is PCLATH is NOTNOT
loaded with loaded with value from PCHvalue from PCH
Direccionamiento Relativo PC PIC16FXXX Direccionamiento Relativo PC PIC16FXXX
Used to perform a computed goto by adding an offset directly to the 13-bit Program Counter (8K addressing).
Used to perform a computed goto by adding an offset directly to the 13-bit Program Counter (8K addressing).
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• • Do NOT use OPTION AND TRIS Do NOT use OPTION AND TRIS instructions instructions on 14 bit coreon 14 bit core devices. devices. • • These Instructions are not in the 12 bit core:These Instructions are not in the 12 bit core:
ADDLW ADDLW - Add literal k to contents of W register - Add literal k to contents of W registerSUBLW SUBLW - Subtract W from Literal - Subtract W from LiteralRETURN RETURN - Return from subroutine - Return from subroutine RETFIE RETFIE - Return from interrupt subroutine - Return from interrupt subroutine
Instrucciones 12-bit < > 14-bit Instrucciones 12-bit < > 14-bit
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Byte-Oriented Operations
No Operation NOP - Clear f CLRF f,s Set f SETF f,s Move W to f MOVWF f Move f to p MOVFP f,p Move p to f MOVPF p,f Negate W NEGW f,s Complement f COMF f,d AND W with f ANDWF f,d Incl OR W with f IORWF f,d Excl OR W with f XORWF f,d Add W with f ADDWF f,d Add W with f + CY ADDWFC f,d Sub W with f SUBWF f,d Sub W with f + BW SUBWFB f,d Decimal Adjust W DAW f,s Swap f SWAPF f,d Multiply W with f MULWF f
Byte-Oriented Operations
f / p = file / peripheral register address t = Table latch high or low tranfer d / s = destination select i = Autoincrement pointera = program addressb = bit k = literal
Decrement f DECF f,d Decr f skip if ZR DECFSZ f,d Decr f skip if NZR DCFSNZ f,d Increment f INCF f,d Incr f skip if ZR INCFSZ f,d Incr f skip if NZR INFSNZ f,d Comp f-W skip if = CPFSEQ f Comp f-W skip if > CPFSGT f Comp f-W skip if < CPFSLT f Test f skip if ZR TSTFSZ f Rotate left f with CY RLCF f,d Rotate left f without CY RLNCF f,d Rotate right f with CY RRCF f,d Rotate right f without CY RRNCF f,d Table read TABLRD t,i,f Table write TABLWT t,i,f Table latch read TLRD t,f Table latch write TLWT t,f
Instrucciones PIC17CXXX (58): ... Instrucciones PIC17CXXX (58): ...
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Bit-Oriented Operations
Bit clear f BCF f,b Bit set f BSF f,b Bit toggle f BTG f,b Bit test skip 0 BTFSC f,b Bit test skip 1 BTFSS f,b
Literal and Control Operations
f / p = file / peripheral register address t = Table latch high or low tranfer d / s = destination select i = Autoincrement pointera = program addressb = bit k = literal
Move literal to W MOVLW k Move literal low BSR MOVLB k Move literal high BSR MOVLR k AND literal with W ANDLW k Incl OR literal with W IORLW k Excl OR literal with W XORLW k Add literal with W ADDLW k Sub literal with W SUBLW k Multiply Lit with W MULLW k Go to address GOTO a Subrutine call CALL a Subrutine Long call LCALL a Return literal to W RETLW k Return subrutine RETURN - Return from int. RETFIE - Clear Watchdog CLRWDT - Go to standby mode SLEEP -
... Instrucciones PIC17CXXX (58): ... Instrucciones PIC17CXXX (58):
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Byte-Oriented & LiteralAdd literal with Wreg ADDLW kAdd Wreg with f ADDWF f,d,a Add Wreg with f + carry ADDWFC f,d,a And literal with Wreg ANDLW kAnd Wreg with f ANDWF f,d,a Clear f CLRF f,a Complement f COMF f,d,a Compare f with Wreg, skip if = CPFSEQ f,a Compare f with Wreg, skip if > CPFSGT f,a Compare f with Wreg, skip if < CPFSLT f,a Decimal adjust Wreg DAW Decrement f DECF f,d,a Decrement f, Skip if 0 DECFSZ f,d,a Decrement f, Skip if /0 DCFSNZ f,d,a Increment f INCF f,d,a Increment f, Skip if 0 INCFSZ f,d,a Increment f, Skip if /0 INFSNZ f,d,a Inclusive OR literal with Wreg IORLW kInclusive OR Wreg with f IORWF f,d,a Move literal to FSRx LFSR x,k
f = file register address d = destination select a = banck selectn&p = program address b = bit k = literal s = shadow reg.
Instrucciones PIC18FXXXX (76): ... Instrucciones PIC18FXXXX (76): ...
Move f MOVF f,d,a Move fs(source) to fd(destin) MOVFF fs,fdMove literal to BSR MOVLB k Move literal to Wreg MOVLW k Move Wreg to f MOVWF f,a Multiply literal with Wreg MULLW k Multiply Wreg with f MULWF f,a Negate f NEGF f,a Rotate Left f through carry RLCF f,d,a Rotate Left f (no carry) RLNCF f,d,a Rotate Right f through carry RRCF f,d,a Rotate Right f (no carry) RRNCF f,d,a Set f SETF f,a Subtract f from Wreg + borrow SUBFWB f,d,a Subtract Wreg from literal SUBLW k Subtract Wreg from f SUBWF f,d,a Subtract Wreg from f + borrow SUBWFB f,d,a Swap nibbles in f SWAPF f,d,a Test f, skip if 0 TSTFSZ f,a Exclusive OR literal with Wreg XORLW kExclusive OR Wreg with f XORWF f,d,a
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Control operationsBranch if carry BC n Branch if no carry BNC n Branch if negative BN n Branch if no negative BNN n Branch if overflow BOV n Branch if no overflow BNOV n Branch if zero BZ n Branch if no zero BNZ n Branch unconditionally BRA n Go to address GOTO p Relative call RCALL n Call subroutine CALL p,s Return from subroutine RETURN s Return with literal in Wreg RETLW k Return from interrupt enable RETFIE s Pop top of return stack POP Push top of return stack PUSH No operation NOP No operation 2nd wordClear watchdog timer CLRWDT Change into standby mode SLEEP Software device reset RESET
... Instrucciones PIC18FXXXX (76): ... Instrucciones PIC18FXXXX (76):
Bit clear into f BCF f,b,a Bit set into f BSF f,b,a Bit toggle into f BTF f,b,a Bit test f, skip if clear BTFSC f,b,a Bit test f, skip if set BTFSS f,b,a Table read TBLRD* Table read with pre-increment TBLRD+* Table read with post-increment TBLRD*+ Table read with post-decrement TBLRD*- Table write TBLWT* Table write with pre-increment TBLWT+* Table write with post-increment TBLWT*+ Table write with post-decrement TBLWT*-
Bit-Oriented
Data <==> Program Memory
f = file register address d = destination select a = banck selectn&p = program address b = bit k = literal s = shadow reg.
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• CLRWDT: Watchdog timer and its postscaler are cleared.
/TO = 1 and /PD = 1
If WDT overflow resets the chipIf WDT overflow resets the chip
Instrucciones Especiales de los PICsCLRWDT
Instrucciones Especiales de los PICsCLRWDT
OverflowResetsChip
8-bit Ripple Counter Postscaler
CLRWDT
Internal free-running
RCOscillator
‘0’ ‘0’
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Instrucciones Especiales de los PICs SLEEP
Instrucciones Especiales de los PICs SLEEP
• The processor can be put into a power-down mode by executing the SLEEP instruction.
– System oscillator is stopped.– Processor status is maintained (static design).– I/O pins configured as output will continue to drive– Wake-up (WDT) and its postscaler are cleared.– /TO = 1 and /PD = 0.– Wake-up (WDT) timer continues to run, if enabled.– Minimal supply current is drawn - mostly due to leakage.
– Power-Down Current: 0.1 - 3.5A typical.– Device remain in power down until any wake-up.
OSC1
OSC2
SLEEP Osc.
Disable