:: milestone 4 2-d discrete cosine transform
DESCRIPTION
:: Milestone 4 2-D Discrete Cosine Transform. Group M2: Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan Kim Project Manager: Yaping Zhan. Team Paradigm. Project status. Design Proposal (Complete) Architecture Proposal (Complete) Behavioral Verilog and test bench (Done) - PowerPoint PPT PresentationTRANSCRIPT
M2: Team Paradigm
:: Milestone 4 2-D Discrete Cosine Transform
Group M2:Tommy Taylor Brandon HsiungChangshi XiaoBongkwan Kim
Project Manager: Yaping Zhan
M2: Team Paradigm
Team Paradigm
M2: Team Paradigm
Project statusDesign Proposal (Complete)Architecture Proposal (Complete): Behavioral Verilog and test bench (Done)Size estimates/floor plan (Complete): Structural Verilog (Done): Revised Floor plan (Done)Full-chip schematic (Done)Verilog verification of full-chip schematic
(almost missing 2d, have 1d)Critical Path Estimation
M2: Team Paradigm
Transistor count and performance estimation :
adder register ROM Control logic total pins
4x(15x24+14)=1500
18x16x15=4320
8x16x2=256
1000 ~10.5k 40
1DDCT module :
2DDCT = 2x1DDCT + SRAM ~ 29k
throughput latency
8 samples/64 cycle 528 cycle
Shift Register Muxes SRAM
mux(44x20)+ff(18x20)=1300
2000 7000
M2: Team Paradigm
Transistor Numbers
: mirror adder - 28: mirror adder 16 bit - 448: accumulator - 1076: and2 - 6: bit address gen - 960: compare3 - 4: compare15 - 14: control - 616: decode 2 4 - 78: eightbitcounter - 208: ff16 - 192: flipflop - 12: fourbitcompare0 - 14: fourbitcounter - 104
: p to s - 884: reg20bit - 240: shiftreg - 832: shiftreg20bit - 1200: sram sense amp - 5: statereg - 24: threebitcounter - 78: tranmission - 2: twobitcounter - 52: twobitmux2 - 28: xor2 - 8: halfadder - 14: midbuf - 1664
M2: Team Paradigm
Larger Components
: Control Logic (616)
M2: Team Paradigm
Larger Components
: In buffer (4226)
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Larger Components Breakdown
: Mirror Adder: (28): 16 bit – (448), 20 bit
(560)
M2: Team Paradigm
Larger Components
: Mid Buffer (960)
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Larger Components
: Bitaddress_Generator (960)
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Larger Components
: Shift Register 16bit (832), 20bit (1200)
M2: Team Paradigm
Larger Components: Accumulator (1076)
M2: Team Paradigm
Larger Components
: 1D Dct (14026)
M2: Team Paradigm
Larger Components
: Parallel to Serial (884)
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Larger Components
: 2d DCT (28200)
M2: Team Paradigm
Old layout proposal
Sub
Add
Control logic
rom
shift reg
16bi
t 1x8
dem
ux
16bit 4x1 mux
16bit 4x1 mux
reg
reg
reg
reg
reg
reg
reg
reg
16bit 1x4 demux
4bit 16x1 mux A
dd
rom A
dd
4bit 16x1 mux
16bit 1x4 demux
16bit2x1 mux
reg
reg
reg
reg
reg
reg
reg
eg
600u
150u
M2: Team Paradigm
Overall floorplan
1D DCT
1D DCT
16 x 64 SRAM
15050
100
600
500
500 x 600 = 300,000um2
M2: Team Paradigm
New Layout Proposal
rom
shift reg
reg
reg
reg
reg
4bit 16x1 mux A
dd
rom
shift regAdd
4bit 16x1 mux
16bit 4x1 mux
reg
reg
reg
reg
Add
regregreg
regregreg
regreg
Add
16bit 4x1 mux
ctrl
500u
200u
M2: Team Paradigm
Overall floorplan
1D DCT
1D DCT
16 x 64 SRAM
15050
100
500
500
500 x 600 = 300,000um2
M2: Team Paradigm
::conclusion & questions
: 29k too much?: How to simulate individual parts.