future of microelectronic technologies from single transistors to integrated imagers news from...

.CERN CERN Erik HEIJNE CERN EP - Div

FUTURE of MICROELECTRONIC

TECHNOLOGIES FROM SINGLE TRANSISTORS

to INTEGRATED IMAGERS

NEWS from INTERNATIONAL ELECTRON DEVICES

MEETING Washington, 2-5 Dec 2001

Erik H.M. HEIJNE CERN EP Division

BDI Forum 19 March 2002


SILICON TECHNOLOGY for

PARTICLE PHYSICSLOW NOISE ELECTRONICS

HIGH FUNCTIONAL DENSITYSMART READOUT

+SENSORS with

PRECISE GEOMETRY HIGH SPEED (ns)

APPLICATIONS for BEAM INSTRUMENTATION ?


CONTENTSSCALING MOS TRANSISTORS

PROSPECTS at IEDM 2001

TECHNOLOGY NODESSHORT TRANSISTORS

CMOS DESIGN for LHC EXPERIMENTS ‘QUANTUM’ IMAGING

RADIATION HARDNESS

DEVELOPMENTS in IMAGERS NEWS IEDM 2001& ISSCC 2002

EXAMPLES CCD PHILIPS cs

CCD LINCOLN LABS MIT(other)

DISCUSSION


HIGHLIGHTS

- TRANSISTORS with L= 15-25 nm

competition INTEL, IBM, AMD, ST

session 29 - CONVICTION that <30 nm is SOI

DIFFERENT APPROACHES

--> DOUBLE GATE

- MANY TECHNOLOGY CHANGES

GATE MATERIAL W, TiDIELECTRIC compounds,

mixtures ?INTERCONNECTS Cu, optical

CHANNEL Ultra-Thin, SON, SiGe

- MEMORY trench : AR 60, ~7 µm

- SYSTEM-on-a-CHIP : SOC- SENSORS 5 sessions

- NEW ROADMAP : ITRS 2001scaling accelerated


MOS TRANSISTOR

CURRENT

FIELD DRAIN

SOURCE

ACTIVE REGION

GATE poly-Si LENGTH L

WIDTH


MOS TRANSISTOR

~ 1985 : LENGTH FEW µm, OXIDE GATE 100 nm -->50 nm

LENGTH

POLYGATE WIDTH

DRAINSOURCE

CHANNEL(INVERSION LAYER)

GATE OXIDE

BULK Si


CARRIER TRANSIT TIME

Si : e 600 cm2/Vs 1 µm 2Vtransit time ~ 13 ps

SHORTER CHANNEL --> FASTER TRANSISTOR

SEVERAL LIMITING FACTORS

transit time τ ~ L2

μ VDS

SMALLER DIMENSIONS NEED HIGHER DOPING --> THEN µ IS DEGRADED

DRIFT VELOCITY SATURATES ETC.

SWITCHING SPEED DEPENDS ALSO ON INTERNAL + EXTERNAL CAPACITANCES


SPEED

Si : e 1500 --> 200 cm2/Vs

CARRIER MOBILITY vs DOPING

Si

GaAs

Ge


TRANSISTOR SCALING

INCREASE in SPEEDRF now POSSIBLE on Si

LOWER COST per FUNCTION

MORE FUNCTIONS on SAME AREA

SYSTEM on CHIP SoC


sub - 70 nm SHORT COURSE

DEVICE DESIGNYuan TAUR now UCSD

LITHOGRAPHY Luc Van den HOVE IMEC

PROCESS INTEGRATION ISOLATION, JUNCTIONS and SILICIDES Liang-Kai HAN TSMC

GATE DIELECTRICS and GATE MATERIALS

Hsing-Huang TSENG Motorola

MANUFACTURING and YIELDAT THE 70 nm NODE

Chris J. McDONALD INTEL


TECHNOLOGY NODES

SHORTER TRANSISTORS can be INTRODUCED as add-on

eg 70 nm in 130 nm NODE

NODES DEFINED BY LITHOGRAPHY

'SECUNDARY' CHANGES DEPEND ON FOUNDRY

eg Cu from 130 nm for IBMnon-SiO2 DIELECTRIC300 mm wafer size



Yuan TAUR CMOS SCALING


Gates Deep-submicron CMOS

New gate oxides ( < 2 nm ) have to be tested for radiation response

MOS Gate TEM Bell Labs April 2000

Si

SiO2 1.6 nm

Poly Si

Reliable oxides can be made alreadywith only ~ 6 atoms in SiO2 layer

SiO2 CMOS technology usedfor 0.08 µm --> 0.02 µm? transistors? NEW GATE METALS? NEW DIELECTRICS ! mobility


SHORT TRANSISTORS

HOW TO PREVENTSHORT CHANNEL

EFFECTS

NEED VERY HIGH DOPING

1019 cm-3 GOOD OFF-CURRENT

AT LOWER VDD

BETTER SERIES R

SUPER-HALO


INTEL 50nm ‘DST’DEPLETED SUBSTRATE TRANSISTOR

30 nm THIN Si SUBSTRATE on 200 nm OX

RAISED SOURCE & DRAIN REDUCE R

µn MOBILITY~ 300

HIGH Vt

EQUIVALENT GATE OXIDE 1.5 nm

NOTE REDUCTION µAt HIGH-FIELD 0.4 MV/cm

---> 2V/50nm


IBM sub-40nm SOISUB-40nm TRANSISTOR at 70nm NODE

>1000 µA /µm for nFET

OFF < 100 nA @ 1.1V Si SUBSTRATEnFET GATE DELAY 0.61 psfT 178 GHz

OFFSET SPACER REDUCES CovGATE OXIDE (equivalent) 1.9 nm


Deep-submicron CMOS

nMOS TRANSISTOR ST at IEDM 2001

Si channel

SiO2 2.75 nm

Poly SiGate L=16 nm

SiO2 CMOS technology still usedbelow 0.02 µm-->some incredulity


ST 80nm ‘SON’ MOSFET20nm Si on 20nm SiGe on Si BULKSiGe --> TUNNEL = ‘NOTHING’

SELECTIVE ETCHING of SiGe (30%)

BURIED ISOLATION of CHANNEL

CAN MAKEGATE OX 1.2 nmon 5 nm Si ‘cap’

GATE OXIDE 3 nm



Yuan TAUR MOSFET TRANSISTORS

THIN Si BETTER

NO HALO NEEDED


TRANSISTOR SCALING

INCREASE in POWERSEVERE LIMITATION

COST of PROCESS DEVELOPMENT

COST of SINGLE FOUNDRY > 2 G$TOO LARGE VOLUME ?


+

POWER DISSIPATION

PROCESSORS NEED COOLING

ALICE1 PIXEL CHIP 2.7 cm2 USES 0.6 to 0.9 W + 0.3 W cm- 2

PIXELS vs Si MICROSTRIP ~3 kW m- 2 vs 0.2 - 0.6 kW m- 2

CRYOGENIC OPERATION ?


PIXEL readout relies on Deep-submicron CMOS

Component density + 6 to 9 levels of interconnect

3 metals shown

length .35 µm

poly Si gate

Pixel chips at CERN now 0.25 µm

FUNCTIONS SPEEDLOW NOISE LOW POWER


DESIGN for PARTICLE PHYSICS

at CERN

EXAMPLE : PHOTON COUNTING

PIXELS COMPLICATED CHIP

0.25 µm CMOS +BUMP-BONDED SENSOR


Photon Counting Chip CERN

Amplifier-Shaper 1 µm SACMOSComparator 3-bit adjust16 bit counter common electronic shutterDark current compensation per column 10 nAReadout 384 µs

PCC1 64 x 64 PIXELS 170µm x 170 µm

1997



15 - bit COUNTERSTATIC LOGIC

170µm x 170 µm

THRESHOLD ADJUST using 3 bit TRIM

BumpbondingSi or GaAs sensor

400 transistors



5.9 keV : SOURCE 55Fe

EFFECT FLAT FIELD CORRECTION

Compensation for inhomogeneity :source geometrypixel size, window absorption, etc

low energy improves contrast



150 ns PEAKING TIME (linear < 0.4 MHz)

HIGH COUNT RATE

~ 109 s-1cm-2

Maximum occupancy ~ 50%

ELECTRONIC NOISE ~170 e- rms DARK CURRENT COMPENSATION

10 nA / pixel

30 µA cm-2

TEST SIGNAL INDIVIDUAL PIXELSMASKING of BAD PIXELS THRESHOLD ADJUSTABLE

DISTRIBUTION~120 e- rmsALLOWS LOW THRESHOLD

~1400 e- 5 keV READOUT TIME 384 µs per CHIP

SUMMARY



CELL 55µm x 55µm 504 TRANSISTORS

2nd GENERATION Medipix Collaboration

+ and - polarity 0.25 µm CMOSdark current compensation per pixel window discriminator with 3-bit adjusts

linear range 80 000 e-

13 bit counter + overflow STATIC LOGIC

count rate ~ 1011 cm-2

55 ?m

55 ?m


PHOTON COUNTING IMAGER

WINDOW DISCRIMINATOR

I D is c

I t hI t h / 2I t h / 4

B 2B 1B 0

O T A

V T H

V i n

D i s c O u t

F D L

I S e t D i s c

M a s k

ANALOG OUTPUT SIGNAL

17200 e -

UPPER COMPARATOR 16400

and LOWER 6300 e -


RADIATION HARDNESS

FOUND WAY TO GET 1-10 MGy

for TRANSISTOR CIRCUITS

IMAGERS ??


RADIATION EFFECTS

GATE THRESHOLD SHIFTionization in gate

oxide

SOURCE-DRAIN LEAKAGEionization in field

oxide

HEAVY IONIZATION EFFECTS SINGLE EVENT EFFECTS ‘SEE’

LATCH-UP

GATE RUPTURE

MEMORY UPSET, etc.


GATE THRESHOLD SHIFT

TUNNELING in THIN LAYER

NO CHARGING CLOSE TO

INTERFACE


GATE THRESHOLD SHIFT

N. SAKS cs. IEEE NS 31(1984) 1249

A to D measurements at CERN 1995-2000

~ 1/tox2

~ 1/tox3


MOS TRANSISTORAFTER IRRADIATION

NORMAL CURRENT

FIELD DRAIN

SOURCE

ACTIVE REGION

LEAKAGE CURRENTS PASSING UNDER BIRD’S BEAKS

GATE poly-Si


EDGE LEAKAGE N-MOS

CURRENT FROM SOURCE TO DRAIN PASSES UNDER FIELD OXIDE, TRANSISTOR CANNOT BE TURNED OFF


ENCLOSED TRANSISTORS

RADIATION TOLERANT BY LAYOUTONLY SMALL PENALTY IN DEEP SUBMICRON

OLD APPROACH (RCA ~1975)

N-MOS NEEDS P+GUARD RING FOR SEPARATION

SECTION VIEW

N-MOSP-MOS


SENSORS at IEDM 2001

MANY TYPES PRESENTED eg SENSOR for CAR TYRE PRESSURECMOS IMAGERS (also at ISSCC)

METAL PLATE as e-GENERATOR for ION IMAGING

CCD with MHz 'FRAME-RATE'4 STORAGE LOCATIONS : ISIS

(at ISSCC --> 100)

ALTERNATIVE MIT USES BACKSIDE +

STORAGE IN FRONT STRUCTURES

512 x 512 96x96 superpixels

8 subpixels -> 12 µm pitch has built-in shutterSOME FUNCTIONS CAN BE MADE in

CCD just like in 'our' PIXEL DETECTORSCCD NOW COMPETITIVE due to CAMERAS


SILICON TECHNOLOGY

VERY FAST DIODES

FORHIGH FREQUENCY FIBER

OPTICS


FAST DIODEIBM : Si on SOI

Fast Fourier Transform

VERTICAL TRENCHES


CCD IMAGING

MULTIPLE FRAMES (4-100)

HIGH SPEED (µs)

2 EXAMPLES


CCD with ~1 MHz MULTIPLE FRAME

STORAGE

FIRST TRY with ‘EXISTING’ CCDUSE SUBSET of SENSITIVE PIXELSUSE OTHERS for STORAGE


Dipl.-Ing (FH) Dirk Poggemann

Fachhochschule OsnabrückFachbereich Elektrotechnik

& Informatik© 2001

Fachhochschule Osnabrück

Entwicklung eines In-situ Storage Image Sensors (ISIS) für ein

Hochgeschwindigkeitskamerasystem

Osnabrück - Philips - Shimadzu- U. Osaka

In-situ Storage Image Sensor (ISIS) for High Speed Camera

Dipl.-Ing. (FH) Dirk PoggemannForschungsschwerpunkt “Intelligente Sensorsysteme”

(ISYS)Fachbereich Elektrotechnik & Informatik



ISIS V1

LOWER LEFT CORNER CCDMETAL + OPEN PIXELS

Dipl.-Ing (FH) Dirk Poggemann

Fachhochschule OsnabrückFachbereich Elektrotechnik

& Informatik© 2001


Entwicklung eines In-situ Storage Image Sensors (ISIS) für ein

Hochgeschwindigkeitskamerasystem

IMAGEBEFORESORTING

3%FILL-FACTOR


CCD 17 FRAMES

MECHANICAL SHUTTER DURING READOUT


CCD 17 FRAMES

NEEDS RE-ORDERING AFTER READOUT


IMPROVED CCD : ISIS V2

Horizontales Ausleseregister

Lichtempfindliches Pixel

Abgedecktes Speicherpixel

103 STORAGE PIXELSOVERWRITE (DRAIN)

PIXEL (ALL UNDER METAL)

LIGHT SENSITIVE ELEMENTS (LARGE, OPEN)



FILL FACTOR 13 %FULL WELL 40 000 eGREY LEVEL 10 bitsISSCC FEB 2002



MANUFACTURED CCD

DETAIL of PHOTOSENSITIVE SITES


CCD IMAGING

BUILT-IN SHUTTER

BLUE/UV-SENSITIVITY by BACKSIDE INCIDENCE


INTEGRATED CCD IMAGER LINCOLN LABS

IEDM 2001 (R.Reich et al.)

LARGE SIZE : 512 x 96 µm --> ~ 50 mm x 60 mm SUPER PIXEL holds 4 FRAMESFILL FACTOR ~ 100%


CCD IMAGER LINCOLNSUPER PIXEL DESIGN 2x4x12µm4-phase 96 µm square

SPECIAL METALLIZATION NEEDED for MHz BACK-ILLUMINATIONSi THICKNESS only 17 µmSHUTTER DIRECTS CHARGE TO SUBPIXEL

17 µm


CCD IMAGER LINCOLN

SHUTTER OPERATION

SPLIT IN 2 PARTS, DRIFT > 48 µm TOO SLOW for MHz


CCD IMAGER LINCOLNDETAILS SHUTTER IEEE ED 40 (1993) 1231

STEPPED p-BURIED LAYERS using 1.5 MeV IMPLANTS n+ SHUTTER DRAIN

SHUTTER 14-18 V


CCD IMAGER LINCOLN

SHUTTER EXTINCTION RATIO

SHUTTER RISE-FALL TIMES

17 µm Si

25 µm Si

~ 50 ns


512x512 CCD LINCOLN4 FRAMES :1x 40 ns PULSED LASER 460nm FILTER 550

nmINTEGRATION TIME 2 ms(EXTINCTION RATIO)

4 FRAMES :CONTINUOUS 40 ns

SHUTTER OPEN 4 FRAMES 4x 520 ns + 100 ns

1.612 MHzEFFECTIVE

OPEN 350 ns CLOSE 150 ns


MONOLITHIC CMOS IMAGERS

'ACTIVE' CIRCUIT in PIXEL at least 1 TRANSISTOR (E. Fossum)

USUALLY 'SIMPLE' INTEGRATOR

MORE FLEXIBILITY for USER than CCD SOLUTIONS for LARGE DYNAMIC RANGE

LOGARITHMIC CHARGE STORAGEADAPTED INTEGRATION TIME

LESS FLEXIBILITY in PROCESSINGCMOS FOUNDRY LINES 1000 WAFERS/DAY

IMAGERS MAY NEED SPECIAL SUBSTRATES

HYBRID CMOS IMAGING ALTERNATIVE


CMOS LARGE DYNAMIC RANGE

POTENTIALLY 138 dB

IRST Trento

SINGLE-PIXEL INTEGRATION ADAPTED TO ILLUMINATION

FILL FACTOR 11%

TOTAL PIXEL25 µm x 25 µm24 transistors

COMMUTATION TIMEin ANALOG MEMORY

or INT. CHARGE


IEDM 2001 IMPRESSIONS

REDUCED ATTENDANCE : 970 instead of usual 1800 - 2200

41 SESSIONS a.m. 6, p.m. 7 papersALL PAPERS 25 min (ISSCC 30’ or 15’

in 26 sessions)

strong selection, many time slots not filled

2 SHORT COURSES Sunday 2 Dec 1. TECHNOLOGY for sub-70 nm

2. ADVANCEDE MEMORY TECHN & ARCHITECTURE more popular

INDUSTRY MOVEMENTS : e.g. PHILIPS RESEARCH --> IMECCONCENTRATIONS in IMAGING


CONCLUSION

ACCELERATION of SCALING COMPARED to ROADMAP

ENORMOUS PROGRESS in ONE YEAR RESEARCH in INDUSTRY NOT MUCH AFFECTED BY DOWNTURN

COMPLICATED TECHNOLOGIESECONOMICS MAKE COMPLICATION ACCEPTABLE

--> SOI, SON etc

SYSTEM-on-a-CHIP with RF etc

SENSORS : both CCD and CMOS

future of microelectronic technologies from single transistors to integrated imagers news from...

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